MM58167B Real Time Clock Design Guide MM58167B real-time 24-hour
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MM58167B Real Time Clock Design Guide
MM58167B Real Time Clock Design Guide
MM58167B real-time 24-hour format clock with input output structure control lines that facilitate interfacing microprocessors provides reliable source calendar data from milliseconds through months well bytes plus nibbles which available user alarm (compare) interrupt used MM58167B features power consumption (typically microamperes 3-volt supply) during battery backed mode flexible interrupt structure (alarm repetitive) fast internal update rate kHz) Systems utilizing this device include personal computers process control security data acquisition This application note covers hardware interface microprocessors clock interrupts oscillator operation accuracy calibration techniques software battery back-up considerations
TRI-STATE registered trademark National Semiconductor Corp NSC800is trademark National Semiconductor Corp
National Semiconductor Application Note Milt Schwartz March 1991
Hardware Description Overview
Figure functional block diagram MM58167B subdivided into following sections Oscillator oscillator consists internal inverter which user connects crystal bias resistor capacitors form Pierce parallel resonant circuit Prescaler prescaler divides oscillator down using pulse swallowing techniques pulse rate incrementing signal timekeeping counters
Block Diagram
AN-353
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FIGURE
C1995 National Semiconductor Corporation 5727 RRD-B30M105 Printed
Hardware Description Overview (Continued)
Timekeeping Counters timekeeping section consists 14-stage counter each stage having read write capability counters keep time 24-hour format Figure shows counter detail calendar-date-time format Rollover Status rollover status (read only) informs user that invalid data have been read counters being incremented during counter read between successive counter reads This situation occurs because counters clocked asynchronously with respect microprocessor nibbles provided alarm (compare) interrupt general storage nibbles packed address except locations address (HEX) nibble address appears high order bits while nibble address appears order bits memory Figure details Address Milliseconds Tenths Seconds Tens Seconds Tens Minutes Tens Hours Exists Tens Month Tens Months Exists Hundredths Seconds Units Seconds Units Minutes Units Hours Week Units Month Units Months Input Output Control Lines input output structure consists 5-bit address 8-bit bidirectional data control lines chip select power down read write addition ready output provided those microprocessors that have wait-state capability meet timing requirements ready signal power down input acts chip select opposite polarity differs from chip select that will TRI-STATE main interrupt output while chip select does TRI-STATE interrupt power down input intended facilitate deselecting chip battery backed operation Chip select read write active controls ready output active open drain caused chip select negative-going-edge read write internal one-shot) ready output used control line when interfacing microprocessor left open circuit
Detail Descriptions
OSCILLATOR Figure represents internal external circuitry that comprise oscillator inverter which heart oscillator designed consume minimum power inverter typical gain oscillator input driven from external source this desired input should swing rail-to-rail approximately duty cycle oscillator output open circuit this case external oscillator circuit constructed using CMOS inverter N-FET (see Figures Referring Figure external resistor biases inverter active region internal feedback resistor large value guarantee reliable biasing external series resistor protect crystal from being overdriven possibly damaged Manufacturers these crystals specify maximum power that crystal dissipate this rating which determines what value series resistor should used external capacitors effectively series with each other (from viewpoint) This total value comprises load capacitance (typically picofarad) specified crystal manufacturer crystal's oscillating frequency rule thumb choosing these capacitors load capacitance greater than (typically four times) usually trimmed obtain 32768 Hertz frequency start-up time this oscillator vary from seven seconds (empirical observation) high ``Q'' crystal Typical waveform values monitored oscillator output observed volts peak peak riding volt level (for volts) CHOOSING CRYSTAL below parameters describe crystal used Parallel Resonant tuning fork cut) Load Capacitance (CL) Power Rating Accuracy Temperature Coefficient Picofarad Microwatt User Choice User Choice
FIGURE Memory Comparator 46-bit comparator compares values against counters provide alarm (compare) interrupt When compare occurs main interrupt will activated interrupt control register standby interrupt will activated ``1''was written address Interrupt Hardware Interrupt hardware consists interrupt outputs main interrupt standby interrupt main interrupt active high push-pull output standby interrupt active open drain output main interrupt 8-bit control register allows user select from interrupt rates well alarm 8-bit status register informs user which interrupts occurred one-bit control register enables disables standby interrupt standby interrupt activated only alarm condition 46-bit comparator matches timekeeping counters against alarm interrupt
Detail Descriptions (Continued)
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FIGURE Oscillator Circuit Recommended Connections
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FIGURE
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FIGURE When used with crystal accuracy oscillator circuit over voltage temperature about Voltage variations cause about inaccuracy temperature variations account other half This inaccuracy results error about minutes year Errors external components must taken into account user external oscillator used then determines accuracy clock oscillator input (pin high impedance node that susceptible `noise' usual result clock gains time high rate order seconds hour greater) This noise usually result coupling from which order address tied directly microprocessor Suggestions alleviate this condition Gate with chip select slow rise fall time inverting buffer such CMOS drive this choice made similar CMOS should drive write read strobes avoid timing conflicts external oscillator drive with impedance device (CMOS transistor) leave open circuit Connect oscillator components close possible pins CALIBRATION calibrate oscillator following method suggested second repetitive interrupt activated This done first connecting interrupt (pin clock interrupt microprocessor Next short program written that sets interrupt control register then enters loop that wastes time while awaiting interrupt interrupt service routine only needs read interrupt status register which clears interrupt then returns result second periodic signal flow chart Figure example detail steps time event meter used measure time interval between successive positive going edges interrupt output while adjusting variable capacitor This period will second when oscillator Hertz
Detail Descriptions (Continued)
dropping three pulses every counts Hertz signal resulting then divided produce which internal incrementer rest timekeeper This waveform nonmonotonic with respect individual periods result there short long periods within second interval short period 1024 seconds long period 1024 32768 seconds result milliseconds hundredths tenths seconds ``jitter'' inaccuracy individual period basis about microseconds period number clock edges correct over second within accuracy crystal oscillator thousandths seconds counter referred data sheet counts milliseconds second slower signals jitter free Refer Figure counter block diagram TIMEKEEPING COUNTERS timekeeping counters intended work with valid values general illegal codes entered then guarantee given recovery shown Figure timekeeping stages arranged ripple counter month month week counters count through milliseconds through hours counters count through rollover counter stage increments next higher order counter This rollover takes place when highest allowed value plus decoded example 30-day month month counter would decode value reset increment month counter highest allowed value plus written counter counter will reset when write removed ``may'' increment next higher order counter example February written clock read back will ``1'' month counter month read ``3'' However leap year February written this done (hours through milliseconds) then clock will read March after hours this value could used indication that date really Refer Figures flowcharts program alarm interrupt that take leap year into account Note that software implemented leap year counter accurate least through year 2048 perpetual calendar more sophisticated algorithm would needed
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FIGURE Flow Chart Calibration Using Repetitive Interrupt Hertz measured directly then impedance capacitance amplifier comparator CMOS gate should connected oscillator output prevent measuring instrument from offsetting frequency oscillator This addition permanently part oscillator circuit must battery backed clock battery backed reason battery backing this buffer ensure that input impedance does change during power down operation which could result oscillator stopping being offset frequency PRESCALER OPERATION Hertz signal divided even Hertz using pulse swallowing techniques This accomplished
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FIGURE Timekeeping Counters
Note Initialize state counter first power least significant bits week four state software counter least significant bits millisecond FLAG FLAG Leap year relative March This program requires that system powered clock read once during February once during March Clock battery backed
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FIGURE Leap Year Flow Chart
Note three least significant bits millisecond five-state software counter leap year first power leap year counter initialized
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FIGURE Leap Year Flow Chart Hardware
Function Milliseconds Hundredths Tenths Seconds Seconds Minutes Hours Week Month Months
Address
DATA Nibble Nibble Exists
Exists
FIGURE Clock Alarm Interrupt March
INTERRUPTS MM58167B interrupt output pins main interrupt (pin active ``high'' active when power down ``high'' When power down (pin main interrupt output TRI-STATE second interrupt ``standby interrupt'' active open drain requiring pull resistor This interrupt always powered Refer Figure typical sink current versus voltage characteristics Separate control bits exist interrupts main interrupt offers modes operation which combined Mode interactive repetitive interrupt this case logic written more bits control register (address hex) from through logic written into position Refer Figure configuration interrupt control status registers
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FIGURE Typical Curve Standby Interrupt result clock chip provides interactive repetitive interrupt that occurs when selected counter rolls over That user must clear interrupt next recognized This done reading interrupt status register (address hex) This read results user obtaining interrupt status (which interrupt occurred)
clearing interrupt output well status register positive-going-edge read strobe which causes preceding This clearing action precludes polling status register precision timing positivegoing-edge repetitive interrupt should used trigger one-per-second through one-per-month repetitive interrupts will accurate setting crystal oscillator ten-per-second interrupt will accurate about microseconds Refer prescaler description more detail second mode main interrupt ``compare'' ``alarm'' this case specific value entered clock When time keeping counter(s) match that value interrupt becomes active Refer Figure typical example Figures show internal interrupt logic waveforms addition specific time interrupt (alarm) repetitive interrupt achieved reprogramming selected location with future event value rule thumb ``alarm'' interrupt nibbles higher order than specified (always compare) nibbles lower than specified ``zero'' programming example fastest interrupt rate obtainable (500 second) given Figure This program written NSC800code (Z80) sets ``always compare'' conditions hex) locations through location which corresponds week counter single digit) location When first interrupt occurs service routine reads status register sets value into location succeeding interrupts values into location sequence repeats interrupt activated interrupt occurs during battery backed operation (power down) main interrupt output will active high when system power returns
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FIGURE Interrupt Registers Logic
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FIGURE Internal Interrupt Timing
Address Function Milliseconds Hundredths Tenths Seconds Seconds Minutes Hours Week Month Months Nibble
DATA Nibble
Exists
Exists
FIGURE Mapping Alarm Interrupt Every
NAME ('I500Hz') TITLE 58167 500HZ REPETITIVE INTERRUPT THIS PROGRAM WITH 58167 POWER DOWN BOARD INTERFACED NSC888 BOARD CODE NSC800 500HZ SIGNAL GENERATED INTERRUPT (13) THIS SIGNAL GENERATED USING COMPARE INTERRUPT UPDATING ''RAM'' NEXT INTERRUPT
0800H 4092 4091 4090 408F 408E 408D 408C 408B 408A 4089 4088 101C 101D RESET CONT STAT VEC1 VEC2 04092H 04091H 04090H 0408FH 0408EH 0408DH 0408CH 0408BH 0408AH 04089H 04088H 0101CH 0101DH
0800' 0802' 0805' 0807' 080A' 080C' 080E' 0811' 0813' 0816' 0818' 081B' 081E' 0820' 0823' 0826' 0829' 082C' 082F' 0832' 0835' 0837' 083A' 083C' 083E' 0840' 0841'
101C 101D 1FFF 4092 4091 4090 408F 408E 408D 408C 408B 408A 4089 4088 4091
INIT
0840
WASTE TIME AWAITING INTERRUPT INTERRUPT SERVICE ROUTINE GETS VALUE MILLISECOND TEST THEN EQUAL CLEAR INTERRUPT RETURN MILLISECOND CLEAR INTERRUPT RETURN ''REMEMBER'' MILLISECONDS ''HIGH'' ORDER NIBBLE ONLY 0900H
(VEC1) 009H (VEC2) (0BBH) 01FFFH 0FFH (Reset) (CONT) (STAT) 0CCH (MON) (DOM) (DOW) (HRS) (MIN) (SEC) (HT) (MIL) (CONT)
INTRPT NSC888
INIT STACK POINTER RESET CLOCK COUNTERS CLEAR INTRPT CONTROL CLEAR PENDING INTRPT INTRPT
COMPARE INTRPT
0900' 0903' 0905' 0907' 090A' 090C' 090F' 0912' 0914' 0917' 091A' 091B'
4088 0912' 4088 0917' 4088 4090
ZERO RETRN
(MIL) 0F0H 080H ZERO 020H (MIL) RETRN (MIL) (STAT)
MILLSEC MASK
CLEAR INTRPT
FIGURE NSC800 Assembly Code Interrupt
STANDBY INTERRUPT ``1'' written address enables standby interrupt ``0'' disables This interrupt also becomes active when match exists between time keeping counter(s) value written into standby interrupt cleared soon recognized user should ensure that delay millisecond greater exists prior reenabling standby interrupt This delay necessary because internal signal level which causes interrupt this delay does occur then standby interrupt becomes reactivated until internal latched compare goes away which occurs next clock Figure illustrates interrupt timing organized shown Figure There bits each counter used general purpose alarm interrupt possible under certain conditions perform compare interrupt selected bits general purpose storage position that `always compare' condition allows user manipulate order bits each nibble However high order bits each nibble position must maintained logic example user have alarm interrupt that does week condition interrupt Therefore order bits might used state software counter keep track leap year Reading writing same standard HARDWARE INTERFACE CONSIDERATIONS There four basic methods interfacing MM58167B microprocessor They memory mapped microproc-
essor ports (for single chip microprocessors like 8048) peripheral adapter separate latches advantage memory mapped interface memory reference instructions disadvantages processor need ``wait-stated'' environment noisier with respect crystal oscillator Refer Figure typical interface Microprocessors that have separate ports sufficient) offer capability interface directly without ``wait-stating'' additional device count Eight port bits (data) need bidirectional this interface Figure indicates port interface Programmable peripheral interface devices such 8255A NSC810 afford user advantage timing control data manipulation well less noisy environment with respect oscillator circuit Figure depicts 8255A NSC810 interface External latches used place programmable peripheral interface device This results higher package count easier troubleshooting Also latches have manipulated through control register Figure illustrates external latch approach peripheral approaches address data chip select read write strobes manipulated controlling data bits program execution peripheral interface approach facilitates calibration oscillator because chip select read strobe address lines steady state logic levels Refer calibration techniques more detail
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FIGURE Typical Interface
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FIGURE MM58167B Interfaced Single Chip Microcomputer
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FIGURE MM58167B Interfaced Through Peripheral Adapter
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FIGURE MM58167B Interfaced Using TRI-STATE Latches
POWER DOWN BATTERY BACKED CONSIDERATIONS Battery back clock considered user maintain time during power failure provide ``wake-up'' alarm save time that power failure occurred calculate long power failure lasted first step providing battery backed system isolate system supply from battery This ensure that battery discharged system supply when power failure occurs Figure shows techniques achieve isolation Figure implemented using diodes isolate case Schottky diode used guarantee minimum voltage drop loss while other case adjustable voltage regulator (LM317) used from higher voltage regulated about volts 1N914 diode series with regulator achieves volts clock Schottky diode drop about volts Thus clock typically volts user must cautious about input signals exceeding volt since clock CMOS device This situation could arise devices driving inputs clock were CMOS received power from volt system supply Figure makes
saturation transistor volt) take care above situation transistor used achieve isolation zener diode ensures that circuit stops conducting appears open circuit before battery switches Some basic considerations must adhered power down situation where real time clock battey backed ensure spurious write strobes accompanied chip select occur during power down power Another guarantee system stable when selecting deselecting clock Also legitimate write-in-progress should completed accomplish this hardware implemented such that early power failure detected (usually comparator detects failure retriggerable one-shot detects failure) Figures this point clock chip deselected worst case power fails faster than detection circuit cause deselection When power returns hardware detects power system must stable before communication allowed with real-time-clock
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FIGURE Isolating System Supply from Battery
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FIGURE Sensing Failure Using Comparator
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FIGURE Sensing Line Failure Using Retriggerable Shot 5-volt system supply rise fall time characteristics during power turn power failure must known Care should taken allow legitimate write progress completed This necessary because ``short write'' could cause erroneous data entered clock clock used ``read only'' device (except initialization calendar time) circuitry allow write progress completed does have considered this situation switch series with write strobe could implemented such that write line clock ``tied high'' after initialization sense system power failure comparator voltage reference used Figure detail shows comparator voltage reference configured such that comparator output ``low'' when 5-volt system power greater than volts possible power fail trip point should referenced lightly loaded (fast collapse) supply preferably higher than 5-volt system This would allow early sense power failure When using comparators output oscillate trip point approached oscillation caused noise line appearing input comparator when near trip voltage cleaner supply less chance oscillation cases hysteresis should used minimize oscillations Note that kohm pull-up resistor connected battery backed node while LM139 connected 5-volt system supply Used this comparator does draw current except leakage from battery output remains high during power down sense failure retriggerable one-shot used time adjusted allow more cycles Hertz missed Using this approach output one-shot always high while Hertz present When cycle missed one-shot times goes Figure shows sensing This technique could cause spurious deselect clock ``glitch'' occurs line resulting missed cycle this application circuit shown Figure implemented MM58167B interfaced NSC800 memory mapped locations demo program written exercise clock display time date calendar Power switched irregular intervals test battery backed circuitry results were that clock kept correct time Battery backed current circuitry microamp general consideration this circuitry allows chip select progress completed FUNCTIONAL OPERATION FIGURE Power sequencing consists LM139 (comparator) making high transition when 5-volt system supply exceeds volts This transition triggers second one-shot causing output removes reset flip-flop through nand gate output microsecond one-shot ``don't care'' once comparator switches from high After seconds system assumed stable flip-flop output which reset clocked high high transition second one-shot Thus clock chip enabled allowing normal communication with microprocessor power down sequence consists comparator making high transition when 5-volt supply less than volts chip select present flip-flop reset through nand gate causing clock (deselected) legitimate chip select progress reset action through nand gate would delayed level 2-microsecond one-shot
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FIGURE Detailed Schematic Power Down Circuitry Interface NSC888 Board
wait state generator implemented using chip select sensing signal This necessary comply with NSC800 wait state timing wait generator provides microseconds access time which more than adequate meet clock chip timing requirements Pull-down resistors were added clock input pins guarantee floating inputs during power down This ensures that CMOS clock does draw excessive current from battery during power down diode isolates 5-volt system from battery 4-volt Tadiran nonrechargeable lithium cell used this application) battery isolated from 5-volt supply using circuit comprised transistors along with zener diode zener diode value selected such that combined voltage drop zener base emitter transistor greater than battery voltage This ensures current will drawn from battery 5-volt supply when power failure occurs battery rechargeable allows microamps charge current without damaging cell LM139 voltage comparator LM385-2 voltage reference were used sense 5-volt system supply trip point adjusted such that when 5-volt supply dropped volts comparator switched from high Observation comparator output showed oscillation caused malfunction duration oscillation about microseconds Burst noise 5-volt supply about volts peak peak circuitry implemented 5-volt supply should fall faster than volt millisecond This rate allows microseconds deselect take place while supply falling from volts volts Thus deselect occurs while system stable
RESET COMMAND Writing value address causes hours through milliseconds counters reset zero week month month counters Writing value address causes cleared GENERAL TIMING CONSIDERATIONS guarantee valid read write without using ready output following criteria must Read Operation When reading deselect time nanoseconds must occur between counter reads Read strobe width must exceed microseconds deselect condition (RD) (WR) Address setup before Read strobe width Address hold after read Deselect time Write Operation Address before data must coincident Data hold after Address hold after ready output used guarantee read write operation then following recommendations made Referencing April 1982 data sheet during read ready line makes positive transition nanoseconds before data valid (Not shown data sheet user should this signal latch data into external latch this signal used wait state microprocessor then critical examination microprocessor timing with respect when terminates wait stated cycle must made This examination must also include set-up time processor needs prior reading data Also note that ready output (per data sheet) negative-going-edge occurs nanoseconds after read write strobe gone Check microprocessor timing ensure that ready signal would recognized ``wait-signal'' advised perform sequential reading connecting chip select read cycling through counters changing address lines reason that possible cause internal latch ``flip result being error timekeeping
Miscellaneous
TEST MODE test mode applies oscillator output input millisecond counter This affords faster testing chip This mode intended factory testing where programmable pulse generator used pulse rate used this mode pulse should swing rail rail square wave Apply pulses oscillator input leaving oscillator output open circuit basic sequence would write values counters enter test mode apply known number pulses Next read counters using normal read sequence COMMAND write address (data ``don't care'') will clear seconds through milliseconds counters value seconds counter equal greater than when command executed then minute counter will incremented
SOFTWARE CONSIDERATIONS Reading Counters read counter plus rollover status counters plus rollover must done within microseconds rollover status ``1'' then complete read counter(s) must performed again microsecond value conservative time between read counter(s) rollover status exceeds microseconds then status will always order reading must counter(s) first then rollover status This because positive going edge read strobe clears status Refer Figure status enabled period microsecond maximum rate during this microsecond period counter(s) read occurs status will This true matter often rollover status read during that time period Each rollover status read resets status counter read within microsecond period will rollover status counters read after repetitive interrupt then allow microseconds (conservative) from sense interrupt read counters (ripple delay time) data will valid counters read after compare interrupt read occur immediately will valid
Writing Counters counters written order because write overrides internal increment desired write counters without increments occurring between writes then complete write operation must performed within microseconds long valid values (with respect specific counter) written other counter affected write general writing high order order counters conservative approach This method less susceptible increments between writes cases where writing takes greater than microseconds initialization time ``GO'' command issued prior write then milliseconds available write from months through tenths hundredths seconds without effect internal incrementing BIBLIOGRAPHY MM58167B Microprocessor Real Time Clock Data Sheet April 1982 ``Crystal Oscillator Design Temperature Compensation'' Marvin Frerking National Semiconductor Application Note AN-313 Electrical Characterization High Speed CMOS Logic LM-139 Quad Voltage Comparator Data Sheet
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FIGURE Rollover Status Logic
MM58167B Real Time Clock Design Guide
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AN-353
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