PCnetTM-PCI Single-Chip Ethernet Controller Local DISTINCTIVE CHA
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Am79C970
PCnetTM-PCI Single-Chip Ethernet Controller Local
DISTINCTIVE CHARACTERISTICS
Single-chip Ethernet controller Peripheral Component Interconnect (PCI) local Supports 8802-3 (IEEE/ANSI 802.3) Ethernet Standards Direct interface local Compliant local specification (Revision 2.0) Software compatible with AMD's Am7990 LANCE, Am79C90 C-LANCE, Am79C960 PCnet-ISA, Am79C961 PCnet-ISA+, Am79C965 PCnet-32, Am79C900 ILACCregister descriptor architecture Compatible with Am2100/Am1500T Novell® NE2100/NE1500 driver software High-performance Master architecture with integrated Buffer Management Unit utilization endian byte alignment supported Single power supply operation Low-power, CMOS design with sleep modes allows reduced power consumption critical battery powered applications Green MicrowireEEPROM interface supports jumperless design Individual 136-byte transmit 128-byte receive FIFOs provide frame buffering increased system latency, support following features:
Advanced Micro Devices
Automatic retransmission with FIFO reload Automatic receive stripping transmit padding (individually programmable) Automatic runt packet rejection Automatic deletion received collision frames Look-Ahead Packet Processing (LAPP) concept allows protocol analysis begin before receive frame Integrated Manchester Encoder/Decoder Provides integrated Attachment Unit Interface (AUI) 10BASE-T transceiver with automatic port selection Automatic Twisted-Pair receive polarity detection automatic correction receive polarity Optional byte padding long-word boundary receive Dynamic transmit generation programmable frame-by-frame basis Internal/external loopback capabilities Supports following types network interfaces: external 10BASE2, 10BASE5,10BASE-T 10BASE-F Internal 10BASE-T transceiver with Smart Squelch Twisted-Pair medium NAND Tree test mode connectivity testing printed circuit boards 132-pin PQFP package
GENERAL DESCRIPTION
PCnet-PCI single-chip 32-bit Ethernet controller highly integrated Ethernet system solution designed address high-performance system application requirements. flexible bus-mastering device that used application, including network-ready PCs, printers, modems, bridge/router designs. bus-master architecture provides high data throughput system system utilization. PCnet-PCI controller fabricated with AMD's advanced low-power CMOS process provide operating standby current power sensitive applications. 1-868 PCnet-PCI controller complete Ethernet node integrated into single VLSI device. contains interface unit, buffer management unit, IEEE 802.3-defined Media Access Control (MAC) function, individual 136-byte transmit 128-byte receive FIFOs, IEEE 802.3-defined Attachment Unit Interface (AUI) Twisted-Pair Transceiver Media Attachment Unit (10BASE-T MAU), Microwire EEPROM interface. PCnet-PCI controller also register compatible with LANCE (Am7990) Ethernet controller, C-LANCE (Am79C90) Ethernet controller, ILACC (Am79C900) Ethernet controller, Ethernet
Publication# 18220 Rev. Issue Date: June 1994 Amendment
This document contains information product under development Advanced Micro Devices, Inc. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
PRELIMINARY controllers PCnet Family, including PCnet-ISA controller (Am79C960), PCnet-ISA+ controller (Am79C961), PCnet-32 controller (Am79C965). buffer management unit supports LANCE, ILACC, PCnet descriptor software models. PCnet-PCI controller software compatible with Novell NE2100 NE1500 Ethernet adapter card architectures. addition, Sleep function been incorporated provide standby current, excellent notebooks Green PCs. 32-bit multiplexed interface unit provides direct interface local applications, simplifying design Ethernet node system. With built-in support both little endian byte alignment, this controller also addresses proprietary non-PC applications. PCnet-PCI controller supports auto configuration configuration space. Additional PCnet-PCI
controller configuration parameters, including unique IEEE physical address, read from external non-volatile memory (serial EEPROM) immediately following system RESET. controller also capability automatically select either port Twisted-Pair transceiver. Only interface active time. individual transmit receive FIFOs optimize system overhead, providing sufficient latency during frame transmission reception, minimizing intervention during normal network error recovery. integrated Manchester encoder/decoder (MENDEC) eliminates need external Serial Interface Adapter (SIA) system. addition, device provides programmable on-chip drivers transmit, receive, collision, receive polarity, link integrity jabber status.
BLOCK DIAGRAM
802.3 Core CI+/DI+/XTAL1 XTAL2 DO+/RXD+/10BASE-T TXD+/TXP+/LNKST/EEDI
AD[31:00] C/BE[3:0] FRAME TRDY IRDY STOP LOCK IDSEL DEVSEL PERR SERR INTA
FIFO
Manchester Encoder/ Decoder (PLS) Port Interface Unit FIFO
NOUT FIFO Control
Microwire Control
EECS EESK/LED1 EEDO/LED3
Buffer Management Unit
18220C-1
Am79C970
1-869
TABLE CONTENTS
DISTINCTIVE CHARACTERISTICS 1-868 GENERAL DESCRIPTION 1-868 BLOCK DIAGRAM 1-869 RELATED PRODUCTS 1-870 CONNECTION DIAGRAM 1-871 ORDERING INFORMATION 1-872 DESIGNATIONS 1-879 Listed Number 1-879 Listed Group 1-880 Driver Type 1-881 DESCRIPTION 1-882 Interface Board Interface Microwire EEPROM Interface Attachment Unit Interface Twisted-Pair Interface Test Interface Power Supply Pins 1-882 1-884 1-885 1-886 1-886 1-886 1-886
BASIC FUNCTIONS 1-887 System Interface Function 1-887 Software Interface 1-887 Network Interfaces 1-887 DETAILED FUNCTIONS 1-888 Interface Unit (BIU) 1-888 Acquisition Master Transfers Target Initiated Termination Master Initiated Termination Initialization Block Transfers Descriptor Transfers FIFO Transfers Slave Transfers Slave Configuration Transfers 1-888 1-889 1-894 1-897 1-900 1-901 1-904 1-909 1-911
Buffer Management Unit (BMU) 1-913 Initialization Re-Initialization Buffer Management Descriptor Rings Descriptor Ring Access Mechanism Polling Transmit Descriptor Table Entry (TDTE) Receive Descriptor Table Entry (RDTE) 1-913 1-913 1-913 1-913 1-914 1-916 1-916 1-918
Media Access Control 1-918 Transmit Receive Message Data Encapsulation 1-918 Media Access Management 1-920 Manchester Encoder/Decoder (MENDEC) 1-922 External Crystal Characteristics 1-922 External Clock Drive Characteristics 1-922 1-870 Am79C970
PRELIMINARY MENDEC Transmit Path Transmitter Timing Operation Receiver Path Input Signal Conditioning Clock Acquisition Tracking Carrier Tracking Message Data Decoding Differential Input Terminations Collision Detection Jitter Tolerance Definition Attachment Unit Interface (AUI)
1-922 1-922 1-922 1-922 1-922 1-922 1-924 1-924 1-924 1-925 1-925 1-925
Twisted-Pair Transceiver (T-MAU) 1-925 Twisted-Pair Transmit Function Twisted-Pair Receive Function Link Test Function Polarity Detection Reversal Twisted-Pair Interface Status Collision Detect Function Signal Quality Error (SQE) Test (Heartbeat) Function Jabber Function Power Down 10BASE-T Interface Connection 1-925 1-925 1-925 1-926 1-926 1-927 1-927 1-927 1-927 1-927
Power Savings Modes 1-928 Software Access 1-928 Configuration Registers 1-928 Resources 1-929 Register Access 1-931 Hardware Access 1-933 PCnet-PCI Controller Master Accesses 1-933 Slave Access Resources 1-934 EEPROM Microwire Access 1-935 Transmit Operation 1-938 Transmit Function Programming Automatic Generation Transmit Generation Transmit Exception Conditions 1-938 1-938 1-939 1-939
Receive Operation 1-940 Receive Function Programming Automatic Stripping Receive Checking Receive Exception Conditions 1-940 1-940 1-941 1-941
Loopback Operation 1-941 Support 1-942 H_RESET, S_RESET, STOP 1-943 H_RESET 1-943 S_RESET 1-943 STOP 1-943 NAND Tree Testing 1-944 Am79C970 1-871
USER ACCESSIBLE REGISTERS 1-947 Configuration Registers 1-948 Vendor Device Register Command Register Status Register Revision Register Programming Interface Register Sub-Class Register Base-Class Register Latency Timer Register Header Type Register Base Address Register Interrupt Line Register Interrupt Register 1-948 1-948 1-949 1-949 1-951 1-951 1-951 1-951 1-951 1-951 1-951 1-952 1-952
Register 1-952 RAP: Register Address Port 1-952 Control Status Registers 1-952 CSR0: PCnet-PCI Controller Status Register CSR1: IADR[15:0] CSR2: IADR[31:16] CSR3: Interrupt Masks Deferral Control CSR4: Test Features Control CSR6: RX/TX Descriptor Table Length CSR8: Logical Address Filter, LADRF[15:0] CSR9: Logical Address Filter, LADRF[31:16] CSR10: Logical Address Filter, LADRF[47:32] CSR11: Logical Address Filter, LADRF[63:48] CSR12: Physical Address Register, PADR[15:0] CSR13: Physical Address Register, PADR[31:16] CSR14: Physical Address Register, PADR[47:32] CSR15: Mode Register CSR16: Initialization Block Address Lower CSR17: Initialization Block Address Upper CSR18: Current Receive Buffer Address Lower CSR19: Current Receive Buffer Address Upper CSR20: Current Transmit Buffer Address Lower CSR21: Current Transmit Buffer Address Upper CSR22: Next Receive Buffer Address Lower CSR23: Next Receive Buffer Address Upper CSR24: Base Address Receive Ring Lower CSR25: Base Address Receive Ring Upper CSR26: Next Receive Descriptor Address Lower CSR27: Next Receive Descriptor Address Upper CSR28: Current Receive Descriptor Address Lower CSR29: Current Receive Descriptor Address Upper CSR30: Base Address Transmit Ring Lower CSR31: Base Address Transmit Ring Upper CSR32: Next Transmit Descriptor Address Lower CSR33: Next Transmit Descriptor Address Upper CSR34: Current Transmit Descriptor Address Lower CSR35: Current Transmit Descriptor Address Upper CSR36: Next Receive Descriptor Address Lower CSR37: Next Receive Descriptor Address Upper 1-872 Am79C970 1-952 1-955 1-955 1-955 1-957 1-959 1-960 1-960 1-960 1-960 1-960 1-960 1-961 1-961 1-963 1-963 1-963 1-963 1-963 1-963 1-963 1-963 1-964 1-964 1-964 1-964 1-964 1-964 1-964 1-964 1-965 1-965 1-965 1-965 1-965 1-965
PRELIMINARY CSR38: Next Transmit Descriptor Address Lower CSR39: Next Transmit Descriptor Address Upper CSR40: Current Receive Status Byte Count Lower CSR41: Current Receive Status Byte Count Upper CSR42: Current Transmit Status Byte Count Lower CSR43: Current Transmit Status Byte Count Upper CSR44: Next Receive Status Byte Count Lower CSR45: Next Receive Status Byte Count Upper CSR46: Poll Time Counter CSR47: Polling Interval CSR58: Software Style CSR59: Register CSR60: Previous Transmit Descriptor Address Lower CSR61: Previous Transmit Descriptor Address Upper CSR62: Previous Transmit Status Byte Count Lower CSR63: Previous Transmit Status Byte Count Upper CSR64: Next Transmit Buffer Address Lower CSR65: Next Transmit Buffer Address Upper CSR66: Next Transmit Status Byte Count Lower CSR67: Next Transmit Status Byte Count Upper CSR72: Receive Ring Counter CSR74: Transmit Ring Counter CSR76: Receive Ring Length CSR78: Transmit Ring Length CSR80: Transfer Counter FIFO Threshold Control CSR82: Activity Timer CSR84: Address Register Lower CSR85: Address Register Upper CSR86: Buffer Byte Counter CSR88: Chip Register Lower CSR89: Chip Register Upper CSR92: Ring Length Conversion CSR94: Transmit Time Domain Reflectometry Count CSR100: Timeout CSR112: Missed Frame Count CSR114: Receive Collision Count CSR122: Receive Frame Alignment Control CSR124: Buffer Management Test (BMU) Register
1-965 1-965 1-966 1-966 1-966 1-966 1-966 1-966 1-967 1-967 1-967 1-968 1-969 1-969 1-969 1-969 1-969 1-969 1-969 1-970 1-970 1-970 1-970 1-970 1-970 1-972 1-973 1-973 1-973 1-973 1-974 1-974 1-974 1-974 1-974 1-975 1-975 1-975
Am79C970
1-873
PRELIMINARY Configuration Registers 1-976 BCR0: Master Mode Read Active BCR1: Master Mode Write Active BCR2: Miscellaneous Configuration BCR4: Link Status (LNKST) BCR5: LED1 Status BCR6: LED2 Status BCR7: LED3 Status BCR16: Base Address Lower BCR17: Base Address Upper BCR18: Burst Size Control Register BCR19: EEPROM Control Status Register BCR20: Software Style BCR21: Interrupt Control 1-977 1-977 1-977 1-978 1-979 1-980 1-980 1-981 1-982 1-982 1-984 1-987 1-988
Initialization Block 1-989 RLEN TLEN RDRA TDRA LADRF PADR MODE 1-989 1-990 1-990 1-991 1-991
Receive Descriptors 1-991 RMD0 RMD1 RMD2 RMD3 1-992 1-992 1-993 1-993
Transmit Descriptors 1-994 TMD0 TMD1 TMD2 TMD3 1-994 1-994 1-995 1-996
Register Summary 1-997 Control Status Registers 1-997 Configuration Registers 1-1000
1-874
Am79C970
ABSOLUTE MAXIMUM RATINGS 1-1001 OPERATING RANGES 1-1001 CHARACTERISTICS 1-1001 SWITCHING CHARACTERISTICS: Interface 1-1004 SWITCHING CHARACTERISTICS: 10BASE-T Interface 1-1005 SWITCHING CHARACTERISTICS: Attachment Unit Interface 1-1006 SWITCHING WAVEFORMS 1-1007 SWITCHING TEST CIRCUITS 1-1008 SWITCHING WAVEFORMS: System Interface 1-1009 SWITCHING WAVEFORMS: 10BASE-T Interface 1-1011 SWITCHING WAVEFORMS: Attachment Unit Interface 1-1013 APPENDIX PCnet-PCI Compatible Media Interface Modules 1-1016 APPENDIX Recommendation Power Ground Decoupling 1-1019 APPENDIX Alternative Method Initialization 1-1021 APPENDIX Look-Ahead Packet Processing (LAPP) Concept 1-1022 DATA SHEET REVISION SUMMARY 1-1032
Am79C970
1-875
RELATED PRODUCTS
Part Am79C98 Am79C100 Am7996 Am79C981 Am79C987 Am79C940 Am7990 Am79C90 Am79C900 Am79C960 Am79C961 Am79C965 Am79C974 Description Twisted-Pair Ethernet Transceiver (TPEX) Twisted-Pair Ethernet Transceiver Plus (TPEX+) IEEE 802.3/Ethernet/Cheapernet Transceiver Integrated Multiport Repeater Plus(IMR+TM) Hardware Implemented Management Information Base(HIMIBTM) Media Access Controller Ethernet (MACETM) Local Area Network Controller Ethernet (LANCE) CMOS Local Area Network Controller Ethernet (C-LANCE) Integrated Local Area Communications Controller(ILACCTM) PCnet-ISA Single-Chip Ethernet Controller (for bus) PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft® Plug Play support) PCnet-32 Single-Chip 32-Bit Ethernet Controller (for buses) PCnet-SCSI Combination Ethernet SCSI Controller Systems
1-876
Am79C970
CONNECTION DIAGRAM
AD28 AD29 VSSB AD30 AD31 RESERVED INTA RESERVED_DNC SLEEP EECS EESK/LED1 EEDI/LNSKT EEDO/LED3 AVDD2 CIDI+ DIAVDD1 DOAVSS1 AD27 AD26 VSSB AD25 AD24 C/BE3
RESERVED
IDSEL AD23 AD22 VSSB AD21 AD20 VDDB AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP LOCK PERR SERR VDDB
XTAL2 AVSS2 XTAL1 AVDD3
TXD+ TXP+ TXDTXPAVDD4
Am79C970 PCnetTM-PCI
RXD+ RXDVSS
C/BE1 AD15 VSSB AD14 AD13 AD12 AD11 AD10 VSSB VDDB C/BE0 VSSB VSSB RESERVED NOUT
marked orientation. Connection, reserved future use. RESERVED Internally bonded, internal test only; should connected. RESERVED_DNC Reserved, don't connect.
18220C-2
Am79C970
1-877
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination
AM79C970
ALTERNATE PACKAGING OPTION Trimmed Formed Tray OPTIONAL PROCESSING Blank Standard Processing TEMPERATURE RANGE Commercial (0°C +70°C)
PACKAGE TYPE (per Prod. Nomenclature) Plastic Quad Flat Pack (PQB132)
SPEED OPTION Applicable
DEVICE NUMBER/DESCRIPTION Am79C970 PCnet-PCI Single-Chip Ethernet Controller Local
Valid Combinations AM79C970 KC\W
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
1-878
Am79C970
DESIGNATIONS Listed Number
Name VDDB AD27 AD26 VSSB AD25 AD24 C/BE3 RESERVED IDSEL AD23 AD22 VSSB AD21 AD20 VDDB AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP LOCK PERR SERR VDDB Name C/BE1 AD15 VSSB AD14 AD13 AD12 AD11 AD10 VSSB VDDB C/BE0 VSSB VSSB RESERVED NOUT Name RXD- RXD+ AVDD4 TXP- TXD- TXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Name AVSS1 AVDD1 AVDD2 EEDO/LED3 EEDI/LNKST EESK/LED1 EECS SLEEP RESERVED_DNC INTA RESERVED RESERVED AD31 AD30 VSSB AD29 AD28
Am79C970
1-879
DESIGNATIONS Listed Group
Name AD[31:00] C/BE[3:0] DEVSEL FRAME IDSEL INTA IRDY LOCK PERR SERR STOP TRDY Board Interface EECS EEDI/LNKST EEDO/LED3 EESK/LED1 SLEEP XTAL1-2 CI+/CI- DI+/DI- DO+/DO- RXD+/RXD- TXD+/TXD- TXP+/TXP- LNKST/EEDI Test Interface NOUT Power Supplies AVDD AVSS VDDB VSSB Analog Power Analog Ground Digital Power Digital Ground Buffer Power Buffer Ground NAND Tree Test Output Microwire Serial PROM Chip Select Microwire Serial EEPROM Data In/Link Status Microwire APROM Data Out/LED predriver Microwire Serial PROM Clock/LED1 Sleep Mode Crystal Input/Output Collision Differential Pair Data Differential Pair Data Differential Pair Receive Differential Pair Transmit Differential Pair Transmit Pre-distortion Differential Pair Link Status/Microwire Serial EEPROM Data Function Address/Data Command/Byte Enable Clock Device Select Cycle Frame Grant Initialization Device Select Interrupt Initiator Ready Lock Parity Parity Error Request Reset System Error Stop Target Ready Type Driver Pins Interface
Attachment Unit Interface (AUI)
10BASE-T Interface
1-880
Am79C970
DESIGNATIONS Listed Driver Type
next table describes various types drivers that implemented PCnet-PCI controller. Current given milliamperes:
Name Type Tri-StateTri-State Totem Pole Totem Pole Open Drain (mA) (mA) -0.4 -0.4 -0.4
Am79C970
1-881
PRELIMINARY When active, input NAND tree testing.
DESCRIPTION Interface AD[31:00]
Address Data Input/Output These signals multiplexed same pins. During first clock transaction AD[31:00] contain physical byte address bits). During subsequent clocks AD[31:00] contain data. Byte ordering little endian default. AD[07:00] defined least significant byte AD[31:24] defined most significant byte. FIFO data transfers, PCnet-PCI controller programmed endian byte ordering. CSR3, (BSWP) more details. During address phase transaction, when PCnet-PCI controller master, AD[31:2] will address active DWORD (double-word). PCnetPCI controller always drives AD[1:0] '00' during address phase indicating linear burst order. When PCnet-PCI controller master, AD[31:00] lines continuously monitored determine address match exists slave transfers. During data phase transaction, AD[31:00] driven PCnet-PCI controller when performing master writes slave read operations. Data AD[31:00] latched PCnet-PCI controller when performing master reads slave write operations. When active, AD[31:0] inputs NAND tree testing.
DEVSEL
Device Select Input/Output This signal when actively driven PCnet-PCI controller slave device signals master device that PCnet-PCI controller decoded address target current access. input indicates whether device been selected. When active, DEVSEL input NAND tree testing.
FRAME
Cycle Frame Input/Output This signal driven PCnet-PCI controller when master indicate beginning duration access. FRAME asserted indicate transaction beginning. FRAME asserted while data transfers continue. FRAME deasserted when transaction final data phase. When active, FRAME input NAND tree testing.
Grant Input This signal indicates that access been granted PCnet-PCI controller. PCnet-PCI controller supports parking. When idle system arbiter asserts without active from PCnet-PCI controller, PCnet-PCI controller will actively drive C/BE lines. When active, input NAND tree testing.
C/BE [3:0]
Command Byte Enables Input/Output These signals multiplexed same pins. During address phase transaction, C/BE[3:0] define command. During data phase C/BE[3:0] used Byte Enables. Byte Enables define which physical byte lanes carry meaningful data. C/BE0 applies byte (AD[07:00]) C/BE3 applies byte (AD[31:24]). function Byte Enables independent byte ordering mode (CSR3, When active, C/BE[3:0] inputs NAND tree testing.
IDSEL
Initialization Device Select Input This signal used chip select PCnet-PCI controller during configuration read write transaction. When active, IDSEL input NAND tree testing.
Clock Input This signal provides timing transactions devices including PCnet-PCI controller. signals sampled rising edge parameters defined with respect this edge. PCnet-PCI controller operates over range MHz.
1-882
Am79C970
INTA
Interrupt Request Input/Output asynchronous attention signal which indicates that more following status flags set: BABL, MISS, MERR, RINT, IDON, RCVCCO, RPCO, JAB, MPCO, TXSTRT. Each status flag mask which allows suppression INTA assertion. flags have following meaning:
BABL RCVCCO RPCO MISS MERR MPCO RINT IDON TXSTRT Babble Receive Collision Count Overflow Runt Packet Count Overflow Jabber Missed Frame Memory Error Missed Packet Count Overflow Receive Interrupt Initialization Done Transmit Start
Parity Input/Output Parity even parity across AD[31:00] C/BE[3:0].When PCnet-PCI controller master, generates parity during address write data phases. checks parity during read data phases. When PCnet-PCI controller operates slave mode target current cycle, generates parity during read data phases. checks parity during address write data phases. When active, input NAND tree testing.
PERR
Parity Error Input/Output This signal asserted PCnet-PCI controller when checks parity error during data phase when AD[31:00] lines inputs. PERR only active when PERREN (bit command register set. PCnet-PCI controller monitors PERR input during master write cycle. will assert Data Parity Reported Status register Configuration Space when parity error reported target device. When active, PERR input NAND tree testing.
When active, INTA input NAND tree testing.
IRDY
Initiator Ready Input/Output This signal indicates PCnet-PCI controllers ability, master device, complete current data phase transaction. IRDY used conjunction with TRDY. data phase completed clock when both IRDY TRDY asserted. During write IRDY indicates that valid data present AD[31:00]. During read IRDY indicates that data accepted PCnet-PCI controller master. Wait states inserted until both IRDY TRDY asserted simultaneously. When active, IRDY input NAND tree testing.
Request Input/Output PCnet-PCI controller asserts signal that wishes become master. Once asserted, remains active until become active, independent subsequent assertion SLEEP setting STOP access S_RESET port (offset 14h). When active, input NAND tree testing.
LOCK
Lock Input LOCK used current master indicate atomic operation that require multiple transfers. slave device, PCnet-PCI controller locked master device. When another master attempts access PCnet-PCI while locked, PCnet-PCI controller will respond asserting DEVSEL STOP with TRDY deasserted (PCI retry). PCnet-PCI controller will never assert LOCK master. When active, LOCK input NAND tree testing.
Reset Input When asserted low, then PCnet-PCI controller performs internal system reset type H_RESET (HARDWARE_RESET). must held minimum periods. While H_RESET state, PCnet-PCI controller will disable deassert outputs. asynchronous when asserted deasserted. recommended that deassertion synchronous guarantee clean bounce free edge.
Am79C970
1-883
PRELIMINARY PCnet-PCI controller Microwire interface. trailing edge pin, LED1 sampled determine value EEDET BCR19. sampled HIGH value means that EEPROM present, EEDET will ONE. sampled value means that EEPROM present, EEDET will ZERO. EEPROM Auto-detection section more details. circuit attached this pin, then pull pull down resistor must attached instead, order resolve EEDET setting.
When active, NAND tree testing enabled. interface pins input mode. result NAND tree testing observed NOUT output (pin 62).
SERR
System Error Input/Output This signal asserted PCnet-PCI controller when detects parity error during address phase when AD[31:00] lines inputs. SERR only active when SERREN (bit PERREN (bit command register set. When active, SERR input NAND tree testing.
LED3
LED3 Output This shared with EEDO function. When functioning LED3, signal this programmable through BCR7. default, LED3 active indicates transmit activity network. Special attention must given external circuitry attached this pin. circuit were directly attached this pin, would create requirement that could serial EEPROM that would also attached this pin. (This multifunctioned with EEDO function Microwire serial EEPROM interface.) Therefore, this used additional output while EEPROM used system, then buffering required between LED3 circuit. EEPROM included system design, then LED3 signal directly connected without buffering. LED3 output from PCnet-PCI controller capable sinking necessary current drive this case. more details regarding connection, section LEDs.
STOP
Stop Input/Output slave role, PCnet-PCI controller drives STOP signal inform master stop current transaction. master role, PCnet-PCI controller receives STOP signal stops current transaction. When active, STOP input NAND tree testing.
TRDY
Target Ready Input/Output This signal indicates that PCnet-PCI controllers ability selected device complete current data phase transaction. TRDY used conjunction with IRDY. data phase completed clock both TRDY IRDY asserted. During read TRDY indicates that valid data present AD[31:00]. During write, TRDY indicates that data been accepted. Wait states inserted until both IRDY TRDY asserted simultaneously. When active, TRDY input NAND tree testing.
LNKST
LINK Status Output This provides driving LED. default, indicates active link connection 10BASE-T interface. This also programmed indicate other network status (see BCR4). LNKST polarity programmable, default, active LOW. Note that this multiplexed with EEDI function.
Board Interface LED1
LED1 Output This shared with EESK function. LED1, function polarity this programmable through BCR5. default, LED1 active indicates receive activity network. LED1 output from PCnet-PCI controller capable sinking necessary current drive directly. LED1 also used during EEPROM Auto-detection determine whether EEPROM present 1-884
SLEEP
Sleep Input When SLEEP asserted (active LOW), PCnet-PCI controller performs internal system reset S_RESET type then proceeds into power savings mode. (The reset operation caused SLEEP assertion will affect registers.) interface section effected SLEEP. particular, access configuration space remains possible. None
Am79C970
PRELIMINARY configuration registers will reset SLEEP. accesses PCnet-PCI controller will result target abort response. PCnet-PCI controller will assert while sleep mode. When SLEEP asserted, non-PCI interface outputs will placed their normal S_RESET condition. non-PCI interface inputs will ignored except SLEEP itself. De-assertion SLEEP results wake-up. system must refrain from starting network operations PCnet-PCI device seconds following deassertion SLEEP signal order allow internal analog circuits stabilize. Both XTAL1 inputs must have valid clock signals present order SLEEP command take effect. SLEEP asserted while asserted, then PCnet-PCI controller will wait assertion GNT. When asserted, signal will deasserted then PCnet-PCI controller will proceed power savings mode. SLEEP should asserted during power supply ramp-up. desired that SLEEP asserted power time, then system must delay assertion SLEEP until three cycles after completion valid operation.
connected Microwire EEPROMs Clock pin. controlled either PCnet-PCI controller directly during read entire EEPROM, indirectly host system writing BCR19, EESK also used during EEPROM Auto-detection determine whether EEPROM present PCnet-PCI controller Microwire interface. trailing edge signal, LED1 sampled determine value EEDET BCR19. sampled HIGH value means that EEPROM present, EEDET will ONE. sampled value means that EEPROM present, EEDET will ZERO. EEPROM Auto-detection section more details. EESK shared with LED1 function. circuit attached this pin, then pull pull down resistor must attached instead, order resolve EEDET setting.
EEDO
EEPROM Data Input EEDO signal used access external 8802-3 (IEEE/ANSI 802.3) address PROM. This designed directly interface serial EEPROM that uses Microwire interface protocol. EEDO connected Microwire EEPROMs Data Output pin. controlled EEPROM during reads. read host system reading BCR19 EEDO shared with LED3 function.
XTAL1
Crystal Oscillator Inputs Input/Output crystal frequency determines network data rate. PCnet-PCI controller supports quartz crystals generate frequency compatible with 8802-3 (IEEE/ANSI 802.3) network frequency tolerance jitter specifications. section External Crystal Characteristics section Manchester Encoder/Decoder) more detail. network data rate one-half crystal frequency. XTAL1 alternatively driven using external CMOS level source, which case XTAL2 must left unconnected. Note that when PCnet-PCI controller comma mode, there internal resistor from XTAL1 ground. external source drives XTAL1, some power will consumed driving this resistor. XTAL1 driven this time power consumption will minimized. this case, XTAL1 must remain active least cycles after assertion SLEEP deassertion REQ.
EECS
EEPROM Chip Select Output function EECS signal indicate Microwire EEPROM device that being accessed. EECS signal active high. controlled either PCnet-PCI controller during command portions read entire EEPROM, indirectly host system writing BCR19
EEDI
EEPROM Data Output EEDI signal used access external 8802-3 (IEEE/ANSI 802.3) address PROM. EEDI functions output. This designed directly interface serial EEPROM that uses Microwire interface protocol. EEDI connected Microwire EEPROMs Data Input pin. controlled either PCnet-PCI controller during command portions read entire EEPROM, indirectly host system writing BCR19 EEDI shared with LNKST function.
Microwire EEPROM Interface EESK
EEPROM Serial clock Input/Output EESK signal used access external 8802-3 (IEEE/ANSI 802.3) address PROM. This designed directly interface serial EEPROM that uses Microwire interface protocol. EESK
Am79C970
1-885
Attachment Unit Interface
Collision Input differential input pair signaling PCnet-PCI controller that collision been detected network media, indicated inputs being driven with pattern sufficient amplitude pulse width meet 8802-3 (IEEE/ANSI 802.3) standards. Operates pseudo levels.
Power Supply Pins Analog Power Supply Pins AVDD
Analog Power Pins) Power There four analog supply pins. Special attention should paid printed circuit board layout avoid excessive noise these lines. Refer Appendix PCnet Family Technical Manual (PID #18216A) details.
Data Input
differential input pair PCnet-PCI controller carrying Manchester encoded data from network. Operates pseudo levels.
AVSS
Analog Ground Pins) Power There analog ground pins. Special attention should paid printed circuit board layout avoid excessive noise these lines. Refer Appendix PCnet Family Technical Manual (PID #18216A) details.
Data Output
differential output pair from PCnet-PCI controller transmitting Manchester encoded data network. Operates pseudo levels.
Digital Power Supply Pins
Digital Power Pins) Power There power supply pins that used internal digital circuitry. pins must connected supply.
Twisted-Pair Interface RXD±
10BASE-T Receive Data Input 10BASE-T port differential receivers.
VDDB
Buffer Power Pins) Power There power supply pins that used Input/Output buffer drivers. VDDB pins must connected supply.
TXD± 10BASE-T Transmit Data Output
10BASE-T port differential drivers.
TXP±
10BASE-T Pre-Distortion Control Output These outputs provide transmit pre-distortion control conjunction with 10BASE-T port differential drivers.
Digital Ground Pins) Ground There ground pins that used internal digital circuitry.
Test Interface NOUT
NAND Tree Output results NAND tree testing observed NOUT pin. NOUT will constantly high, when deasserted.
VSSB
Buffer Ground Pins) Ground There ground pins that used Input/Output buffer drivers.
1-886
Am79C970
BASIC FUNCTIONS System Interface Function
PCnet-PCI controller designed operate Master during normal operations. Some slave accesses PCnet-PCI controller required normal operations well. Initialization PCnetPCI controller achieved through combination Configuration Space accesses, Slave accesses, Master accesses optional read serial EEPROM that performed PCnet-PCI controller. EEPROM read operation performed through Microwire interface. 8802-3 (IEEE/ANSI 802.3) Ethernet Address reside within serial EEPROM. Some PCnet-PCI controller configuration registers also programmed EEPROM read operation. APROM, on-chip board-configuration registers, Ethernet controller registers occupy 32-bytes space which located wide variety starting addresses modifying Base Address Register Configuration Space.
space that must begin 32-byte block boundary. base address changed 32-bit quantity that begins 32-bit block boundary modifying Base Address Register Configuration Space. 32-byte space used software program PCnet-PCI controller operating mode, enable disable various features, monitor operating status request particular functions executed PCnet-PCI controller. third portion software interface descriptor buffer areas that shared between software PCnet-PCI controller during normal network operations. descriptor area boundaries software change during normal network operations. There descriptor area receive activity there separate area transmit activity. descriptor space contains relocatable pointers network packet data used transfer packet status from PCnet-PCI controller software. buffer areas locations that hold packet data transmission that accept packet data that been received.
Software Interface
software interface PCnet-PCI controller divided into three parts. part configuration registers. They used identify PCnet-PCI controller, also used setup configuration device. setup information includes base address routing PCnet-PCI controller interrupt channel. This allows jumperless implementation. second portion software interface direct access resources PCnet-PCI controller. PCnet-PCI controller occupies 32-bytes
Network Interfaces
PCnet-PCI controller connected 802.3 network network interfaces. Attachment Unit Interface (AUI) provides 8802-3 (IEEE/ANSI 802.3) compliant differential interface remote on-board transceiver. 10BASE-T interface provides twisted-pair Ethernet port. While auto-selection mode, interface determined auto-sensing mechanism which checks link status 10BASE-T port. there active link status, then device assumes connection.
Am79C970
1-887
DETAILED FUNCTIONS Interface Unit (BIU)
interface unit built several state machines that synchronously CLK. interface unit state machine handles accesses where PCnet-PCI controller slave, another handles accesses where PCnet-PCI controller master. inputs synchronously sampled. outputs synchronously generated rising edge CLK.
FRAME
ADDR
Acquisition
PCnet-PCI microcode buffer management section) will determine when transfer should initiated. first step PCnet-PCI master transfer acquire ownership bus. This task handled synchronous logic within BIU. ownership requested with signal ownership granted arbiter through signal. Figure shows PCnet-PCI controller acquisition. asserted clock PCnet-PCI controller starts driving AD[31:00] C/BE[3:0] prior clock FRAME asserted clock indicating valid address command AD[31:00] C/BE[3:0]. ADSTEP (bit Command register indicated that PCnet-PCI controller uses address stepping. Address stepping only used first address phase master period.
C/BE
18220C-3
Figure Acquisition
Note that assertion STOP CSR0 will cause deassertion signal. Note also that read RESET register, (I/O resource offset from PCnet-PCI base address) will cause deassertion signal. Either these actions will cause internal master state machine logic cease operations, signal will remain active until signal asserted. Following either above actions, next clock cycle after signal asserted, PCnet-PCI controller will deassert signal. Assertion minimum-width pulse will cause signal deassert immediately following assertion pin. this case, PCnet-PCI controller will wait assertion signal before deasserting signal.
1-888
Am79C970
Master Transfers
There four primary types transfers. PCnet-PCI controller uses non-burst well burst cycles read write access main memory. Basic Non-Burst Read Cycles PCnet-PCI controller uses non-burst read cycles access initialization block receive transmit descriptor entries. Some read accesses transmit buffer memory also non-burst mode. PCnet-PCI controller non-burst read accesses command type Memory Read (type Note that during non-burst read operations, PCnet-PCI
controller will always activate byte enables, even though some byte lanes contain valid data indicated buffer pointer value. such instances, PCnet-PCI controller will internally discard unneeded bytes. Figure shows typical non-burst read access. PCnet-PCI controller asserts IRDY clock immediately after address phase starts sampling DEVSEL. target extends cycle asserting DEVSEL until clock Additionally, target inserts wait state asserting ready (TRDY) clock
FRAME
ADDR
DATA
C/BE
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller.
18220C-4
Figure Non-Burst Read Cycle With Wait States
Am79C970
1-889
PRELIMINARY access. example below also shows target that respond PCnet-PCI controller read cycles without wait states.
Figure shows non-burst read access within arbitration cycle. PCnet-PCI controller will drop FRAME between consecutive non-burst read cycles. PCnet-PCI controller will re-request right again preempted before starting second
FRAME
ADDR
DATA
ADDR
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller.
18220C-5
Figure Non-Burst Read Cycles Without Wait States
1-890
Am79C970
PRELIMINARY Basic Burst Read Cycles PCnet-PCI controller provides burst mode read data from transmit buffer. burst mode must enabled setting BREADE BCR18. PCnet-PCI controller burst read transfers command type Memory Read Line (type15). AD[1:0] will both ZERO during address phase indicating linear burst order. four byte enable signals will ZERO during
data phase PCnet-PCI controller always reads full 32-bit word when burst mode. Figure shows typical burst read access. PCnetPCI controller arbitrates bus, granted access, reads four 32-bit words (DWORD) from system memory then releases bus. four data phases this example take clock cycles each, which determined timing TRDY.
FRAME
ADDR
DATA
DATA
DATA
DATA
C/BE
1110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller.
18220C-6
Figure Burst Read Cycles
Am79C970
1-891
Basic Non-Burst Write
PRELIMINARY FRAME between consecutive non-burst write cycles. PCnet-PCI controller will re-request immediately preempted before starting second access. example below shows extended cycle first access. target asserts DEVSEL clock cycles after address phase (FRAME asserted) adds extra wait state asserting TRDY only clock second write cycle example shows ZERO wait state access.
PCnet-PCI controller uses non-burst write cycles access receive transmit descriptor entries. Some write accesses receive buffer memory also non-burst mode. PCnet-PCI controller non-burst write accesses command type Memory Write (type Figure shows non-burst write access within arbitration cycle. PCnet-PCI controller will drop
FRAME
ADDR
DATA
ADDR
DATA
C/BE
0111
BE's
0111
BE's
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller.
18220C-7
Figure Non-Burst Write Cycles With Without Wait States
1-892
Am79C970
PRELIMINARY Basic Burst Write Cycles PCnet-PCI controller provides burst mode write data receive buffer. burst mode must enabled setting BWRITE BCR18. PCnet-PCI controller burst write transfers command type Memory Write (type AD[1:0] will both ZERO during address phase indicating linear burst order. four byte enable signals will ZERO during data phase PCnet-PCI controller always writes full 32-bit word when burst mode.
Figure shows typical burst write access. PCnetPCI controller arbitrates bus, granted access, writes four 32-bit words (DWORDs) from system memory then releases bus. this example, memory system extends data phase first access wait state. following three data phases take clock cycle each, which determined timing TRDY.
FRAME
ADDR
DATA
DATA
DATA
DATA
C/BE
0111
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller.
18220C-8
Figure Burst Write Cycles
Am79C970
1-893
PRELIMINARY IRDY TRDY asserted. PCnet-PCI controller terminates current transfer with deassertion FRAME clock then clock cycle later with deassertion IRDY. finally releases clock PCnet-PCI controller will re-request after clock cycles, wants transfer more data. starting address transfer will address next untransferred data.
Target Initiated Termination
When PCnet-PCI controller master, cycles produces terminated target three different ways. Disconnect With Data Transfer Figure shows disconnection which last data transfer occurs after target asserted STOP. STOP asserted clock start termination sequence. Data still transferred during this cycles, since both
FRAME
ADDR
DATA
DATA
ADDR
C/BE
0111
0000
0111
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled PCnet-PCI controller.
18220C-9
Figure Disconnect with Data Transfer
1-894
Am79C970
PRELIMINARY Disconnect Without Data Transfer Figure shows target disconnect sequence during which data transferred. STOP asserted clock without TRDY being asserted same time. PCnet-PCI controller terminates current transfer with deassertion FRAME clock clock
cycle later with deassertion IRDY. finally releases clock PCnet-PCI controller will re-request after clock cycles retry last transfer. starting address transfer will same address last untransferred data.
FRAME
ADDRi
DATA
ADDRi
C/BE
0111
0000
0111
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled PCnet-PCI controller.
18220C-10
Figure Disconnect Without Data Transfer
Am79C970
1-895
Target Abort
PRELIMINARY Since data integrity guaranteed, PCnet-PCI controller cannot recover from target abort event. PCnet-PCI controller will reset locations their H_RESET values. on-going network activity will stopped immediately. configuration registers will cleared. RTABORT (bit Status register will indicate that PCnetPCI controller received target abort.
Figure shows target abort sequence. target asserts DEVSEL clock. then deasserts DEVSEL asserts STOP clock target target abort sequence indicate that cannot service data transfer that does want transaction retried. Additionally, PCnet-PCI controller cannot make assumption about success previous data transfers current transaction. PCnet-PCI controller terminates current transfer with deassertion FRAME clock clock cycle later with deassertion IRDY. finally releases clock
FRAME
ADDR
DATA
C/BE
0111
0000
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled PCnet-PCI controller.
18220C-11
Figure Target Abort
1-896
Am79C970
Master Initiated Termination
There three scenarios besides normal completion transaction where PCnet-PCI controller will terminate cycles produces bus. Preemption When FRAME Deasserted PCnet-PCI controller will generate multiple address phases during single ownership period when accessing initialization block, descriptor ring
entries data buffers main memory. FRAME deasserted between address phases. While FRAME deasserted, central arbiter remove PCnet-PCI controller time service another master. When removed, PCnet-PCI controller will finish current transfer then release bus. will keep asserted regain ownership soon possible.
FRAME
ADDR
DATA
C/BE
0111
BE's
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller.
18220C-12
Figure Preemption When FRAME Deasserted
Am79C970
1-897
Preemption When FRAME Asserted
PRELIMINARY current transfer then immediately release bus. Latency Timer configuration space PCnet-PCI controller always ZERO. PCnetPCI controller will keep asserted regain ownership soon possible.
central arbiter take PCnet-PCI controller away current operation takes long. This happen e.g. when PCnet-PCI controller tries fill whole transmit FIFO target inserts extra wait states every data phase. When taken away, PCnet-PCI controller will finish
FRAME
ADDR
DATA
DATA
DATA
C/BE
0111
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller.
18220C-13
Figure Preemption When FRAME Asserted
1-898
Am79C970
PRELIMINARY Master Abort PCnet-PCI controller will terminate cycle with Master Abort sequence DEVSEL asserted within clocks after FRAME asserted. Master Abort treated fatal error PCnet-PCI controller. PCnet-PCI controller will reset locations their H_RESET values. on-going network
activity will stopped immediately. configuration registers will cleared. RMABORT (bit Status register will indicate that PCnetPCI controller terminated transaction with master abort.
FRAME
ADDR
DATA
C/BE
0111
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller.
18220C-14
Figure Master Abort
Am79C970
1-899
PRELIMINARY transfer during master initialization procedure, four mastership periods needed order complete initialization sequence. Note that last DWORD transfer last mastership period initialization sequence accesses unneeded location. Data from this transfer discarded internally. When SSIZE32 (BCR20, then three mastership periods needed complete initialization sequence.
Initialization Block Transfers
During execution PCnet-PCI controller master initialization procedure, PCnet-PCI microcode will repeatedly request transfers from BIU. During each these initialization block transfers, will perform data transfer cycles (eight bytes) then will relinquish bus. transfers within mastership period will always read cycles ascending contiguous addresses. When SSIZE32 (BCR20, there DWORDs
FRAME
IADDi
DATA
IADD
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller.
18220C-15
Figure Initialization Block Read
1-900
Am79C970
Descriptor Transfers
PCnet-PCI microcode will determine when descriptor access required. descriptor read will consist DWORD (double-word) transfers. descriptor write will consist DWORD transfers. (The transfers within descriptor transfer mastership period will always same type (either read write)). buffer chaining used, writes descriptors intermediate buffers consist only DWORD
return OWNership buffer system. single buffer transmit receive descriptors, well last buffer chain, writes descriptor consist DWORDs. first DWORD containing status information. second DWORD containing additional status OWNership (i.e. MD1[31]). transfers will addressed specified tables
Table Master Reads Descriptors
16-Bit Software Mode Address Sequence AD[7:0]* Break LANCE/ PCnet-ISA Item Accessed MD1[15:0], MD0[15:0] MD3[15:0], MD2[15:0] PCnet-PCI Item Accessed MD1[31:24], MD0[23:0] MD2[15:0], MD1[15:0] Address Sequence AD[7:0]* Break 32-Bit Software Mode LANCE/ PCnet-ISA Item Accessed MD1[15:8], MD2[15:0] MD1[7:0], MD0[15:0] PCnet-PCI Item Accessed MD1[31:0] MD0[31:0]
Table Master Writes Descriptors
16-Bit Software Mode Address Sequence AD[7:0]* Break LANCE/ PCnet-ISA Item Accessed MD3[15:0], MD2[15:0] MD1[15:0], MD0[15:0] PCnet-PCI Item Accessed MD2[15:0], MD1[15:0] MD1[31:24], MD0[23:0] Address Sequence AD[7:0]* Break 32-Bit Software Mode LANCE/ PCnet-ISA Item Accessed MD3[15:0] MD1[15:8], MD2[15:0] PCnet-PCI Item Accessed MD2[31:0] MD1[31:0]
Address values AD[31:08] constant throughout single descriptor transfer. AD[1:0] must ZERO descriptor base address.
During descriptor read accesses, byte enable signals will indicate that byte lanes active. Should some bytes needed, then PCnet-PCI controller will internally discard extraneous information that gathered during such read. During write accesses, only bytes which need written enabled, activating corresponding byte enable pins.
only significant differences between descriptor transfers initialization transfers that addresses accesses follow different ordering.
Am79C970
1-901
FRAME
MD1*
DATA
MD0*
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller. Note that Message Descriptor addresses descending order.
18220C-16
Figure Descriptor Ring Read
1-902
Am79C970
FRAME
MD2*
DATA
MD1*
DATA
C/BE
0111
0000
0111
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller.
Note that Message Descriptor addresses descending order.
18220C-17
Figure Descriptor Ring Write
Am79C970
1-903
PRELIMINARY registers, preemption another mastering device, exceptional receive transmit events, packet signal from FIFO, FIFO watermark settings extent Grant latency will major factors determining number accesses performed during given arbitration cycle when DMAPLUS TRDY response memory device will also affect number transfers when DMAPLUS since speed accesses will affect state FIFO. (During accesses, FIFO filling emptying network end. slower memory response will allow additional data accumulate inside FIFO (during write transfers from receive FIFO). accesses slow enough, complete DWORD become available before arbitration cycle thereby increase number transfers that cycle.) general rule that longer Grant latency slower transfer operations clock speed) higher transmit watermark lower receive watermark combination thereof longer will average mastership period. Burst FIFO Transfers Bursting only performed PCnet-PCI controller BREADE and/or BWRITE bits BCR18 set. These bits individually enable/disable ability PCnet-PCI controller perform burst accesses during master read operations master write operations, respectively. Only FIFO data transfers will make burst mode. first transfer burst will consist both address data phase. Subsequent transfers will contain data only. AD[1:0] will always ZERO during address phase indicating linear burst order. Note, that terms `burst' `linear burst' used interchangeably throughout this document. number data phases within burst transfer determined LINBC value from BCR18 register. burst upper limit calculated taking BCR18 LINBC[2:0] value multiplying result number transfers that will performed within single linear burst sequence. When LINBC upper limit data transfers have been performed, FRAME asserted there more data transferred), with address pins. Following assertion FRAME, linear bursting data will resume. byte lanes will always active during burst transfers reflected C/BE[3:0] signals. number data transfer cycles within total mastership period dependent programming DMAPLUS option (CSR4, 14). possibilities follows:
FIFO Transfers
PCnet-PCI microcode will determine when FIFO transfer required. This transfer mode will used transfers data from PCnet-PCI FIFOs. Once PCnet-PCI been granted mastership, will perform series consecutive transfer cycles before relinquishing bus. transfers within master cycle will either read write cycles, transfers will contiguous, ascending addresses. Both non-burst burst cycles used. Non-Burst FIFO Transfers Non-burst FIFO transfers default mode PCnet-PCI controller uses read write data when accessing FIFOs. Each non-burst transfer will performed sequentially, with issue address, transfer corresponding data with appropriate output signals indicate selection active data bytes during transfer. FRAME will dropped after every address phase. (See figures number data transfer cycles contained within single mastership period general dependent programming DMAPLUS option (CSR4, 14). Several other factors will also affect length mastership period. possibilities follows: DMAPLUS maximum transfers will performed default. This default value changed writing Transfer Counter (CSR80). Note that DMAPLUS merely sets maximum value. minimum number transfers mastership period will determined following variables: settings FIFO watermarks conditions FIFOs, value Transfer Counter (CSR80), value Timer (CSR82), occurrence preemption that takes place during mastership period. DMAPLUS cycle will continue until transmit FIFO filled high threshold (read transfers) receive FIFO emptied threshold (write transfers), until Timer value (CSR82) expired. Other variables also affect point mastership period this mode. Among those variables particular conditions existing within FIFOs, receive transmit status conditions, preemption events. FIFO thresholds programmable (see description CSR80), Transfer Counter Timer values. exact number transfer cycles case DMAPLUS will dependent latency system PCnet-PCI controller's mastership request speed operation, will limited value Timer register, FIFO condition, receive transmit status, preemption events. Barring time-out either these 1-904
Am79C970
PRELIMINARY DMAPLUS maximum transfers will performed default. This default value changed writing Transfer Counter (CSR80). Note that DMAPLUS merely sets maximum value. minimum number transfers mastership period will determined following variables: settings FIFO watermarks conditions FIFOs, value Transfer Counter (CSR80), value Timer (CSR82), occurrence preemption that takes place during mastership period. DMAPLUS linear bursting will continue until transmit FIFO filled high threshold (read transfers) receive FIFO emptied threshold (write transfers), until Timer value (CSR82) expired. preemption event another cause termination cycles. FIFO thresholds programmable (see description CSR80), Transfer Counter Timer values. exact number total transfer cycles case DMAPLUS will dependent latency system PCnet-PCI controller's mastership request speed operation, will limited value Timer Register, FIFO condition preemption occurrences, any. Note that number transfer cycles each FRAME assertion will always only controlled LINBC, Grant FIFO conditions. number transfer cycles each FRAME assertions will affected DMAPLUS values Transfer Count register Timer register. However, these factors influence number transfers that performed during given mastership period. Barring time-out Transfer Count register Timer register preemption another mastering device, FIFO watermark settings extent Grant latency will major factors determining number accesses performed during given mastership period. TRDY response time memory device will also affect number transfers, since speed accesses will affect state FIFO. (During accesses, FIFO
filling emptying network end. example, Receive operation, slower device will allow additional data accumulate inside FIFO. accesses slow enough, complete DWORD become available before mastership period thereby increase number transfers that period.) general rule that longer Grant latency slower transfer operations slower clock speed higher transmit watermark lower receive watermark combination thereof, will produce longer total burst lengths. Linear Burst Starting Address Restrictions PCnet-PCI controller linear burst will begin only when address current transfer meets following condition: AD[31:00] (LINBC following table illustrates possible starting address values legal LINBC values. Note that AD[31:06] don't care values addresses. Also note that while AD[1:0] physically exist within system (the PCnet-PCI controller always drives AD[1:0] ZERO during address phase indicate linear burst order), they valid bits within buffer pointer field descriptor word Thus, where AD[1:0] listed, they refer lowest bits descriptors buffer pointer field. These bits will have affect determining when PCnet-PCI controller linear burst operation legally begin they will affect output values byte enable pins, therefore they have been included table AD[1:0]. Table Linear Burst Starting Address Values
Linear Burst Size (number LINBC[2:0] transfers) Reserved Linear Burst Beginning Addresses AD[5:0] (Hex) (AD[31:06] (don't care) Applicable
Size Burst (bytes) Reserved
Am79C970
1-905
PRELIMINARY Linear Burst Address Alignment Linear bursting begin during mastership period which initially performing only non-burst operations. change from non-burst operation linear bursting will normally occur during linear burst address alignment operations. PCnet-PCI controller programmed burst mode (i.e. BREADE and/or BWRITE bits BCR18 ONE), PCnet-PCI controller requests bus, starting address first transaction does meet conditions specified table above, then PCnet-PCI controller will perform non-burst accesses until arrives address that does meet conditions described table. that time, without releasing bus, PCnet-PCI controller will invoke linear burst mode. Figure shows example linear burst alignment operation being performed. first access transmit buffer non-burst mode, because current address does align with linear burst boundary. PCnet-PCI controller switches burst mode beginning with second transfer. stays asserted during transfers.
necessary software insure that buffer address pointer contained descriptor word matches address restrictions given table. buffer pointer does meet conditions forth table, then PCnet-PCI controller will simply postpone start linear bursting until enough non-burst FIFO transfers have been performed bring current working buffer pointer value valid linear burst starting address. This operation referred aligning buffer address valid linear burst starting address. Once this been done, PCnet-PCI controller will recognize that address current access valid linear burst starting address, will automatically begin perform linear burst accesses that time, provided course that software enabled linear burst mode. Note that software would provide only valid linear burst starting addresses buffer pointer, then PCnet-PCI controller could avoid performing alignment operation. would begin linear burst accesses very first buffer transfers thereby allowing slight gain bandwidth efficiency.
FRAME
n0Ch
DATA
n10h
DATA
DATA
C/BE
0110
0000
1110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller.
18220C-18
Figure Burst Alignment 1-906 Am79C970
PRELIMINARY Partial Linear Burst Certain factors cause PCnet-PCI controller burst fewer than LINBC limit during single burst sequence. Factors that could generate partial linear burst include: more data available transfers from current buffer more data available transfer from FIFO this packet more space available transfers current buffer Preemption Typically, during case master read operation (for buffer transfers), last transfer linear burst sequence will last transfer executed before PCnet-PCI controller releases bus. This true both partial completed linear burst sequences.
During case master write operation (for buffer transfers) when packet data ended, last transfer linear burst sequence will last transfer executed before PCnet-PCI controller releases bus. This true both partial completed linear burst sequences. However, next transfer that PCnet-PCI controller scheduled execute will last available location buffer, then PCnet-PCI controller will non-burst cycle make last transfer buffer. This event occurs because restrictions placed upon byte enable signals during linear burst operation. mentioned initial description linear burst accesses, byte lanes data always enabled during linear burst operations. Note, however, that case last buffer location, PCnet-PCI controller only portion DWORD location. such cases, necessary discontinue linear burst accesses second from last buffer location that ordinary transfer with some byte lanes disabled used final transfer.
Am79C970
1-907
PRELIMINARY second transfer will another bytes space, PCnet-PCI controller able predict that third transfer will last. Therefore, de-asserts FRAME second transfer terminate linear burst operation. However, PCnet-PCI controller retains ownership that may, immediately, make non-burst transfer(s) last spaces buffer.
Figure shows partial linear burst that occurred while approaching transfer last bytes data buffer. linear burst begins when bytes space still remain buffer. (The number spaces remaining figure drawn could anywhere from value 10-byte spaces been chosen just purposes illustration.) After first linear burst transfer, byte spaces remain. Knowing that
FRAME
n00h
DATA
DATA
n08h
DATA
C/BE
0111
0000
0111
1100
IRDY
TRDY
DEVSEL
DEVSEL sampled PCnet-PCI controller.
18220C-19
Figure Partial Linear Burst Buffer burst cycle preempted before last data phase, PCnet-PCI controller will finish current data phase release bus. will stay asserted. PCnet-PCI controller will revert non-burst cycle accesses following preemption event. this case, linear bursting will next occur when memory address being accessed next meets linear burst starting address requirements.
1-908
Am79C970
Slave Transfers
After PCnet-PCI controller configured device setting IOEN Command register), starts monitoring access internal registers. PCnet-PCI controller will look address that falls within bytes address space (starting from base address). PCnet-PCI controller will assert DEVSEL detects address match access cycle. DEVSEL asserted clock cycles after host asserted FRAME. PCnet-PCI controller will assert DEVSEL detects address match, command type read write. PCnet-PCI controller will suspend looking cycles while being master.
Slave Read Slave Read command used host read PCnet-PCI's CSRs, BCRs EEPROM locations. single cycle, non-burst 8-bit,16-bit 32-bit transfer which initiated host CPU. typical number wait states added slave read access part PCnet-PCI controller clock cycles, depending upon relative phases internal Buffer Management Unit clock signal, since internal Buffer Management Unit clock divide-by-two version signal. PCnet-PCI controller will produce Slave Read commands while being master.
FRAME
ADDR
DATA
C/BE
0010
BE's
IRDY
TRDY
DEVSEL
STOP
18220C-20
Figure Slave Read
Am79C970
1-909
Slave Write
PRELIMINARY cycles, depending upon relative phases internal Buffer Management Unit clock signal, since internal Buffer Management Unit clock divide-by-two version signal. PCnet-PCI controller will produce Slave write commands while being master.
Slave Write command used host write PCnet-PCI's CSRs, BCRs EEPROM locations. single cycle, non-burst 16-bit 32-bit transfer which initiated host CPU. typical number wait states added slave write access part PCnet-PCI controller clock
FRAME
ADDR
DATA
C/BE
0011
BE's
IRDY
TRDY
DEVSEL
STOP
18220C-21
Figure Slave Write
1-910
Am79C970
Slave Configuration Transfers
host access PCnet-PCI configuration space with configuration read write command. PCnet-PCI controller will assert DEVSEL IDSEL input asserted during address phase access configuration cycle. DEVSEL asserted clock cycles after host asserted FRAME. configuration cycles fixed length. PCnet-PCI controller will assert TRDY clock data phase.
Slave Configuration Read Slave Configuration Read command used host read configuration space PCnetPCI controller. This provides host with information concerning device capabilities. This single cycle, non-burst 8-bit, 16-bit, 32-bit transfer.
FRAME
ADDR
DATA
C/BE
1010
BE's
IRDY
TRDY
DEVSEL
STOP
IDSEL
18220C-22
Figure Slave Configuration Read
Am79C970
1-911
Slave Configuration Write
PRELIMINARY activity device, such enable/disable, change location, etc. This single cycle, non-burst 8-bit, 16-bit, 32-bit transfer.
Slave Configuration Write command used host write configuration space PCnetPCI controller. This allows host control basic
FRAME
ADDR
DATA
C/BE
1011
BE's
IRDY
TRDY
DEVSEL
STOP
IDSEL
18220C-23
Figure Slave Configuration Write
1-912
Am79C970
Buffer Management Unit (BMU)
buffer management unit micro-coded state machine which implements initialization procedure manages descriptors buffers. buffer management unit operates half speed input.
Initialization
PCnet-PCI initialization includes reading initialization block memory obtain operating parameters. initialization block read when INIT CSR0 set. INIT should before concurrent with STRT insure correct operation. DWORDs read during each period mastership. When SSIZE32 (BCR20, this results total arbitration cycles arbitration cycles SSIZE32 Once initialization block been completely read internal registers have been updated, IDON will CSR0, interrupt generated IENA set). this point, knows where receive transmit descriptor rings hence, normal network operations will begin. PCnet-PCI controller obtains start address Initialization Block from contents CSR1 (least significant bits address) CSR2 (most significant bits address). host must write CSR1 CSR2 before setting INIT bit. block contains user defined conditions PCnet-PCI operation, together with base addresses length information transmit receive descriptor rings. There alternative method initialize PCnetPCI controller. Instead initialization initialization block memory, data written directly into appropriate registers. Either method used discretion programmer. registers written directly, INIT must set, initialization block will read thus overwriting previously written information. Please refer Appendix details this alternative method. initialization done writing directly registers, Polling Interval register (CSR47) must initialized addition those registers that loaded automatically from initialization block.
Reinitialization done initialization block setting STOP CSR0, followed writing CSR15, then setting START CSR0. Note that this form restart will perform same PCnet-PCI controller LANCE. particular, upon restart, PCnet-PCI controller reloads transmit receive descriptor pointers with their respective base addresses. This means that software must clear descriptor bits reset descriptor ring pointers before restart PCnet-PCI controller. reload descriptor base addresses performed LANCE only after initialization, restart LANCE without initialization leaves LANCE pointing same descriptor locations before restart.
Buffer Management
Buffer management accomplished through message descriptor entries organized ring structures memory. There rings, receive ring transmit ring. size message descriptor entry DWORDs, bytes, when SSIZE32 size message descriptor entry words, bytes, when SSIZE32
Descriptor Rings
Each descriptor ring must organized contiguous area memory. initialization time (setting INIT CSR0), PCnet-PCI controller reads user-defined base address transmit receive descriptor rings, well number entries contained descriptor rings. Descriptor ring base addresses must 16-byte boundary when SSIZE32=1, 8-byte boundary when SSIZE=0. maximum 512, depending upon value SSIZE32) ring entries allowed when ring length through TLEN RLEN fields initialization block. However, ring lengths beyond this range 65535) writing transmit receive ring length registers (CSR76, CSR78) directly. Each ring entry contains following information: address actual message data buffer user host memory length message buffer Status information indicating condition buffer permit queuing de-queuing message buffers, ownership each buffer allocated either PCnet-PCI controller host. within descriptor status information, either (see section RMD), used this purpose. signifies that PCnet-PCI controller currently ownership this ring descriptor associated buffer. Only owner permitted relinquish ownership write field descriptor entry. device that current owner descriptor entry cannot assume ownership change field 1-913
Re-Initialization
transmitter receiver sections PCnet-PCI controller turned initialization block (MODE Register DTX, bits; CSR15[1:0]). states transmitter receiver monitored host through CSR0 (RXON, TXON bits). PCnetPCI controller should reinitialized transmitter and/or receiver were turned during original initialization, subsequently required activate them either section shut detection error condition (MERR, UFLO, BUFF error).
Am79C970
PRELIMINARY final step self-initialization process, base address each ring loaded into each current descriptor address registers address next descriptor entry transmit receive rings computed loaded into each next descriptor address registers. When SSIZE32 software data structures bits wide. following diagram, Figure illustrates relationship between Initialization Base Address, Initialization Block, Receive Transmit Descriptor Ring Base Addresses, Receive Transmit Descriptors Receive Transmit Data Buffers, case SSIZE32
entry. device may, however, read from descriptor that does currently own. Software should always read descriptor entries sequential order. When software finds that current descriptor owned PCnet-PCI controller, then software must read "ahead" next descriptor. software should wait unOWNed descriptor until ownership been granted software (when SPRINTEN (CSR3, then this rule modified. SPRINTEN description). Strict adherence these rules insures that "Deadly Embrace" conditions avoided.
Descriptor Ring Access Mechanism
initialization, PCnet-PCI controller reads base address both transmit receive descriptor rings into CSRs PCnet-PCI controller during subsequent operations.
24-Bit Base Address Pointer Initialization Block CSR2
IADR[23:16]
Descriptor Ring
desc. start desc. start
CSR1
IADR[15:0]
RMD0
RMD0 RMD1 RMD2 RMD3
Initialization Block
MODE PADR[15:0] PADR[31:16] PADR[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RLEN TLEN RDRA[23:16] TDRA[15:0] TDRA[23:16]
Buffers
Data Buffer
Data Buffer
Data Buffer
DESCRIPTOR RINGS
Descriptor
DESCRIPTOR RINGS Ring
desc. start
desc. start
TMD0
TMD0 TMD1 TMD2 TMD3
Buffers
Data Buffer
Data Buffer
Data Buffer
18220C-24
Figure 16-Bit Data Structures: Initialization Block Descriptor Rings 1-914 Am79C970
PRELIMINARY When SSIZE32 software data structures bits wide. following diagram illustrates, Figure relationship between Initialization Base Address, Initialization Block, Receive Transmit
Descriptor Ring Base Addresses, Receive Transmit Descriptors Receive Transmit Data Buffers, case SSIZE32
32-Bit Base Address Pointer Initialization Block CSR2
IADR[31:16]
Descriptor Ring
desc. start desc. start
CSR1
IADR[15:0]
RMD0
RMD0 RMD1 RMD2 RMD3
Initialization Block
TLEN RLEN MODE PADR[31:0] PADR[47:32] LADRF[31:0] LADRF[63:32] RDRA[31:0] TDRA[31:0]
Buffers
Data Buffer
Data Buffer
Data Buffer
DESCRIPTOR RINGS
Descriptor
DESCRIPTOR RINGS Ring
desc. start
desc. start
TMD0
TMD0 TMD1 TMD2 TMD3
Buffers
Data Buffer
Data Buffer
Data Buffer
18220C-25
Figure 32-Bit Data Structures: Initialization Block Descriptor Rings
Am79C970
1-915
PRELIMINARY typical transmit poll product following conditions: PCnet-PCI controller does possess ownership current TDTE DPOLL=0 (CSR4, TXON=1 (CSR0, poll time elapsed, PCnet-PCI controller does possess ownership current TDTE DPOLL=0 TXON=1 frame just been received, PCnet-PCI controller does possess ownership current TDTE DPOLL=0 TXON=1 frame just been transmitted. Setting TDMD CSR0 will cause microcode controller exit poll counting code immediately perform polling operation. RDTE ownership been previously established, then RDTE poll will performed ahead TDTE poll. microcode executing poll counting code when TDMD set, then demanded poll TDTE will delayed until microcode returns poll counting code. user change poll time value from default 65,536 clock periods modifying value Polling Interval register (CSR47). Note that non- default value desired, then strict sequence setting INIT CSR0, waiting IDONE, then writing CSR47, then setting STRT CSR0 must observed, otherwise default value will overwritten. CSR47 section details.
Polling
there network channel activity there pre- post-receive pre- post-transmit activity being performed PCnet-PCI controller, then PCnet-PCI controller will periodically poll current receive transmit descriptor entries order ascertain their ownership. DPOLL CSR4 set, then transmit polling function disabled. typical polling operation consists following: PCnet-PCI controller will current receive descriptor address stored internally vector appropriate Receive Descriptor Table Entry (RDTE). will then current transmit descriptor address (stored internally) vector appropriate Transmit Descriptor Table Entry (TDTE). accesses will made following order: RMD1, then RMD0 current RDTE during arbitration, after that, TMD1, then TMD0 current TDTE during second arbitration. information collected during polling activity will stored internally appropriate CSRs. (i.e. CSR18, CSR19, CSR20, CSR21, CSR40, CSR42, CSR50, CSR52). UnOWNed descriptor status will internally ignored. typical receive poll product following conditions: PCnet-PCI controller does possess ownership current RDTE poll time elapsed RXON=1 (CSR0, PCnet-PCI controller does possess ownership next RDTE poll time elapsed RXON=1. RXON=0 PCnet-PCI controller will never poll RDTE locations. ideal system should always have least RDTE available possibility unpredictable receive event. (This condition requirement. this condition met, simply means that frames will missed system because there buffer space available.) typical system usually least RDTEs available possibility unpredictable receive event. Given that this condition satisfied, current next RDTE polls rarely seen hence, typical poll operation simply consists check status current TDTE. When there only RDTE (because RLEN ZERO), then there "next RDTE" ownership "next RDTE" cannot checked. there least RDTE, RDTE poll will rarely seen typical poll operation simply consists check current TDTE.
Transmit Descriptor Table Entry (TDTE)
after TDTE access, PCnet-PCI controller finds that that TDTE set, then PCnetPCI controller resumes poll time count reexamines same TDTE next expiration poll time count. TDTE set, Start Frame (STP) set, PCnet-PCI controller will immediately request order reset this descriptor. (This condition would normally found following LCOL RETRY error that occurred middle transmit frame chain buffers.) After resetting this descriptor, PCnet-PCI controller will again immediately request order access next TDTE location ring.
1-916
Am79C970
PRELIMINARY buffer length will reset. LANCE buffer length interpreted 4096-byte buffer. acceptable have length buffer transmit with acceptable have length buffer with start frame (STP) set, then microcode control proceeds routine that will enable transmit data transfers FIFO. PCnet-PCI controller will look ahead next transmit descriptor after performed least transmit data transfer from first buffer. (More than transmit data transfer possibly take place, depending upon state transmitter.) contents TMD0 TMD1 will stored Next Buffer Address (CSR64 CSR65), Next Byte Count (CSR66) Next Status (CSR67) regardless state bit. This transmit descriptor lookahead operation performed only once. PCnet-PCI controller does next TDTE (i.e. second TDTE this frame), then will complete transmission current buffer then update status current (first) TDTE with BUFF UFLO bits being set. This will cause transmitter disabled (CSR0, TXON=0). PCnet-PCI controller will have re-initialized restore transmit function. situation that matches this description implies that system been able stay ahead PCnet-PCI controller transmit descriptor ring therefore, condition treated fatal error. avoid this situation, system should always transmit chain descriptor bits reverse order.) PCnet-PCI controller does second TDTE chain, will gradually empty contents first buffer bytes needed transmit operation), perform single-cycle transfer update status first descriptor (reset TMD1), then perform data access second buffer chain before executing another lookahead operation. (i.e. lookahead third descriptor.) PCnet-PCI controller queue frames transmit FIFO. Call them frame frame "Y", where after "X". Assume that frame currently being transmitted. Because PCnet-PCI controller perform lookahead data transfer past frame "X", possible PCnet-PCI controller completely transfer data from buffer belonging frame into FIFO even though frame been completely transmitted. this buffer data transfer, PCnet-PCI controller will write intermediate status (change ZERO) frame buffer, frame uses data chaining.
last TDTE frame (containing ENP) been written, since frame been completely transmitted. Note that PCnet-PCI controller has, this instance, returned ownership TDTE host "normal" sequence. this reason, becomes imperative that host system should never read Transmit ownership bits order. Software should always process buffers sequence, waiting ownership before proceeding. There should problems software which processes buffers sequence, waiting ownership before proceeding. error occurs transmission before bytes current buffer have been transferred, then TMD2 TMD1 current buffer will written; such case, data transfers from next buffer will commence. Instead, following TMD2/TMD1 update, PCnet-PCI controller will next transmit frame, any, skipping over rest frame which experienced error, including chained buffers. This done returning polling microcode where PCnet-PCI controller will immediately access next descriptor find condition OWN=1 STP=0 described earlier. described that case, PCnetPCI controller will reset this descriptor continue like manner until descriptor with OWN=0 more transmit frames ring) OWN=1 STP=1 (the first buffer frame) reached. transmit operation, whether successful with errors, immediately following completion descriptor updates, PCnet-PCI controller will always perform another poll operation. described earlier, this poll operation will begin with check current RDTE, unless PCnet-PCI controller already owns that descriptor. Then PCnet-PCI controller will proceed polling next TDTE. transmit descriptor ZERO value, then PCnet-PCI controller will resume poll time count incrementing. transmit descriptor value ONE, then PCnet-PCI controller will begin filling FIFO with transmit data initiate transmission. This end-of- operation poll coupled with TDTE lookahead operation allows PCnet-PCI controller avoid inserting poll time counts between successive transmit frames. Whenever PCnet-PCI controller completes transmit frame (either with without error) writes status information current descriptor, then TINT CSR0 indicate completion transmission. This causes interrupt signal IENA CSR0 been TINbit CSR3 reset.
Am79C970
1-917
PRELIMINARY third buffer information gathered will stored chip, regardless state ownership bit. transmit flow, lookahead operations performed only once. This activity continues until PCnet-PCI controller recognizes completion frame (the last byte this receive message been removed from FIFO). PCnet-PCI controller will subsequently update current RDTE status with frame (ENP) indication set, write message byte count (MCNT) complete frame into RMD2 overwrite "current" entries CSRs with "next" entries.
Receive Descriptor Table Entry (RDTE)
PCnet-PCI controller does both current next Receive Descriptor Table Entry then PCnet-PCI controller will continue poll according polling sequence described above. receive descriptor ring length then there next descriptor polled. poll operation revealed that current next RDTE belong PCnet-PCI controller then additional poll accesses necessary. Future poll operations will include RDTE accesses long PCnet-PCI controller retains ownership current next RDTE. When receive activity present channel, PCnet-PCI controller waits complete address message arrive. then decides whether accept reject frame based active addressing schemes. frame accepted PCnet-PCI controller checks current receive buffer status register CRST (CSR41) determine ownership current buffer. ownership lacking, then PCnet-PCI controller will immediately perform (last ditch) poll current RDTE. ownership still denied, then PCnet-PCI controller buffer which store incoming message. MISS will CSR0 interrupt will generated IENA=1 (CSR0) MISSM=0 (CSR3). Another poll current RDTE will occur until frame finished. PCnet-PCI controller sees that last poll (either normal poll, last-ditch effort described above paragraph) current RDTE shows valid ownership, then proceeds poll next RDTE. Following this poll, regardless outcome this poll, transfers receive data from FIFO begin. Regardless ownership second receive descriptor, PCnet-PCI controller will continue perform receive data transfers first buffer. frame length exceeds length first buffer, PCnet-PCI controller does second buffer, ownership current descriptor will passed back system writing ZERO RMD1 status will written indicating buffer (BUFF=1) possibly overflow (OFLO=1) errors. frame length exceeds length first (current) buffer, PCnet-PCI controller does second (next) buffer, ownership will passed back system writing ZERO RMD1 when first buffer full. Receive data transfers second buffer occur before PCnet-PCI controller proceeds look ahead ownership third buffer. Such action will depend upon state FIFO when status been updated first descriptor. case, lookahead will performed 1-918
Media Access Control
Media Access Control engine incorporates essential protocol requirements operation compliant Ethernet/802.3 node, provides interface between FIFO sub-system Manchester Encoder/Decoder (MENDEC). engine fully compliant Section ISO/ 8802-3 (ANSI/IEEE Standard 1990 Second edition) ANSI/IEEE 802.3 (1985). engine provides programmable enhanced features designed minimize host supervision, utilization, pre- post- message processing. These include ability disable retries after collision, dynamic generation frame-by-frame basis, automatic field insertion deletion enforce minimum frame size attributes, automatic retransmission without reloading FIFO, automatic deletion collision fragments, reduces bandwidth use. primary attributes engine are: Transmit receive message data encapsulation. Framing (frame boundary delimitation, frame synchronization). Addressing (source destination address handling). Error detection (physical medium transmission errors). Media access management. Medium allocation (collision avoidance). Contention resolution (collision handling). Transmit Receive Message Data Encapsulation engine provides minimum frame size enforcement transmit receive frames. When APAD_XMT (CSR, 11), transmit messages will padded with sufficient bytes (containing 00h) ensure that receiving station will observe information field (destination address, source address, length/type, data FCS) 64-bytes. When ASTRP_RCV (CSR4, 10), receiver will
Am79C970
PRELIMINARY automatically strip bytes from received message observing value length field, stripping excess bytes this value below minimum data size bytes). Both features independently over-ridden allow illegally short (less than bytes frame data) messages transmitted and/or received. this feature reduces utilization because bytes transferred into main memory. Framing (Frame Boundary Delimitation, Frame Synchronization) engine will autonomously handle construction transmit frame. Once Transmit FIFO been filled predetermined threshold (set XMTSP CSR80), providing access channel currently permitted, engine will commence byte preamble sequence (10101010b, where first transmitted engine will subsequently append Start Frame Delimiter (SFD) byte (10101011b) followed serialized data from Transmit FIFO. Once data been completed, engine will append (most significant first) which computed entire data portion frame. data portion frame consists destination address, source address, length/type, frame data. user responsible correct ordering content each fields frame. receive section engine will detect incoming preamble sequence lock encoded clock. internal MENDEC will decode serial stream present this engine. will discard first 8-bits information before searching sequence. Once detected, subsequent bits treated part frame. engine will inspect length field ensure minimum frame size, strip unnecessary characters enabled), pass remaining bytes through Receive FIFO host. stripping performed, engine will also strip received bytes, although normal computation checking will occur. Note that apart from stripping, frame will passed unmodified host. length field value greater, engine will attempt validate length against number bytes contained message. frame terminates suffers collision before 64-bytes information (after SFD) have been received, engine will automatically delete frame from Receive FIFO, without host intervention. PCnetPCI controller ability accept runt packets diagnostics purposes proprietary networks.
Addressing (Source Destination Address Handling) first 6-bytes information after will interpreted destination address field. engine provides facilities physical, logical (multicast) broadcast address reception. Error Detection (Physical Medium Transmission Errors) engine provides several facilities which report recover from errors medium. addition, network protected from gross errors inability host keep pace with engine activity. completion transmission, following transmit status available appropriate areas: exact number transmission retry attempts (ONE, MORE, RTRY TRC). Whether engine Defer (DEF) channel activity. Excessive deferral (EXDEF), indicating that transmitter experienced Excessive Deferral this transmit frame, where Excessive Deferral defined 8802-3 (IEEE/ANSI 802.3). Loss Carrier (LCAR), indicating that there interruption ability engine monitor transmission. Repeated LCAR errors indicate potentially faulty transceiver network connection. Late Collision (LCOL) indicates that transmission suffered collision after slot time. This indicative badly configured network. Late collisions should occur normal operating network. Collision Error (CERR) indicates that transceiver respond with Test message within predetermined time after transmission completed. This failed transceiver, disconnected faulty transceiver drop cable, fact transceiver does support this feature disabled). addition reporting network errors, engine will also attempt prevent creation network error inability host service engine. During transmission, host fails keep Transmit FIFO filled sufficiently, causing underflow, engine will guarantee message either sent runt packet (which will deleted receiving station) invalid (which will also cause receiver reject message).
Am79C970
1-919
PRELIMINARY Medium Allocation IEEE/ANSI 802.3 Standard (ISO/IEC 8802-3 1990) requires that CSMA/CD monitor medium traffic watching carrier activity. When carrier detected, media considered busy, should defer existing message. 8802-3 (IEEE/ANSI 802.3) Standard also allows optional part deferral after receive message.
status each receive message available appropriate areas. Framing errors (FRAM) reported, although received frame still passed host. FRAM error will only reported error detected there integral number bytes message. engine will ignore additional bits message (dribbling bits), which occur under normal network operating conditions. reception additional bits will cause engine de-serialize entire byte, will result received message being modified. PCnet-PCI controller handle dribbling bits when received frame terminates. During reception, generated every serial (including dribbling bits) coming from cable, although internally saved value only updated eighth each byte boundary). framing error reported user follows: number dribbling bits there (FCS) error, then there Framing error (FRAM number dribbling bits there (FCS) error, then there also Framing error (FRAM number dribbling bits then there Framing error. There (FCS) error. Counters provided report Receive Collision Count Runt Packet Count network statistics utilization calculations. Note that engine detects received frame which pattern preamble (after first bits which ignored), entire frame will ignored. engine will wait network inactive before attempting receive additional frames.
ANSI/IEEE 802.3 -1990 Edition, 4.2.3.2.1: Note: possible carrier sense indication fail asserted during collision media. deference process simply times interFrame based this indication possible short interFrame generated, leading potential reception failure subsequent frame. enhance system robustness following optional measures, specified 4.2.8, recommended when InterFrameSpacingPart1 other than ZERO: Upon completing transmission, start timing interpacket gap, soon transmitting carrier Sense both false. When timing interFrame following reception, reset interFrame timing carrier Sense becomes true during first interFrame timing interval. During final interval timer shall reset ensure fair access medium. initial period shorter than interval permissible including ZERO.
engine implements optional receive part deferral algorithm, with first part inter-frame-spacing time second part inter-framespacing interval therefore PCnet-PCI controller will perform part deferral algorithm specified Section 4.2.8 (Process Deference). Inter Packet (IPG) timer will start timing InterFrameSpacing after receive carrier de-asserted. During first part deferral (InterFrameSpacingPart1 IFS1) PCnet-PCI controller will defer pending transmit frame respond receive message. counter will reset ZERO continuously until carrier de-asserts, which point counter will resume count once again. Once IFS1 period elapsed, PCnet-PCI controller will begin timing second part deferral (InterFrame Spacing Part IFS2) Once IFS1 completed, IFS2 commenced, PCnet-PCI controller will defer receive frame transmit frame pending. This means that PCnet-PCI controller will attempt receive receive frame, since will start transmit, generate collision PCnet-PCI controller will guarantee complete preamble (64-bit) (32-bit)
Media Access Management
basic requirement stations network provide fairness channel allocation. 802.3/Ethernet protocols define media access mechanism which permits stations access channel with equality. node attempt contend channel waiting predetermined time (Inter Packet internal) after last activity, before transmitting media. channel multidrop communications media (with various topological configurations permitted) which allows single station transmit other stations receive. nodes simultaneously contend channel, their signals will interact causing loss data, defined collision. responsibility attempt avoid recover from collision, guarantee data integrity end-to-end transmission receiving station.
1-920
Am79C970
PRELIMINARY sequence before ceasing transmission invoking random backoff algorithm. This transmit part deferral algorithm implemented option which disabled using DXMT2PD CSR3. part deferral after transmission useful ensuring that severe shrinkage cannot occur specific circumstances, causing transmit message follow receive message closely make them indistinguishable. During time period immediately after transmission been completed, external transceiver case standard connected device), should generate Test message nominal burst Times duration) pair (within after transmission ceases). During time period which Test message expected PCnet-PCI controller will respond receive carrier sense. ANSI/IEEE 802.3-1990 Edition, 7.2.4.6 (1):
prior bits being transmitted, Engine will abort transmission, append sequence immediately. sequence 32-bit Zeros pattern. Engine will attempt transmit frame total times (initial attempt plus retries) normal collisions (those within slot time). Detection collision will cause transmission re-scheduled, dependent backoff time that Engine computes. single retry required, will Transmit Frame Status. more than retry required, MORE will set. attempts experienced collisions, RTRY will (ONE MORE will clear), transmit message will flushed from FIFO. retries have been disabled setting DRTY CSR15, Engine will abandon transmission frame detection first collision. this case, only RTRY will transmit message will flushed from FIFO. collision detected after times have been transmitted, collision termed late collision. Engine will abort transmission, append sequence LCOL bit. retry attempt will scheduled detection late collision, transmit message will flushed from FIFO. 8802-3 (IEEE/ANSI 802.3) Standard requires "truncated binary exponential backoff" algorithm which provides controlled pseudo random mechanism enforce collision backoff interval, before re-transmission attempted. ANSI/IEEE 802.3-1990 Edition, 4.2.3.2.5:
conclusion output function, opens time window during which expects signal_quality_error signal asserted Control circuit. time window begins when CARRIER_STATUS becomes CARRIER_OFF. execution output function does cause CARRIER_ON occur, test occurs DTE. duration window shall least more than During time window Carrier Sense Function inhibited."
PCnet-PCI controller implements carrier sense "blinding" period within from de-assertion carrier sense after transmission. This effectively means that when transmit part deferral enabled (DXMT2PD cleared) IFS1 time from after transmission. However, since shrinkage below will rarely encountered correctly configured networks, since fragment size will larger than blinding window, then counter will reset worst case shrinkage/fragment scenario PCnet-PCI controller will defer transmission. addition, PCnet-PCI controller will restart "blinding" period carrier detected within IFS1 period, will commence timing entire IFS1 period. Contention Resolution (Collision Handling) Collision detection performed reported engine integrated Manchester Encoder/Decoder (MENDEC). collision detected before complete preamble/SFD sequence been transmitted, Engine will complete preamble/SFD before appending sequence. collision detected after preamble/SFD been completed,
enforcing collision (jamming), CSMA/CD sublayer delays before attempting retransmit frame. delay integer multiple slot Time. number slot times delay before re-transmission attempt chosen uniformly distributed random integer range:
where (n,10)." PCnet-PCI controller provides alternative algorithm, which suspends counting slot time/IPG during time that receive carrier sense detected. This aids networks where large numbers nodes present, numerous nodes collision. effectively accelerates increase backoff time busy networks, allows nodes involved collision access channel whilst colliding nodes await reduction channel activity. Once channel activity reduced, nodes resolving collision time their slot time counters normal.
Am79C970
1-921
PRELIMINARY Power Reset (POR) circuit, which ensures that analog portions PCnet-PCI controller forced into their correct state during power prevents erroneous data transmission and/or reception during this time.
Manchester Encoder/Decoder (MENDEC)
integrated Manchester Encoder/Decoder provides (Physical Layer Signaling) functions required fully compliant 8802-3 (IEEE/ANSI 802.3) station. MENDEC provides encoding function data transmitted network using high accuracy on-board oscillator, driven either crystal oscillator external CMOS level compatible clock. MENDEC also provides decoding function from data received from network. MENDEC contains
External Crystal Characteristics
When using crystal drive oscillator, following crystal specification used ensure less than ±0.5 jitter DO±. Table below.
Table Crystal Specification
Parameter Parallel Resonant Frequency Resonant Frequency Error Change Resonant Frequency With Respect Temperature 70°C)* Crystal Load Capacitance Motional Crystal Capacitance (C1) Series Resistance Shunt Capacitance Drive Level 0.022 Unit
Requires trimming specification; trim total.
External Clock Drive Characteristics
When driving oscillator from CMOS level external clock source, XTAL2 must left floating (unconnected). external clock having following characteristics must used ensure less than ±0.5 jitter DO±. Table Table Clock Drive Characteristics
Clock Frequency: Rise/Fall Time (tR/tF): XTAL1 HIGH/LOW Time (tHIGH/tLOW): XTAL1 Falling Edge Falling Edge Jitter: ±0.01% from -0.5 ±0.2 input (VDD/2)
MENDEC Transmit Path
transmit section encodes separate clock data input signals into standard Manchester encoded serial stream. transmit outputs (DO±) designed operate into terminated transmission lines. When operating into terminated transmission line, transmit signaling meets required output levels skew Cheapernet, Ethernet IEEE-802.3.
create internal transmit clock reference. Both clocks into MENDECs Manchester Encoder generate transitions encoded data stream. internal transmit clock used MENDEC internally synchronize Internal Transmit Data (ITXDAT) from controller Internal Transmit Enable (ITXEN). internal transmit clock also used stable rate clock receive section MENDEC controller. oscillator requires external 0.01% timing reference. accuracy requirements, external crystal used tighter because allowance on-board parasitics must made deliver final accuracy 0.01%.
Transmitter Timing Operation
fundamental mode crystal oscillator provides basic timing reference MENDEC portion PCnet-PCI controller. crystal divided two, 1-922
Am79C970
PRELIMINARY Transmission enabled controller. long ITXEN request remains active, serial output controller will Manchester encoded appear DO±. When internal request dropped controller, differential transmit outputs idle states, dependent TSEL Mode Register (CSR15,
TSEL LOW: idle state yields "ZERO" differential operate transformercoupled loads.
Receiver Path
principal functions Receiver signal PCnet-PCI controller that there information receive pair, separate incoming Manchester encoded data stream into clock data. Receiver section (see Receiver Block Diagram) consists parallel paths. receive data path ZERO threshold, wide bandwidth line receiver. carrier path offset threshold bandpass detecting line receiver. Both receivers share common bias networks allow operation over wide input common mode range.
IRXDAT* ISRDCLK*
TSEL HIGH: this idle state, positive with respect (logical HIGH).
Data Receiver
Manchester Decoder
Noise Reject Filter
Carrier Detect Circuit
IRXCRS*
*Internal signal
18220C-26
Figure Receiver Block Diagram
Input Signal Conditioning
Transient noise pulses input data stream rejected Noise Rejection Filter. Pulse width rejection proportional transmit data rate. Carrier Detection circuitry detects presence incoming data frame discerning rejecting noise from expected Manchester data, controls stop start phase-lock loop during clock acquisition. Clock acquisition requires valid Manchester pattern 1010b lock onto incoming message. When input amplitude pulse width conditions DI±, internal enable signal from MENDEC controller (IRXCRS) asserted clock acquisition cycle initiated.
clock from incoming Manchester pattern times with 1010b Manchester pattern. ISRDCLK IRXDAT enabled time after clock acquisition cell IRXDAT HIGH state when receiver idle ISRDCLK). IRXDAT however, undefined when clock acquired remain HIGH change state whenever ISRDCLK enabled. time through cell controller portion PCnet-PCI controller sees first ISRDCLK transition. This also strobes incoming fifth MENDEC Manchester "1". IRXDAT make transition after ISRDCLK rising edge cell state still undefined. Manchester clocked IRXDAT output time cell
Clock Acquisition
When there activity (receiver idle), receive oscillator phase locked internal transmit clock. first negative clock transition (bit cell center first valid Manchester "0") after IRXCRS asserted interrupts receive oscillator. oscillator then restarted second Manchester (bit time phase locked result, MENDEC acquires
Tracking
After clock acquisition, phase-locked clock compared incoming transition cell center (BCC) resulting phase error applied correction circuit. This circuit ensures that phaselocked clock remains locked received signal. Individual cell phase corrections Voltage Controlled Oscillator (VCO) limited 100% phase 1-923
Am79C970
PRELIMINARY fall time. ISRDCLK strobes data receiver output time determine value Manchester bit, clocks data IRXDAT following ISRDCLK. data receiver also generates signal used phase detector comparison internal MENDEC voltage controlled oscillator (VCO).
difference between phase-locked clock. Hence, input data jitter reduced ISRDCLK
Carrier Tracking Message
carrier detection circuit monitors inputs after IRXCRS asserted message. IRXCRS de-asserts times after last positive transition incoming message. This initiates reception cycle. time delay from last rising edge message IRXCRS de-assert allows last strobed ISRDCLK transferred controller section, prevents extra bit(s) message.
Differential Input Terminations
differential input Manchester data (DI±) externally terminated 40.2 resistors optional common-mode bypass capacitor, shown Differential Input Termination diagram below. differential input impedance, ZIDF, common-mode input impedance, ZICM, specified that Ethernet specification cable termination impedance using standard resistor terminators. devices used, also suitable value. differential inputs terminated exactly same pair.
Data Decoding
data receiver comparator with clocked output minimize noise sensitivity inputs. Input error less than minimize sensitivity input rise
Isolation Transformer PCnet-PCI
40.2
40.2 0.01
18220C-27
Figure Differential Input Termination
1-924
Am79C970
Collision Detection
detects collision condition network generates differential signal inputs. This collision signal passes through input stage which detects signal levels pulse duration. When signal detected MENDEC sets ICLSN line HIGH. condition continues approximately times after last LOW-to-HIGH transition CI±.
Carrier Sense, Transmit Active Collision Present indication.
Twisted-Pair Transmit Function
differential driver circuitry TXD± TXP± pins provides necessary electrical driving capability pre-distortion control transmitting signals over maximum length Twisted-Pair cable, specified 10BASE-T supplement 8802-3 (IEEE/ ANSI 802.3) Standard. transmit function data output meets propagation delays jitter specified standard.
Jitter Tolerance Definition
MENDEC utilizes clock capture circuit align internal data strobe with incoming stream. clock acquisition circuitry requires four valid bits with values 1010b. Clock phase-locked negative transition cell center second pattern. Since data strobed time, Manchester transitions which shift from their nominal placement through time will result improperly decoded data. With this criteria error, definition Jitter Handling peak deviation approaching crossing cell position from nominal input transition, which MENDEC section will properly decode data.
Twisted-Pair Receive Function
receiver complies with receiver specifications 8802-3 (IEEE/ANSI 802.3) 10BASE-T Standard, including noise immunity received signal rejection criteria (`Smart Squelch'). Signals meeting this criteria appearing RXD± differential input pair routed MENDEC. receiver function meets propagation delays jitter requirements specified standard. receiver squelch level drops half threshold value after unsquelch allow reception minimum amplitude signals offset carrier fade event worst case signal attenuation crosstalk noise conditions. Note that 10BASE-T Standard defines receive input amplitude external Media Dependent Interface (MDI). Filter transformer loss specified. T-MAU receiver squelch levels defined account insertion loss MHz, which typical type receive filters/transformers employed. Normal 10BASE-T compatible receive thresholds employed when (CSR15[9]) LOW. When (HIGH), Receive Threshold option invoked, sensitivity T-MAU receiver increased. This allows longer line lengths employed, exceeding target distance normal 10BASE-T (assuming typical cable). increased receiver sensitivity compensates increased signal attenuation caused additional cable distance. However, making receiver more sensitive means that also more susceptible extraneous noise, primarily caused coupling from co-resident services (crosstalk). this reason, recommended that when using Receive Threshold option that service should installed 4-pair cable only. Multipair cables within same outer sheath have lower crosstalk attenuation, allow noise emitted from adjacent pairs couple into receive pair, sufficient amplitude falsely unsquelch T-MAU.
Attachment Unit Interface (AUI)
(Physical Layer Signaling) (Physical Medium Attachment) interface which effectively connects MAU. differential interface provided PCnet-PCI controller fully compliant Section 8802-3 (ANSI/IEEE 802.3). After PCnet-PCI controller initiates transmission will expect data "looped-back" pair (when port selected). This will internally generate "carrier sense", indicating that integrity data path from intact, that operating correctly. This "carrier sense" signal must asserted within times after first transmitted (when using port). "carrier sense" does become active response data transmission, becomes inactive before transmission, loss carrier (LCAR) error will Transmit Descriptor Ring (TMD2, after frame been transmitted.
Twisted-Pair Transceiver (T-MAU)
T-MAU implements Medium Attachment Unit (MAU) functions Twisted-Pair Medium, specified supplement 8802-3 (IEEE/ANSI 802.3) standard (Type 10BASE-T). T-MAU provides twisted pair driver receiver circuits, including on-board transmit digital predistortion receiver squelch number additional features including Link Status indication, Automatic Twisted-Pair Receive Polarity Detection/Correction Indication, Receive
Link Test Function
link test function implemented specified 10BASE-T standard. During periods transmit pair 1-925
Am79C970
PRELIMINARY 10BASE-T Standard generated transmitter passed through twisted pair cable. Negative link beat pulses defined received signals with negative amplitude greater than with pulse width This negative excursion followed positive excursion. This definition consistent with expected received signal reverse wired receiver, when link beat pulse which fits template Figure 14-12 10BASE-T Standard generated transmitter passed through twisted pair cable. polarity detection/correction algorithm will remain "armed" until consecutive frames with valid identical polarity detected. When "armed", receiver capable changing initial previous polarity configuration based polarity. receipt first frame with valid following H_RESET link fail, T-MAU will utilize inferred polarity information configure RXD± input, regardless previous state. receipt second frame with valid with correct polarity, detection/correction algorithm will "lock-in" received polarity. second subsequent) frame detected confirming previous polarity decision, most recently detected polarity will used default. Note that frames with invalid have effect updating previous polarity decision. Once consecutive frames with valid have been received, T-MAU will disable detection/correction algorithm until either Link Fail condition occurs H_RESET activated. During polarity reversal, internal signal will active. During normal polarity conditions, this internal signal inactive. state this signal read software and/or displayed when enabled con
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