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ZR36060 INTEGRATED JPEG CODEC
Single-chip JPEG processor that integrates modules needed JPEG encoding decoding: Raster-to-block block-to-raster converter Strip buffer JPEG codec Motion video compression expansion capability: frames/sec, square pixel CCIR frames/sec, square pixel CCIR NTSC Three modes Rate Control (BRC): Auto Pass: still image compression, produces tightly controlled compressed code volume Single pass: motion video compression, keeps file size approximately fixed BRC: uses fixed quantization tables Glueless interface common video decoders (e.g., Philips, Brooktree, Samsung, ITT, Harris) Supports 16-bit video interfaces Supports master slave modes video synchronization Interfaces variety host controllers, ranging from dedicated high-performance ZR36057 controller generic low-cost microcontrollers clock speed grades available: ZR36060-27, MHz, CCIR video format ZR36060-29.5, 29.5 MHz, NTSC square pixel video formats Flexible compressed data interface: 8-bit master mode, supporting 29.5 Mbytes/sec* 16-bit slave mode, supporting 16.8 Mbytes/sec* 8-bit slave mode, supporting Mbytes/sec* peak data rates, with 29.5 clock) On-chip video processing, including: Mixing video sources Horizontal (1:2 1:4) vertical (1:2) down scaling Cropping compression programmable background color decompression 3.3V power supply with 5V-tolerant power consumption: (typical) operating frequency (typical) 29.5 operating frequency Power down mode power saving 100-pin PQFP package
Desktop video editing subsystems PCMCIA video capture cards Digital still cameras Digital video recording JPEG-based video conferencing systems
Video Decoder
Video Encoder
Audio Control Audio FIFO Graphics Sub-System
Audio Codec
ZR36057
ZR36060
Figure JPEG-Based Video Editing Subsystem Systems
ZORAN Corporation
3112 Scott Blvd
Santa Clara, 95054
(408) 919-4111
(408) 919-4122
January 1998
ZR36060 Integrated JPEG Codec Contents
Features. Applications Introduction.
ZR36060 ZR36060 JPEG Standard
JPEG baseline overview JPEG markers. Motion JPEG
Power Management Power-up Register Memory Description
General Control Registers.
Load Parameters Register. Code FIFO Status Register Code Interface Register. Code Mode Register Maximum Block Code Volume Register Markers Enable Register Interrupt Mask Register Interrupt Status Register Target Code Volume Register. Target Data Code Volume Register. Scale Factor Register Allocation Factor Register Accumulated Code Volume Register. Accumulated Total Activity Register Accumulated Truncated Bits Register
Notational Conventions
Signal Description Video Interface
Video Syncs Master Slave Modes
Master mode Slave mode
Data Formats. Video stream sampling cropping
PVALID control signal
Testing Registers.
Identification Registers Test Control Registers
Video Scaling
Horizontal down-scaling compression Vertical down-scaling compression Horizontal up-scaling decompression Vertical up-scaling decompression
Video Registers
Video Control Register. Video Polarity Register Scaling Register. Background Color Registers Sync Generator Registers Active Area Registers Sub-image Window Registers
Active Area Size Restrictions Spatial Video Streams
Host Interface
Interrupt Request Associated Registers
Code Interface.
Master Mode Slave Mode
Host abort code read write cycle Data alignment Code Slave mode. Transition between fields compression Transition between fields decompression
JPEG Marker Segments
Electrical Characteristics
Absolute Maximum Ratings. Operating Range Characteristics Timing Characteristics.
Pinout Mechanical Data Ordering Information
Operation.
ZR36060 Functional States State Transitions SLEEP State Loading Parameters Tables Data Flow Overview
Data flow compression Data flow decompression
Compression Decompression Modes. Compression Pass
Data corruption during compression
Statistical Compression Pass Auto Two-Pass Compression Tables-Only Compression Pass Decompression
Data corruption during decompression
ZR36060 Integrated JPEG Codec
INTRODUCTION
ZR36060
ZR36060 integrated JPEG codec targeted video capture editing applications desktop laptop computers. Figure shows example typical application, video editing subsystem computers. ZR36060 integrates functionality JPEG codec such ZR36050, raster-to-block converter such ZR36015, well strip buffer SRAM raster-to-block converter additional functions. based field proven, fully compliant Zoran JPEG device technology, incorporates Zoran's patented rate control mechanism. compression, ZR36060 accepts 4:2:2 digital video, performs optional cropping decimation, encodes into JPEG baseline compressed bitstream, which outputs host controller. decompression, receives bitstream from host controller, decodes back 4:2:2 format digital video, up-scales required, outputs video composite video encoder other destination. ZR36060 incorporates hardware support multiplexing video sources rectangular windows) compression, reconstructed video with another source decompression. operate video sync master slave, with 8-bit 16bit video widths. pixel flow control mechanism provided convenient implementation non-real-time video rates, such still picture compression.
VSYNC HSYNC BLANK PVALID SUBIMG Y[7:0] UV[7:0] VCLK VCLKx2
code interface ZR36060 operate 8-bit master, 8-bit slave 16-bit slave modes. slave mode, code transfer shares host interface, which generic enough able interface gluelessly with variety host controllers, ranging from dedicated, high performance ZR36057 common microcontrollers. ZR36060 CMOS device, requiring Volt power supply. inputs outputs Volt tolerant. power-down ("sleep") mode reduces current consumption very level, while preserving logic state device. block diagram ZR36060 shown Figure
ZR36060 JPEG Standard
JPEG standard, ISO/IEC 10918-1, defines whole range options compressing continuous-tone images baseline lossy compression process, extended lossy processes, lossless compression, hierarchical compression methods. ZR36060 implements baseline process. Even baseline method defined JPEG standard provide maximal flexibility choosing color space which image compressed image have almost unlimited number color components, these compressed single scan, multiple scans. Because main targeted application motion color video compression decompression, architecture ZR36060 supports particular subset: Since ZR36060 supports only 4:2:2 pixel format, supports three color components, single interleaved scan.
Clocks
Video Interface Internal Configuration Memory bits) (Registers, Markers, Tables)
1.2.1 JPEG baseline overview
JPEG baseline compression method based discrete cosine transform DCT. performed blocks samples, each color component, resulting coefficients each block. Thus, order normal raster-scanned image compressed, must first converted block format This requires that 8-line strip image (for 4:2:2, containing lines each color component) stored strip buffer, that samples re-ordered (see Figure subsequent stages compression, coefficients each block further re-ordered scanning block zig-zag sequence. Each coefficients quantized using appropriate value from 64-entry quantization table. ZR36060, possible define three different quantization tables, color component; generally, however, tables sufficient, luminance component chrominance components. quantized coefficients passed Huffman encoder, final stage process. Huffman coding performed separately coefficient each block (the
RTBSY DATERR
Strip Memory START FRAME COMP SLEEP RESET
JPEG CODEC Control CODE FIFO (512 bits)
CBUSY CODE [7:0]
CODE Host Interface
ADDR[1:0] JIRQ DATA[7:0]
Figure ZR36060 Block Diagram
ZR36060 Integrated JPEG Codec
first coefficient block), remaining coefficients. encoding methods used coefficients differ their details, this requires Huffman tables specified, since statistics luminance chrominance components generally quite different, separate Huffman tables required luminance chrominance, total four tables, ZR36060 supports this configuration. Baseline decompression essentially consists inverses each stages used compression, reverse order: Huffman decoding, dequantization, inverse DCT, conversion blocks back raster order using strip buffer. three formats, table specifications parameters required decoding image and/or tables contained marker segments, which sequences bytes that start with special two-byte codes called markers marker codes. bytes that follow marker specify length marker segment bytes, including length bytes including marker code itself. There three special stand-alone markers that associated with marker segments, mark start-of-image (SOI), restart (RST), endof-image (EOI). code values 0xFFD8 SOI, 0xFFD00xFFD7 0xFFD9 EOI. first byte every marker 0xFF. marker prefixed arbitrary number 0xFF bytes which discarded decoder. second byte marker defined values, except 0x00, which used follows. order permit decoder identify restart markers, they exist, marker, encoder stuffs 0x00 byte after every 0xFF byte that results from Huffman encoding. Note that this "byte stuffing" essential part JPEG standard, there definition standard bitstream that does include byte stuffing. ZR36060 always produces image bitstreams with byte stuffing, requires byte stuffing present order decode JPEG bitstream. JPEG standard also does define sort "markerless" bitstream data format. Certain markers marker segments defined standard "required", others, such restart markers table marker segments, optional. ZR36060 always includes required markers when produces compressed bitstream, programmed include certain optional markers. decompressed ZR36060, image bitstream must include required markers. markers included bitstream, required optional, handled automatically, without host intervention, ZR36060 decompression.
1.2.1.1 Minimum Coded Unit
compressed image data interleaved, case ZR36060, compression performed units Minimum Coded Unit, MCU, which contains more blocks each color component. 4:2:2 pixel format used ZR36060, where chrominance components decimated horizontally relative luminance (Y), consists blocks followed block each
1.2.1.2 Restart Intervals
ZR36060 supports compression decompression JPEG data that includes restart intervals. restart interval defined integral number MCUs, which processed "independent sequence", meaning that possible identify decode restart interval within JPEG data sequence, without need decode whatever data precedes context baseline compression, this significance because coefficients differentially encoded. Note that restarts optional; acceptable (and very common) restart markers encode whole image single sequence.
1.2.2.1 Required markers marker segments 1.2.2 JPEG markers
JPEG defines three data formats compressed bitstream, which supported ZR36060: interchange format, which contains specifications tables required decode image. abbreviated format compressed data, which contain some none tables, under assumption that remaining tables known decoder already loaded decoder loaded. This commonly used motion video, order save time otherwise required decode tables from their specifications. abbreviated tables-only format, which contains compressed data only tables. means which possible load tables into decoder; ZR36060 other means specifying tables device issuing explicit Load command. required markers baseline JPEG are: Start-of-image, (0xFFD8). This first marker JPEG image bitstream. Start-of-frame marker segment, SOF0 (0xFFC0), followed variable number bytes depending number color components. ZR36060, there always three components segment length bytes. segment used specify which quantization table each color component, number blocks each color component MCU. Start-of-scan marker segment, (0xFFDA), followed variable number bytes depending number color components. Huffman coded data follows immediately after last byte segment. case ZR36060, length segment always bytes. segment used specify which Huffman table each color component.
ZR36060 Integrated JPEG Codec
End-of-image, (0xFFD9). This marker follows last byte compressed data. compression, ZR36060 inserts optional marker segments, programmed into compressed data bitstream fixed order: APP, COM, DRI, DQT, DHT. These appear immediately after SOI, before SOF. decompression, they appear order position allowed JPEG standard; multiple marker segments same type supported extent allowed standard.
1.2.2.2 Optional markers marker segments
ZR36060 supports following optional markers segments: Application specific, APPn (0xFFE0-0xFFEF). standard allows different markers single image bitstream. ZR36060 insert marker compression. ZR36060 marker have segment length bytes. decompression, image bitstream contains single marker with segment length bytes fewer, host retrieve from internal memory after ZR36060 finished decompressing image; segment longer, data lost. there multiple segments, only last retrieved. Comment, (0xFFFE). restriction length bytes) same marker. Define restart interval, (0xFFDD). Specifies that restarts used, size MCUs restart interval. Define quantization tables, (0xFFDB). Specifies quantization tables used compress image. Define Huffman tables, (0xFFC4). Specifies Huffman tables used compress image. Restart, RSTm (0xFFD0-0xFFD7). Marks beginning restart interval compressed data. This marker inserted ZR36060 only restart mechanism enabled (see description Markers Enable Register). There RSTm marker before first restart interval. Note that when quantization Huffman tables loaded into ZR36060 host controller, they specified exactly same format used marker segments.
1.2.3 Motion JPEG
JPEG standard defines method compression single ("still") image. does have provision motion video, term "motion JPEG" simply means that each field video sequence compressed separate JPEG image bitstream, starting with ending with EOI. ZR36060 includes features that make this procedure straightforward.
Notational Conventions
following notational conventions used this data sheet: External signals: capital letters (e.g., COMP) Active-low mark: overbar (e.g., RESET) Buses: XXmsb_index:lsb_index (e.g., UV7:0) Register fields: XXmsb_index:lsb_index (e.g., Count27:16) Register types: read only write only read-write (data written read back) Numbers: numbers with prefix suffix decimal (e.g., 365, 23.19). Hexadecimal numbers indicated with `0x' prefix (e.g., 0xB000, 0x3). Binary numbers indicated with suffix (e.g., 010b, 0000110100011b). Control register fields italicized when mentioned text.
ZR36060 Integrated JPEG Codec
SIGNAL DESCRIPTION
Table Signal Description
Symbol Type Description Code/Host Port pins) CODE7:0 Code bus. Code Master mode, this 8-bit bidirectional used read write) compressed data from external code FIFO. 16-bit Code Slave mode, this used extension (the MSB) DATA bus. During after RESET this floating, with internal pull-ups. Code Chip Select, used only Code Master mode. This active-low output signal acts chip select from ZR36060 external code FIFO. goes active start read write cycle remains active throughout cycle. remains active continuously back-to-back read write cycles. During after RESET this logic high. Code Read (output enable), used only Code Master mode. This active-low output signal acts read strobe signal from ZR36060 external code FIFO. goes active VCLKx2 cycles after start read cycle. CODE input latched rising edge COE. During after RESET this logic high. Code Write, used only Code Master mode. This active-low output signal acts write strobe from ZR36060 external code FIFO. goes active VCLKx2 cycles after start write cycle. CODE data valid throughout strobe pulse permits external code FIFO latch data rising edge CWE. During after RESET this logic high. Code FIFO Busy. When ZR36060 master code CBUSY active-low input, used external code FIFO controller temporarily halt transfer compressed data. When ZR36060 slave code CBUSY active-low output. asserted (low) ZR36060 indicate internal code FIFO cannot accessed, empty/full condition (for compression/decompression modes respectively). deassertion, CBUSY driven high internal clock then released floating condition (needs external pullup). When ZR36060 connected ZR36057, CBUSY connected CBUSY input latter. During after RESET this floating (input mode). Data bus. This 8-bit bidirectional used access internal memory ZR36060. Code Slave mode, also used transfer compressed data. 16-bit Code Slave mode, CODE used extension DATA bus. During after RESET this floating with internal pullup. Address bus. This 2-bit used host access code register Code Slave mode), indirect address/data register which maps 1Kbyte internal memory array ZR36060. Chip Select. This active-low input signal acts chip select from host ZR36060. Write strobe. This active-low input signal acts write pulse from host ZR36060. DATA bus, with CODE extension 16-bit Code Slave mode, latched rising edge Read strobe. This active-low input signal acts read pulse from host ZR36060. DATA bus, with CODE extension 16-bit Code Slave mode, enabled output during pulse host latch ZR36060 data rising edge Acknowledge. Used ZR36060 notify host that current read write strobe pulse completed. During code access (Code Slave mode), ZR36060 will issue internal code FIFO empty/full compression/decompression respectively). deassertion, driven high VCLKx2 cycle then released floating condition (needs external pull-up). During after RESET this floating logic high with pullup).
CBUSY
DATA7:0
ADDR1:0
Video Port pins) Y7:0 16-bit video mode, these video luminance pins. 8-bit mode, these luminance/chrominance pins, multiplexed time according CCIR656 component order. compression these pins inputs, while decompression they outputs. During after RESET these pins floating with internal pullups. 16-bit video mode, these video chrominance pins. compression these pins inputs, while decompression they outputs. 8-bit video mode, these pins used: compression they ignored (inputs), decompression they floating. During after RESET these pins floating with internal pull-ups. Main Video Clock input. video interface ZR36060 synchronized this clock.
UV7:0
VCLKx2
ZR36060 Integrated JPEG Codec
Table Signal Description (Continued)
Symbol VCLK HSYNC VSYNC Type Description Digital video clock enable. Used qualifier video data. Must synchronized toggling half frequency VCLKx2, both 16-bit video width modes. Horizontal sync. When ZR36060 sync slave, HSYNC input, when sync master, HSYNC output. During after RESET this floating (input mode). Vertical sync. When ZR36060 sync slave, VSYNC input, when sync master, VSYNC output. During after RESET this floating (input mode). Digital video field indicator (odd/even). When ZR36060 sync master output, otherwise input. polarity input output, programmable. During after RESET this floating (input mode). Digital video composite blank output. Active only when ZR36060 sync master video bus, otherwise floating. horizontal vertical blanking areas programmable. During after RESET this floating with internal pullup. When ZR36060 compression mode, this input used additional qualifier (other than VCLK) video data signals sync signals. active level sampled this signal time when pixel sampled, indicates that this valid pixel. When ZR36060 decompression mode, this input used recipient video stall video stream ZR36060. non-active level sampled this signal will cause ZR36060 continue output current pixel instead proceeding next one. Once PVALID sampled active again normal pixel sequence resumes. ZR36060 video sync master, then PVALID active will freeze internal sync generator. polarity PVALID programmable. When ZR36060 connected ZR36057, PVALID connected PXEN output latter. This output dynamically indicates boundaries sub-image rectangle within main input output field size. When pixels within programmable rectangle output/input, SUBIMG active. sub-line consecutive pixels within rectangle, SUBIMG continuously active. polarity SUBIMG programmable. SUBIMG connected FEIN input SAA7110/11, read-enable input line buffer, FIFO, etc., permit pixel-by-pixel video mixing during compression decompression. During after RESET this logic high. Pixel Output Enable. Used disable video during decompression, permit pixel-by-pixel video mixing ZR36060 video output with another source. directly connected SUBIMG output, another suitable control signal.
BLANK
PVALID
SUBIMG
Control Status pins) RESET SLEEP Reset. When this input asserted ZR36060 goes into RESET state. When deasserted state machines IDLE state registers contain their default values. RESET must active least VCLKx2 cycles. Power-down mode. When this input active (low), ZR36060 goes into SLEEP (power-down) state, discontinuing chip operation consuming minimal supply current. This also initiates coarse locking internal VCLKx2 frequency. must toggled least once after initial RESET applied after power-up. SLEEP must remain least VCLKx2 cycles. process indication. This active-low output signal indicates completion field compression/decompression process. During after RESET this logic low. End-of-image marker indication. Code Slave mode, this active-low output signal indicates that End-Of-Image code word FFD9 (16-bit code bus), second byte this word (8-bit code bus), being output input. deasserted together with deassertion (rising edge) beginning next field process. During after RESET this logic low. Start compression/decompression command input. When ZR36060 IDLE state, waits active level this input order start compression decompression. Once active level sampled, ZR36060 will start compression decompression with next VSYNC with next VSYNC (depending FRAME input). detected correctly, START must remain least VCLK cycles. This input sampled ZR36060 together with START input. When START sampled active, then FRAME also active ZR36060 will start compressing/decompressing next field. Otherwise will start with next field. This output asserted when there data corruption event. deasserted together with deassertion (rising edge) upon beginning next field process. deassertion, DATERR floating (needs external pull-up). During after RESET this floating (logic high with pullup).
START
FRAME DATERR
ZR36060 Integrated JPEG Codec
Table Signal Description (Continued)
Symbol RTBSY Type Description compression this output signal indicates "nearly full" condition internal raster-to-block memory (strip buffer). This condition occurs when strip buffer fewer) pixels away from overflow condition. decompression RTBSY indicates that strip buffer near underflow condition. IDLE state RTBSY asserted. while RTBSY asserted data corruption event occurs (overflow underflow), RTBSY continues asserted together with DATERR until beginning next field process (deassertion END). data corruption occurs, RTBSY deasserted soon almost-overflow/underflow condition longer true. ZR36060 used with ZR36057/67, RTBSY should connected RTBSY input ZR36057/67. During after RESET this logic high. Interrupt request (active low). This output signal requests interrupt from host controller, interrupt request enabled event associated with interrupt request occurs. deasserted host responds interrupt reading interrupt status register, host disables interrupt, upon reset ZR36060. deassertion JIRQ floating (needs external pull-up). When JIRQ active, START signal disregarded. During after RESET this floating (logic high with pullup). Compression/Decompression. This output signal provides indication current operating mode ZR36060. When high, ZR36060 compression mode; when low, ZR36060 decompression mode. During after RESET this logic high.
JIRQ
COMP
Power Signals VDDPLL Ground Power supply (3.3V) Power (3.3V). page
VIDEO INTERFACE
video interface ZR36060 highly configurable, facilitate glueless connection most video decoders, encoders, MPEG decoders, frame memory controllers, graphics accelerators, etc. Vtotal Total number lines frame (e.g.- NTSC, video lines) Htotal Total number VCLKs (pixels) line (e.g.- CCIR NTSC, pixels) VsyncSize Length VSYNC pulse measured lines HsyncSize Length HSYNC pulse measured VCLKs BVstart Length lines) from VSYNC first non-BLANK line. BVend Length lines) from VSYNC last non-BLANK line. BHStart Length pixels) from HSYNC first non-BLANK pixel. BHend Length pixels) from HSYNC last non-BLANK pixel. VSPol Polarity VSYNC signal HSPol Polarity HSYNC signal FIPol Polarity signal BlPol Polarity BLANK signal FIVedge Defines which VSYNC edge signal changes state (leading trailing edge). This also reset point vertical counters, indicating previous field beginning field. After parameters properly initialized loaded (using Load command), sync generator free running, affected state JPEG codec. SyncRst
Video Syncs Master Slave Modes
ZR36060 supports video sync source modes: Sync Master ZR36060 internally generates video timing signals. Sync Slave ZR36060 synchronizes itself with external video source. 1-bit SyncMstr parameter selects mode. Normally, compression ZR36060 would slaved output video decoder, necessarily; example, ZR36060 could control frame memory Sync Master mode.
3.1.1 Master mode
When configured sync Master, ZR36060 drives following signals: HSYNC Horizontal sync VSYNC Vertical sync Even/Odd field indication BLANK Composite blanking parameters that configure sync generator when ZR36060 sync master (see Figure
ZR36060 Integrated JPEG Codec
register resets sync generator counters PVALID signal temporarily freeze counting sync signals.
BHend BHstart
BLANK
edge (leading trailing) used latch HSYNC signal programmed means FIVedge parameter. Changing FIDet will change even/odd interpretation. Note: HSYNC edge must precede latching VSYNC edge least VCLKs reliable latching.
HSYNC
HsyncSize
HSYNC
BVstart BVend
VsyncSize Htotal
Field EVEN Field VSYNC Field (Fields
Vtotal
BLANK
VSYNC
HSYNC Note: this example VSPol HSPol FIPol BlPol FIVedge VSYNC
Figure Video Sync Generation
EVEN Field (Fields
3.1.2 Slave mode
When configured sync Slave, ZR36060 samples following signals: HSYNC Horizontal sync VSYNC Vertical sync Even/Odd field indication parameters Vtotal, Htotal, VsyncSize, HsyncSize, BVstart, BVend, BHstart, BHend, BlPol, FIPol used Slave mode. VSPol, HSPol, FIDet FIVedge used follows: VSPol Polarity VSYNC input signal. HSPol Polarity HSYNC input signal. FIDet Exchange even/odd field interpretation after detection. (Detection accomplished ways according FIExt parameter, below.) FIVedge Defines reset point vertical counters indicating previous field beginning field. When FIExt also defines proper VSYNC edge used latch HSYNC internally detect even/odd field. field detection accomplished ways depending FIExt parameter (see Figure External indication means signal (FIExt toggling every VSYNC, indicating whether current field even odd. polarity programmable, using FIPol parameter, while even/odd interpretation exchanged using FIDet parameter. Internal detection (FIExt derived from latching state HSYNC each VSYNC. This useful when using ZR36060 with video sources that provide dedicated field indication signal. fields those where VSYNC edge latches HSYNC during short sync period, while even fields VSYNC edge latches HSYNC middle line (see Figure VSYNC
Note: this figure, VSPol HSPol FIPol FIDet FIVedge
Figure Field Detection Signal Relationships
Data Formats
When ZR36060 configured 16-bit video width (Video8=0), luminance signal Y7:0, chrominance signals multiplexed UV7:0 lines (see Figure When operating 8-bit video mode (Video8=1), both luminance chrominance signals Y7:0, multiplexed time according CCIR656 recommendation (U=Cb, V=Cr): U0,Y0,V0,Y1,U2,Y2,V2,Y3,. 16-bit video, pixels sampled every other rising edge VCLKx2, which enabled VCLK, video clock qualifier. polarity VCLK qualifier programmable VCLKPol parameter. 8-bit video sampled using rising edges VCLKx2, twice pixel rate. Note that duration pixel always VCLK period, with both 16-bit 8-bit video widths. internal counters video events based VCLK, that must always present half frequency VCLKx2) even when video interface configured 8-bit width. decompression, output pixel levels CCIR-601 compliant, with values range [16,235]. possible override this with Range parameter ZR36060 output full 256-level scale.
ZR36060 Integrated JPEG Codec
Note that both 16-bit 8-bit modes, ZR36060 does output, expect receive, control codes indicating timing information, video bus.
VCLKx2 VCLK 8-Bit Video Interface Y7:0 VSYNC 16-Bit Video Interface Y7:0 UV7:0 Active Area
Vstart
VSYNC Active Area
Vstart
VSPol FIVedge
VSYNC Active Area
Vstart
VSPol FIVedge
VSPol FIVedge
VSYNC Active Area
Vstart
Legend: Background Color Note: 16-bit video shown with VCLKPol that sampling when VCLK
VSPol FIVedge
Figure Video Data Formats,
Notes: active video area must overlap VSYNC pulse. other words, active area must always contained between trailing edge VSYNC next leading edge. There restrictions allowed values VStart VEnd. page
Video stream sampling cropping
Only pixels within rectangular active area sampled compressed compression) output decompression), shown Figure VSYNC signal indicates beginning field (the VSYNC edge polarity configured FIVedge VSPol). Vstart Vend parameters determine first last lines sampled field. leading edge HSYNC indicates beginning horizontal line (with HSYNC polarity according HSPol Hstart Hend parameters determine first last pixels sampled each line. Further processing such formatting, scaling compression done only pixels within active rectangle. decompression, video outputs background color, specified BackY, BackU, BackV parameters, outside processed active area rectangle. Figure Figure associated notes, describe active area aligned relative VSYNC HSYNC.
HSYNC
Figure Relationship VSYNC Active Video Area
HSYNC Active Area
Hstart
HSPol
HSYNC Active Area
Hstart
HSPol
Notes: line counting (for Vstart, Vend) always uses leading edge HSYNC pulse. Hstart specified from leading edge HSYNC. active video area allowed partially overlap HSYNC pulse. other words, Hstart could before after trailing edge HSYNC. There restrictions allowed values HStart HEnd. page
Figure Relationship HSYNC Active Video Area
3.3.1 PVALID control signal
continuous video stream usually used encoders decoders `real-time' video capture playback. However, sometimes desirable `hold' sample video pixels intermittently, especially when connected slow peripheral (such host interface compressing still image, memory controller) that cannot cope with real-time pixel rate. PVALID signal used this purpose. PVALID acts pixel qualifier indicating presence `valid' pixels (analogous action VCLK 16-bit mode). interrupt video stream out) period time with resolution VCLK, shown Figure VCLK PVALID differ that VCLK must always toggle half rate VCLKx2, while PVALID maintain continuous level. Only pixels qualified PVALID that within rectangular active area sampled. PVALID also acts `count enable' horizontal vertical counters that implement Hstart, Hend, Vstart, Vend. example, after leading edge HSYNC ZR36060 counts Hstart pixels qualified
Vstart
Background Color
VSYNC
Vend
Active Area (Rectangle)
Hend Hstart
Figure Active Area Video
ZR36060 Integrated JPEG Codec
PVALID, then samples pixels qualified PVALID until Hend. polarity PVALID programmable means PValPol parameter.
VCLKx2 VCLK HSYNC
8-Bit Video Interface Y7:0 Input PVALID Y7:0 Output Horizontal Counter Width Width
16-Bit Video Interface Y7:0 Input UV7:0 Input PVALID Y7:0 Output UV7:0 Output Horizontal Counter Width Width
Notes: this illustration, HSPol VCLKPol (sample when VCLK PValPol (valid when PVALID "Horizontal counter" represents internal counter used identify active area. PVALID granularity VCLK, both 16-bit video interface modes. PVALID toggle only pixel boundary, this figure when VCLK=0.
Figure PVALID Operation, 16-bit Video Widths
Video Scaling
ZR36060 incorporates scaler, that scale video active area, horizontally vertically, simple ratios. down-scale video before compressed, up-scale after decompressed. result permit straightforward implementation "half reen" "quarter reen" compression. horizontal down- up-scaling accompanied filtering. Note that this filtering disabled. Vertical downand up-scaling employ line dropping line replication respectively.
HScale 10b: decimation, with 5-tap filter. filter coefficients (0.0625, 0.25, 0.375, 0.25, 0.0625). 3.4.2 Vertical down-scaling compression
This specified 1-bit VScale parameter:
VScale down-scaling VScale decimation, line dropping
case vertical scaling, second, fourth,.etc. lines active area video field dropped before video compressed.
3.4.1 Horizontal down-scaling compression
This specified 2-bit HScale parameter. There three possible configurations:
3.4.3 Horizontal up-scaling decompression
compression, this specified HScale:
HScale 11b: up-scaling HScale 01b: interpolation HScale 10b: interpolation
HScale 11b: down-scaling HScale 01b: decimation, with 3-tap filter. filter coefficients (0.25, 0.5, 0.25).
ZR36060 Integrated JPEG Codec
interpolated samples created averaging neighboring samples, with weighting proportional distance interpolated point from samples used. where image outside other inside rectangle (see Figure 10). compression, this signal connected, example, synchronized sources live video multiplex their outputs. Some digital video sources have video which placed floating state (for example, Philips SAA7110 video digitizer/decoder); SUBIMG used float this while enabling second video source. Some possible options multiplex video decoders, decoder field memory, video decoder MPEG decoder, etc.
HSYNC
3.4.4 Vertical up-scaling decompression
compression, this specified VScale:
VScale up-scaling VScale interpolation, line replication
Active Area Size Restrictions
maximum allowed size active area rectangle pixels lines. ZR36060 JPEG codec always processes image with dimensions 2*8*x pixels integers This because 4:2:2 format, where blocks block block active area video interface must configured reflect dimensions before down-scaling compression, after up-scaling decompression. Tables show resulting restrictions imposed dimensions active area.
SVstart SVend
Source
Active Area Rectangle
VSYNC
Source
Sub-image Rectangle
SHend SHstart
Table Active Area, Horizontal Dimension (HEnd HStart)
Horizontal scaling scaling (1:1) Multiple Multiple Multiple Restriction
Figure Sub-image Parameters Compression There several inherent problems mixing video that system designer must bear mind: video sources must synchronized. This means that pixel clocks, horizontal vertical timing must come from only source which sync master. Both video sources must work same mode (16-bit 8-bit width). SHstart SHend parameters must chosen that boundaries sub-image rectangle (where SUBIMG changes state) coincide with boundaries between independent 4:2:2 units (units VCLKs, containing related samples) both sources. permit video mixing during decompression (playback), SUBIMG output externally connected input. This way, ZR36060 places video data only within outside) rectangle defined SUBIMG, floating output video outside inside) boundaries (see Figure 11). polarity SUBIMG signal defined SImgPol parameter, polarity signal place ZR36060 data inside outside rectangle during playback) defined PoePol parameter. Figure polarity SUBIMG been chosen float video outside subimage rectangle. Note that SUBIMG operate independently each other, they also used separately.
Table Active Area, Vertical Dimension (VEnd VStart)
Vertical Scaling scaling (1:1) Multiple Multiple Restriction
internal sampling scheme, first chrominance sample always assumed (Cb) sample. This directly controlled Hstart parameter. compression, Hstart must programmed appropriate value (even odd) order ZR36060 sample first (Cb) pixel, otherwise inversion occurs.
Spatial Video Streams
ZR36060 capable spatially mixing (multiplexing) video sources compression, also multiplexing ZR36060 output video with another video source during decompression. latter useful feature video editing, e.g. superimpose titles subtitles onto images. SUBIMG output signal creates sub-image rectangle defined SHstart, SHend, SVstart, SVend parameters,
ZR36060 Integrated JPEG Codec
HSYNC HSYNC
SVstart
SVend
Background Color Floating Video Sub-image Rectangle
VSYNC
ZR36060 Image Display
VSYNC
Active Area Rectangle
SHend SHstart
Floating Video
Figure Sub-image Parameters (with SUBIMG Wired POE) Decompression During decompression, SUBIMG rectangle overlaid active rectangle. other words, video will floating active areas indicated Figure regardless whether underlying pixels active background color (see also Figure 12). example Figure shows result spatial mixing decompressed video with another video source, seen destination (such video encoder). Figure shows timing transitions sub-image boundaries, same typical example which SUBIMG used control POE. timing 16-bit external video source example that Philips SAA7110.
Figure Video Output from ZR36060 Decompression, Using SUBIMG with
HSYNC
Background Color ZR36060 Image Rectangle
VSYNC
Source
Other Source Area
Figure ZR36060 Output Image Multiplexed with Another Source, Seen Video Encoder
ZR36060 Integrated JPEG Codec
VCLKx2 VCLK
VCLKx2 Y7:0 from ZR36060 SUBIMG (POE) Y7:0 External
8-Bit Video Interface VCLKx2
VCLKx2 Y7:0 from ZR36060 UV7:0 from ZR36060 SUBIMG (POE) Y7:0 External (SAA7110) UV7:0 External (SAA7110) Notes:
Sampled SAA7110
16-Bit Video Interface VCLKx2
Sampled SAA7110
this example SImgPol VCLKPol this example SUBIMG connected float ZR36060 video bus. SUBIMG changes state with resolution VCLK rising edge VCLKx2, both 8-bit 16-bit mode. 8-bit mode, first pixel enabled VCLKx2 after SUBIMG changes state, last pixel disabled VCLKx2 after SUBIMG changes. 16-bit mode, first pixel enabled VCLKx2 after SUBIMG changes state (this causes first pixel from ZR36060 appear VCLK instead complete VCLK period). last pixel disabled VCLKx2 after SUBIMG changes, avoid contention. This timing chosen match characteristics SAA7110. SUBIMG also connected SAA7110's output enable, FEIN.
Figure SUBIMG timing during decompression, shown 16-bit video widths
HOST INTERFACE
host interface generic interface with 8-bit bidirectional data bus, 2-bit address (that indirectly maps 1Kbyte internal memory space), pins. supports glueless low-glue interface many microprocessors microcontrollers, buses like ISA. When Code interface configured Slave mode (see section "Code Interface") some ZR36060 Host interface pins have dual functions, seen Figure
CODE7:0 CBUSY ZR36060 DATA7:0 ADDR1:0
CODE7:0 Code Only CBUSY ZR36060 DATA7:0 ADDR1:0 Code ZR36060 CBUSY DATA7:0 ADDR1:0 Code (Data Extension)
Host Only
Code/Host Shared
Code/Host Shared
Code Master Mode, 8-Bit Code
Code Slave Mode, 8-Bit Code
Code Slave Mode, 16-Bit Code
Figure Various Code Interface Modes Host Interface
ZR36060 Integrated JPEG Codec
ADDR1:0 address pins direct access registers (Figure Figure 17):
DATA7:0
When accessing Code FIFO (address 00b) Code Slave mode, signal reflects also CBUSY status (see section "Code Interface" more details). (But CBUSY only used host Code Slave mode must ignored other host accesses.) complete description internal memory register mapping, refer section "Register Memory Description".
Read Operation
ADDR1:0
Host Address Host Data
Host Address Bits)
Figure Address Space ZR36060 Code Master Mode
ADDR1:0
DATA7:0 CODE FIFO Host Address Host Data
Host Address Bits)
CODE7:0 CODE FIFO
DATA7:0 Host Address Host Data
Code FIFO register bits wide, depending Code16 parameter. When 16-bit Code Slave mode, CODE7:0 extension DATA7:0 bus.
ADDR1:0
Figure Address Space ZR36060 Code Slave Mode
Write Operation
access ZR36060's internal Code FIFO Code Slave mode only), read write operations directed address 00b. more information Code FIFO access, refer section "Code Interface". access ZR36060's internal registers markers array, host must first write 10-bit host address, followed read write 8-bit host data register. Note that host address self-incrementing. However, does need re-written every data access, only different register memory location accessed. host address location accessed changed writing register, register, both, required. host interface asynchronous interface (see Figure 18). Internally, however, interface synchronized internal clock twice frequency VCLKx2), VCLKx2 must exist stable, locked, before host access take place. Host-ZR36060 handshake performed using strobe pulses, signal. Some time after goes low, activated ZR36060 acknowledge that ready input output host code data. Only after this event host allowed release strobe. ZR36060 acknowledges access cycle releasing ACK. slow host extend strobe pulse beyond activation signal ZR36060. read cycle, data from ZR36060 stays until after signal deasserted. write cycle, data strobed rising edge Note that, guaranteed that minimum strobe width always larger than minimum specified Timing Characteristics, signal ignored.
DATA7:0 ADDR1:0 Host Address Host Data
Figure Asynchronous Operation Host Interface
Interrupt Request Associated Registers
ZR36060 capable requesting interrupt from host controller means JIRQ output signal. This section describes protocol registers associated with interrupt request. interrupt request occur consequence more following events: Assertion DATERR output data corruption event). Assertion output. Assertion (end-of-image marker detection) output during decompression. active rectangle video field (EOAV) which being processed ZR36060. Each events dedicated (DATERR, END, EOI, EOAV, respectively) Interrupt Mask Register that enables disables interrupt requesting event. Each events also status Interrupt Status Register.
ZR36060 Integrated JPEG Codec
DATERR bits exactly reflect levels DATERR output pins, respectively, with positive logic opposed negative logic output pins). should only used when decompressing Code Slave mode; Code Master mode meaningless. exactly reflects state signal (but with positive logic). EOAV indicates that last line active area defined active area parameters), been sampled displayed) ZR36060. Note that Auto Two-Pass Compression mode, EOAV asserted only first pass. DATERR, END, EOI, EOAV Interrupt Status bits when respective event occurs, cleared together with their respective pins (with exception EOAV, which does have associated with beginning next process, i.e.- next START. Note that Interrupt Status Register bits always reflect valid status information without regard whether their corresponding interrupts enabled Interrupt Mask Register. When interrupt-enabled event occurs, JIRQ asserted, once ZR36060 asserts (completion field process, i.e. compression decompression current field) moves WAIT-ISR state (see state diagram Figure 28). JIRQ remains asserted until host reads Interrupt Status Register (see Figure 19). When this happens JIRQ deasserted ZR36060 completes process returns IDLE state, ready sample START next field process. Interrupt Status Request register includes another pair bits, ProCount1:0, that related interrupt requests, located this register convenience. ProCount1:0 output modulo-4 cyclic counter that advances with every start process (every rising edge END). reset only RESET which initializes counter 01b. used host controllers indication field dropped ZR36060 (e.g., when ZR36060 outputs field after next already started).
DATA7:0 ADDR1:0 JIRQ
STATUS Address STATUS Data
Figure Interrupt Acknowledgment Reading Interrupt Status Register
CODE INTERFACE
code interface modes operation: Code Master mode Code Slave mode operating mode code port selected through CodeMstr register bit. After RESET ZR36060 defaults Code Master mode. With 29.5 VCLKx2, peak code throughput 29.5 MByte/sec Master mode, 16.8 MByte/sec 16-bit Slave mode MByte/sec 8-bit Slave mode. With VCLKx2, peak code throughput MByte/sec Master mode, 15.4 MByte/sec 16-bit Slave mode MByte/sec 8-bit Slave mode. master mode almost identical master mode ZR36050. compatible with ZR36057 JPEG controller with ZR36055 JPEG controller. slave mode compatible with common microprocessors microcontrollers. CFIS parameter, that determines cycle time this mode, limited values (one VCLKx2 cycle) VCLKx2 cycle) CAEN signal ZR36050 does exist ZR36060. Master mode cycle starts with activation CCS, rising edge VCLKx2. remains active throughout cycle remains active continuously back-to-back cycles. read cycle, executed during decompression, goes active VCLKx2 period after beginning cycle remains active until cycle. Data strobed trailing edge COE. Similarly, write cycle, executed during compression, goes active VCLKx2 period after beginning cycle remains active until cycle. Examples shown Figure Figure CBUSY sampled VCLKx2 before beginning each cycle active, inhibits cycle. cycle started same time CBUSY sampled active completes normally. Note: CBUSY status bits valid Code Master mode.
Master Mode
this mode compressed data transferred 8-bit CODE bus, using CCS, COE, outputs inform system when code cycle taking place, CBUSY input stall further accesses until system available again. Master mode differs from ZR36050's master mode minor ways:
ZR36060 Integrated JPEG Codec
16-bit width (Code16 CODE7:0 extension DATA7:0]to transfer 16-bit words. byte ordering exchanged using Endian parameter. Code Slave mode accesses asynchronous (Figure 22). (Code Chip-Select) ADDR1:0 inputs deasserted after every cycle, order achieve best performance, left asserted burst code transfer cycles. host must select three different methods handshake with ZR36060 throughout compression decompression process:
Code Write (Compression) CBUSY CODE7:0 (output)
VCLKx2 CBUSY CODE7:0 (input)
Code Read (Decompression)
CBUSY signal, signal, polling CFIFO level bits. CBUSY used indication empty/full status internal code FIFO ZR36060. When CBUSY active (low), means that code FIFO empty (during compression) full (during decompression). When host uses this signal, must sample CBUSY prior each code access, hold assertion until CBUSY deasserted. ZR36060's signal indicates permission complete current cycle. Assertion indicates that internal code FIFO empty (during compression) full (during
Code Read (Compression) ADDR[1:0]
Cannot perform strobe
Figure Master Mode Operation Code Bus, with CFIS=0b VCLKx2 Cycle)
VCLKx2 CBUSY CODE7:0 (input)
Code Read (Decompression)
Code Write (Compression) CBUSY
CBUSY DATA7:0 (CODE7:0)
CFIFO Empty (Stall Access)
Code Write (Decompression)
CODE7:0 (output)
ADDR[1:0] CBUSY DATA7:0 (CODE7:0)
Strobe held
Figure Master Mode Operation Code Bus, with CFIS=1b VCLKx2 Cycle)
Slave Mode
Slave mode, access internal code FIFO accomplished using host interface, reading writing (depending compression decompression mode respectively) direct access address zero (ADDR1:0 00b). data width bits, depending Code16 parameter: 8-bit width (Code16 Only DATA7:0 used code transfer.
CFIFO Empty (Stall Access)
Notes: pulsed, maintained active burst read write pulses. granted when CBUSY active, both compression decompression. example (compression) shows system using CBUSY decide when perform next strobe. bottom example (decompression) shows system using decide when terminate current strobe. Note extension cycle when FIFO full.
Figure Slave Mode Operation Code
ZR36060 Integrated JPEG Codec
decompression), therefore transfer successfully completed. host using this signal must terminate strobe before ZR36060 acknowledges cycle asserting ACK. This actually stall host middle compressed data stream, between compressed data fields case continuous operation, host attempts read write) FIFO while completely empty full). system must designed CBUSY equivalents, below) output signal handshake, both. Maximum code transfer rate performance achieved when using CBUSY handshake 16-bit code width. host also access status register interrogate full/empty status internal code FIFO CBUSY (positive logic opposed CBUSY state), pair read-only bits, CFIFO1:0, which indicate fullness code FIFO follows: CFIFO1:0 00b: less than FIFO occupied. CFIFO1:0 01b: more, less than 1/2, FIFO occupied. CFIFO1:0 10b: more, less than 3/4, FIFO occupied. CFIFO1:0 11b: more FIFO occupied. Using this register, host poll fifo status directly (instead using CBUSY signals), determine when should temporarily stop code transfer. However, system must guarantee minimum strobe widths, since being used. After last code word input decompression) output compression), ZR36060 asserts signal, indicating code stream with End-Of-Image marker. CFIFO1:0 status bits valid after code stream signal (EOI) corresponding status have been asserted.
5.2.1 Host abort code read write cycle
During compression decompression process host must obey handshake rules create valid code file. host safely abort (e.g.- timeout) cycle only after signal asserted. code transfer cycle aborted host before this, behavior ZR36060 will unpredictable, must reset resume normal operation. Figure shows example code transfer abort after asserted.
5.2.2 Data alignment Code Slave mode
compression, code slave mode, ZR36060 always completes compressed data file each field that 32-bit (double-word) aligned. This true both 8-bit 16-bit interface modes. variable number padding bytes value 0xFF appended ZR36060 after marker, complete last double word. decompression, such padding bytes constitute legal preamble marker code next field, thus ignored ZR36060.
ADDR1:0 CBUSY DATA7:0 CODE7:0 Data Code Code Data Attempt Code FAIL! Data Code CFIFO Full Ignored
This example shows status register reads interleaved with code FIFO write transactions. After end-of-image code, instead waiting long (for signal) until next field, host decide abort cycle.
Notes:
host reads status register, receives normally. host writes some code bytes (two this example), ZR36060 asserts normally. After second code write cycle, ZR36060 senses end-of-image code indicating last code byte current field asserts CBUSY. this example host reads status register, asserted, independently CBUSY. This access code FIFO while CBUSY asserted. issued ZR36060, until after beginning next field. host stalled while, then decides abort cycle, i.e.- release strobe without from ZR36060. ZR36060 senses this situation abort cycle ignores strobe. Again note, that this only allowed while asserted, middle process. host decides read status register. This operation completed normally. host writes code into ZR36060. ZR36060 already started decompressing field, CBUSY released issued.
Figure Example ZR36060 Interleaved Code/Data Accesses Abort Access
ZR36060 Integrated JPEG Codec
8-bit interface mode, number appended bytes 16-bit interface mode, number appended bytes Note that both cases, number bytes from first byte including second byte exact multiple ZR36060 actually appends more bytes. Note also that 16-bit mode, byte required make total multiple ZR36060 actually appends bytes. between consecutive fields showing behavior EOI, CBUSY signals. CBUSY asserted after last padding byte been read out. remains asserted continuously until first code byte next field available. code read shown figures while CBUSY asserted, with host access stalled. asserted soon read cycle last byte marker code (0xD9) complete. asserted only after compressed data, including padding bytes, read out, post-compression calculations completed their results stored hostaccessible registers. this time ZR36060 returns IDLE state. Compression next field started when ZR36060 senses START signal active.
5.2.3 Transition between fields compression
compression, Figure shows code transfer with 8-bit interface Figure with 16-bit interface, transition
ADDR1:0 CBUSY End-Of-Image marker DATA7:0
field process Start field process START
Start-Of-Image marker
32-Bit Alignment (Worst Case Padding) CODE Field CODE Field
Figure 8-Bit Code Slave Mode Compression, Transition Between Consecutive Fields
ADDR1:0 CBUSY End-Of-Image marker DATA7:0 CODE7:0 XXXX XXFF D9FF FFFF FFFF
field process Start field process START
FFD8 Start-Of-Image marker
FFXX
32-Bit Alignment (Worst Case Padding) CODE Field
CODE Field
Figure 16-Bit Code Slave Mode Compression, Transition Between Consecutive Fields
ZR36060 Integrated JPEG Codec
5.2.4 Transition between fields decompression
decompression, Figure shows code transfer with 8-bit interface Figure with 16-bit interface, transition between consecutive fields, showing behavior EOI, CBUSY signals. JPEG compressed files input ZR36060 size, required 32-bit (double-word) aligned. ZR36060 detects marker (0xFFD9), asserting CBUSY next write strobe. Note that host allowed write additional byte after marker code 8-bit mode, additional word after word containing second byte marker code 16-bit interface mode. This byte word discarded ZR36060. this discarded code byte word contained both bytes marker next field, ZR36060 automatically reconstructs marker when starts decompressing next field. Note that CBUSY remain unasserted until asserted, host other means detect marker code therefore does issue additional write strobe. Attempts access code FIFO while CBUSY asserted will held until FIFO available again, using signal. this example, pulse shown being extended until next field begins, when CBUSY deasserted. asserted only after whole decompressed field been output from video interface. this time ZR36060 sets EOAV status returns IDLE state. Decompression started again when ZR36060 senses START signal active.
ADDR1:0 CBUSY DATA7:0 End-Of-Image marker CODE Field
field process Start field process START
Start-Of-Image marker
CODE Field
Figure 8-Bit Code Slave Mode Decompression, Transition Between Consecutive Fields
ADDR1:0 CBUSY DATA7:0 CODE7:0 XXXX XXXX XXFF End-Of-Image marker CODE Field D9XX XXXX
field process Start field process START
FFD8 Start-Of-Image marker
FFXX
CODE Field
Figure 16-Bit Code Slave Mode Decompression, Transition Between Consecutive Fields
ZR36060 Integrated JPEG Codec
OPERATION
ZR36060 Functional States
purposes this description, ZR36060 viewed having states: RESET this state RESET input held active. SLEEP Power-down. SLEEP input held active this state. IDLE asserted ZR36060 waiting START. WAIT-ACTIVE After ZR36060 sensed START asserted, waits beginning active area next field processed (this depends state FRAME when START sampled active). deasserted. Compression active area. video input, code data output. deasserted. Decompression (expansion) active area. video output, code data input. deasserted. WAIT-ISR After ZR36060 finished compression decompression asserted while JIRQ active (due non-masked interrupt), ZR36060 waits this state host read Interrupt Status Register.
active area[1] compression START
Power-Up
RESET
RESET
SLEEP RESET
SLEEP RESET SLEEP SLEEP SLEEP
IDLE
SLEEP
START JIRQ (active area) JIRQ
WAIT ACTIVE
active area[1] decompression
JIRQ
JIRQ JIRQ
State Transitions
Figure depicts states their transitions.
JIRQ
WAIT
SLEEP State
this state, pins remain logic states they were immediately before transition SLEEP. host, video code interface operation allowed SLEEP state. When ZR36060 leaves SLEEP state returns IDLE, ready next compression decompression operation. This state also used lock internal frequency VCLKx2, mandatory through SLEEP state least once after power-up before operating device (see section "Power Management Power-up").
Active area correct field, depending state FRAME when START sampled active.
Figure ZR36060 Functional States Then, host sets ZR36060's (write-only) Load bit. This commands ZR36060 initialize "Load" internal hardware blocks with parameters internal memory, also decode Huffman Quantization tables into internal form required compression decompression. While ZR36060 performing this Load operation, (read-only) Busy `1'. host must poll completion loading, i.e.- wait Busy reset `0', before starting compression decompression process. START signal ignored during execution Load, i.e.- ZR36060 remains IDLE state (with asserted). Only after Load complete (Busy reset), parameter values become effective, ZR36060 ready sample START move WAIT-ACTIVE state start compression decompression process (see Figure 29). Parameters status registers read ZR36060 state with exception RESET SLEEP.
Loading Parameters Tables
Prior compression decompression process host must load appropriate parameters tables into ZR36060. parameters affect compression/decompression mode, video interface, operation code port. parameters tables loaded only when ZR36060 IDLE state. First, host controller writes (via host interface) desired parameters and/or tables their correct locations 1Kbyte internal memory (see section "Register Memory Description" details).
ZR36060 Integrated JPEG Codec
System decides compress next field (pulls START low). START FRAME state IDLE WAIT ACTIVE RTBSY CBUSY Video System senses deasserted, deasserts START compress next field only, then stop.
using PVALID input. This useful, example, when compressing still pictures.
Strip Memory
JPEG Codec
CODE FIFO CODE
Delay while ZR36060 completes execution Load command.
Figure Data Flow Compression, Code Master Mode When code interface operates slave mode (see Figure scenario almost identical. main difference that CBUSY output ZR36060, used indicate that code FIFO "nearly empty", thus host must stop reading code until CBUSY indicates that FIFO occupancy above threshold.
Figure IDLE WAIT-ACTIVE state transition
Data Flow Overview
This section provides overview data flow ZR36060 during compression decompression. this purpose useful view ZR36060 roughly JPEG engine with dual port data buffer each side: code FIFO buffer side video buffer (strip buffer) other side (see Figure through Figure 33).
Strip Memory Video
JPEG Codec
CODE FIFO CODE
6.5.1 Data flow compression
video input, after being processed video interface, written strip buffer raster format. JPEG engine reads data block format, writes JPEG code into code FIFO other side. From FIFO data transferred either ZR36060 itself, code master, host controller, ZR36060 code slave mode. When ZR36060 code master (see Figure writes code long CBUSY input asserted. When code FIFO empty ZR36060 does perform code write cycles. host controller slow asserts CBUSY long, code FIFO fill order prevent overflow, ZR36060 stops reading data from strip buffer. this situation continues long enough, strip buffer overflows, because video keeps flowing strip buffer overflow data corruption event. system level this event prevented means: First, host should able accept code same rate generated ZR36060. Second, some system configurations have capability halt video input stream when strip buffer close overflow pixels, less, from overflow). ZR36060 indicates this "nearly full" condition with RTBSY output. configuration implementing this ZR36060 master video syncs, system stops video
RTBSY
CBUSY
Figure Data Flow Compression, Code Slave Mode
6.5.2 Data flow decompression
JPEG code transferred code into code FIFO, either ZR36060, Code Master mode, host, Code Slave mode. JPEG engine writes decoded video into strip buffer block format. video interface reads video raster format, executes post-processing operations outputs video digital video bus. When ZR36060 code master (see Figure reads code long CBUSY input asserted. Whenever code FIFO full ZR36060 stops reading code. host controller slow asserts CBUSY long, code FIFO become empty. order prevent underflow ZR36060 stops writing data into strip buffer. this situation continues long enough, strip buffer underflows, because video unit keeps reading video from strip buffer, keep with timing digital video bus. strip buffer underflow data corruption event. system level this event prevented means: First, system should able provide code rate required ZR36060; second, some system configurations have capability stop video output stream when strip buffer close underflow pixels, less, away from underflow). ZR36060 indicates this "nearly empty" condition with RTBSY output. configuration implementing this ZR36060 master video syncs, system stops video
ZR36060 Integrated JPEG Codec
using PVALID input. This useful, example, when decompressing still pictures.
Processed Fields VSYNC Strip Memory Video JPEG Codec CODE FIFO CODE START FRAME RTBSY CBUSY state IDLE WAIT ACTIVE IDLE WAIT ACTIVE IDLE EVEN EVEN
Figure Data Flow Decompression, Code Master Mode When code interface operates slave mode (see Figure scenario almost identical. main difference that CBUSY output ZR36060, used indicate that code FIFO "nearly full", thus host must temporarily stop writing code until CBUSY indicates that FIFO occupancy below threshold.
Figure Compression With START FRAME Continuously Asserted FRAME active when START sampled (Figure 35), ZR36060 always starts compressing next field (i.e., next VSYNC).
Processed Fields
Strip Memory Video
JPEG Codec
CODE FIFO CODE VSYNC START
RTBSY
CBUSY
FRAME
Figure Data Flow Decompression, Code Slave Mode
IDLE
WAIT
IDLE
IDLE
ZR36060 decompression mode (called simply decompression), four compression modes: Compression Pass Statistical Compression Pass Auto Two-Pass Compression Tables-Only Compression Pass following sections describe these modes.
WAIT ACTIVE
WAIT
Compression Decompression Modes
state IDLE
Figure Compression With START Continuously Asserted FRAME Deasserted VSYNC edge used ZR36060 make decision `next' field configurable with FIVedge parameter (leading trailing edge). During IDLE, CBUSY active code slave mode, preventing host controller from reading code, since code FIFO buffer empty. Once compression process starts, CBUSY released host controller expected read code. code master mode, ZR36060 drives code only after compression process starts active area begins. When compression field stopped because interrupt request targeted host (JIRQ assertion), then upon completion ZR36060 asserts signal returns IDLE state, looking again START FRAME. Note that does matter host controller continuously asserts START (and/or FRAME) only asserts START (and/or FRAME) after ZR36060 asserts END. reason that ZR36060 interrogates START only when IDLE state. Figure
Compression Pass
When ZR36060 IDLE state, after correct initialization been done host (loading parameters and/ tables), waits command start compressing (assertion START). RTBSY asserted this time. Once ZR36060 senses active (low) START, checks level FRAME, then, FRAME active (Figure 34), starts compressing next field (i.e., next VSYNC). Note: FRAME maintained active, consequently will detected active every time START sampled active, ZR36060 will compress only fields. This convenient method implementing field decimation
ZR36060 Integrated JPEG Codec
DATERR enabled interrupt requesting event, JIRQ asserted together with assertion DATERR output, when ZR36060 completes current process enters WAIT-ISR state remains there, ignoring START, until host reads Interrupt Status register. this time ZR36060 goes back IDLE state again ready start process, soon samples START active. both cases, DATERR deasserted beginning next process, i.e. simultaneously with deassertion END.
IDLE WAIT ACTIVE IDLE WAIT ACTIVE IDLE
Host decides compress next field only VSYNC START FRAME state
Processed Fields
compression ZR36060 identifies data corruption condition strip buffer overflows,
Figure Compression with Pulsed START compression pass always executed with Rate Control (BRC). every compression process ZR36060 writes accumulated code volume (ACV) into register. also calculates iteration scale factor, based target accumulated code volumes, and, (Fixed Scale Factor) equals zero, writes scale factor Scale Factor register. uses this value register scale factor compressing next image field. host only program initial scale factor used compressing first field. Otherwise, FSF=1, ZR36060 uses fixed scale factor fields. compression pass ZR36060 does update Allocation Factor (AF). During encoding each block ZR36060 calculates measure spatial "activity" this block, denoted BACT. Block Accumulated Code Volume (BACV) exceeds specified allocation (given BACT*AF), exceeds Maximum Block Code Volume (MBCV), code block truncated accordingly. Note that both means rate controlling (namely truncation Allocation Factor, truncation MBCV) cannot turned directly, their effects reduced insignificance setting MBCV and/or their maximum values. Note: Allocation Factor only valid compression pass follows Statistical Pass. only Compression Passes executed, mode normally used motion JPEG compression, Allocation Factor must maximum value, otherwise image will compressed correctly.
active edge VSYNC (leading trailing edge controlled FIVedge parameter) next video field arrives before current field asserted.
Statistical Compression Pass
this mode ZR36060 goes through calculations involved encoding input video, accumulating code volume without writing code code FIFO. does assert CCS, COE, code master, CBUSY code slave. process ZR36060 calculates scale factor allocation factor writes them into their respective registers, writes accumulated values into their respective registers. Then asserts signal returns IDLE state.
Auto Two-Pass Compression
this mode ZR36060 first executes Statistical Compression Pass, then, without asserting END, immediately starts Compression Pass. Activation START (and optionally FRAME) required only first pass. second pass follows immediately with next VSYNC, without regard START FRAME. (Note that START FRAME only sampled when ZR36060 IDLE, this mode ZR36060 does into IDLE between passes). This mode only works correctly exactly same image data ZR36060 both passes.
6.10 Tables-Only Compression Pass
6.7.1 Data corruption during compression
during compression field ZR36060 senses data corruption event, immediately asserts DATERR output. However, ZR36060 continues process until finishes compressing field. this time asserts enters IDLE state. DATERR enabled interrupt requesting event (i.e., cleared Interrupt Mask register), then ZR36060 samples START again, START asserted process begins. this mode ZR36060 produces only "abbreviated format table specification", that code output contains frame header, scan header, Huffman-coded segments. output includes marker, table marker segment(s), optional and/or marker segments, marker. process activated START (possibly with FRAME), upon completion asserted ZR36060 returns IDLE.
ZR36060 Integrated JPEG Codec
Note VSYNC Active area State IDLE WAIT-ACT (w/error) Wait-ISR (w/error) IDLE EVEN EVEN EVEN EVEN EVEN EVEN
Legend: through IDLE WAIT-ACTIVE
START FRAME RTBSY DATERR (code master) CBUSY (code slave) DATA (CODE bus) JIRQ Notes: field START FRAME asserted indicate begin next VSYNC Wait next field; meanwhile START signal ignored (END asserted) Field compressed, issue return IDLE. this point, START sensed FRAME high, compression starts next VSYNC. Field compressed. Again, after system asserts START FRAME, next field must compressed too. Begin field compression, system slow read data out, DATERR asserted. with DATERR informs system corrupted field. Since interrupt request data error enabled, ZR36060 asserts JIRQ waits until host acknowledges JIRQ reading associated interrupt status register. During this field, host services interrupt (ZR36060 de-asserts JIRQ) asserts START compress next field. this example, host also disables interrupts after servicing this one. Field compressed. After END, host asserts START again. Field compressed normally, during last lines active area, system response slow last part code read much slower rate. Next field (#9) begins (VSYNC asserted) before ZR36060 activates END. This error condition indicated DATERR. JIRQ here since interrupts disabled. START sensed next field (the ZR36060 skips field #9). Fields compressed normally. START de-asserted during field #11, therefore after ZR36060 returns IDLE waits next operation.
Figure Examples ZR36060 Compression (after host loaded parameters Load command)
6.11 Decompression
Before starting decompression ZR36060 IDLE state. After correct initialization been done host (loading parameters and/or tables), ZR36060 ready receive command start decompression. video already outputs background color, ZR36060 code slave, CBUSY asserted, host cannot write compressed data ZR36060. After START activated, ZR36060 starts reading compressed data code master), decoding filling strip buffer with pixels. However, pixels will start flowing video before VSYNC that follows START VSYNC, FRAME asserted together with START). Host controllers that capable synchronizing start command VSYNC providing start command soon possible after VSYNC. This makes sure that once VSYNC arrives, ZR36060 enough pixels strip buffer avoid condition strip buffer underflow. systems where video sync signals controlled host, this
capability used guarantee that START asserted long enough before next VSYNC. Once START asserted, CBUSY deasserted configured output, i.e., code slave mode), RTBSY asserted indicating that strip memory initially (close empty (underflow). host should provide compressed data ZR36060 quickly possible, fill strip memory. Deassertion RTBSY indication that sufficient data available strip buffer start video output. Every time that ZR36060 senses that strip buffer close overflow (full), asserts internal flag that stops transfer pixels into strip buffer, eventually might result assertion CBUSY code slave mode) stopping compressed data acquisition code master mode). When ZR36060 senses marker, when active portion video field over (whichever occurs later), asserts signal returns IDLE state, waiting start command. compression, host controller choose leave START asserted continuously, rather than asserting after every END).
ZR36060 Integrated JPEG Codec
6.11.1 Data corruption during decompression
during decompression field ZR36060 senses data corruption event, immediately asserts DATERR, then continues decompression process until senses (End Image) marker active video area (whichever occurs later). this time asserts enters IDLE state. deassertion (upon START next field) deasserts DATERR signal. DATERR enabled interrupt requesting event (i.e., cleared Interrupt Mask register), then ZR36060 samples START again, START asserted process begins. DATERR enabled interrupt requesting event, JIRQ asserted together with assertion DATERR, when ZR36060 completes current process enters WAITISR state remains there, ignoring START, until host reads Interrupt Status register. this time ZR36060 goes back IDLE again ready start process, waiting START. decompression ZR36060 signals data corruption condition strip buffer underflows.
Note VSYNC Active area State
EVEN
EVEN
EVEN
EVEN
EVEN
EVEN
IDLE
WAIT-ACT
Legend: through IDLE WAIT-ACTIVE
(w/error)
WAIT-ISR
(w/error)
IDLE
START FRAME RTBSY DATERR (code master) CBUSY (code slave) DATA (CODE bus) JIRQ Notes: field START FRAME asserted instruct ZR36060 decompress next VSYNC (field #3). Code input immediately after START asserted, decode fill with lines video first strip buffer before beginning active area. After first strip decompressed, code longer fetched, ZR36060 waits active area next field. Field decompression continues when completed, ZR36060 issues returns IDLE. Field decompressed normally. Begin field decompression, system slow feed data, DATERR asserted. with DATERR informs system corrupted field. Since interrupt request data error enabled, ZR36060 asserts JIRQ waits until host acknowledges JIRQ reading associated interrupt status register. During this field, host services interrupt, ZR36060 de-asserts JIRQ, host asserts START decompress next field. this example, host also disables interrupts after servicing this one. Field decompressed. After END, system asserts START next field. Field ZR36060 starts input code, somewhere during active area, code unavailable long enough that ZR36060 issues DATERR JIRQ here since interrupts disabled). Nevertheless, system continues feed code ZR36060 until which occurs only after VSYNC next field (#9). START sensed meaning that next decompression will happen field (field skipped). Fields decompressed normally. START asserted during field #11, therefore after ZR36060 returns IDLE waits next operation.
Figure Examples ZR36060 Decompression (after host loaded parameters Load command)
ZR36060 Integrated JPEG Codec
POWER MANAGEMENT POWER-UP
ZR36060 power consumption modes: normal mode, low-power mode, SLEEP state, entered activating SLEEP pin. This power saving achieved disabling internal clocking flip-flops gates, this mode regarded "frozen" state ZR36060. outputs retain their states, bidirectional signals retain their directions. Transitions from SLEEP state must done IDLE state. host accesses allowed SLEEP state, during IDLE SLEEP transition. Otherwise ZR36060 must reset again. After SLEEP de-activated, ZR36060 operational again, without need reset, retaining registers, markers parameters previously loaded. note: before START activated again next compression decompression, host must write Load reload parameters tables. Deactivation SLEEP also serves initiate coarse frequency lock phase internal PLL. this reason, mandatory pulse SLEEP least once after power-up, when system clock (VCLKx2) stable (within nominal frequency). coarse lock must re-initiated pulsing SLEEP pin) each time system changes frequency VCLKx2, example video standard changed. Figure coarse frequency lock procedure takes 5000 VCLKx2 cycles, executed every low-to-high transition SLEEP. ZR36060 remains SLEEP state during this time interval.
RESET SLEEP state Power RESET
(SLEEP must inactive) VCLKx2 min)
WAIT VCLKx2 STABILIZE
SLEEP
LOCK
IDLE
(operational)
RESET Period: Minimum pulse width VCLKx2 cycles. WAIT Period: wait VCLKx2 stabilize correct operating frequency. SLEEP Pulse: Minimum pulse width VCLKx2 cycles. LOCK Period: After SLEEP deasserted, system must wait 5,000 VCLKx2 cycles until correctly locked clock frequency. IDLE: ZR36060 ready operation.
Figure Power-Up Sequence SLEEP Operation
ZR36060 Integrated JPEG Codec
REGISTER MEMORY DESCRIPTION
ZR36060 internal memory space implemented 1024 bytes RAM, accessible host controller through host interface. contents this loaded into working storage registers tables using Load command (refer "Loading Parameters Tables"). Figure depicts partitioning RAM. "default" specified each register bit. This value after reset.
Bits Data Host Address Host Data Host Interface 022h 024h 026h 030h 000h General Control Registers Identification Registers Test Control Registers Reserved Video Registers
before starting operation every time parameter written anywhere internal memory space. effect Load parameters
Code FIFO Status Register (Read only)
0x001 type default Busy CBUSY
Address 0x001
CFIFO1 CFIFO0
CFIFO1:0 Indicates fullness Code FIFO: less than full. more less than full. more less than full. full more. These bits valid only when asserted. CBUSY: Indicates full/empty condition code FIFO. Identical state CBUSY pin, with inverse logic. code FIFO full empty code FIFO full empty This valid only when CBUSY output; i.e.- code slave mode. Busy: Status Load operation. host must poll this determine when ZR36060 ready (not Busy) load parameter start compression/decompression process. ZR36060 ready operate, Load operation progress Load progress now, access internal memory location while this
052h 060h
Reserved
JPEG Markers Array
3FFh
Figure Internal Memory
Code Interface Register Address 0x002
CFIS
CodeMstr
General Control Registers
Load Parameters Register
0x000 type default Load
0x002 type default
Code16
Endian
Address 0x000
SyncRst
CodeMstr: Selects Code Master Slave mode. Code Slave mode Code Master mode CFIS: Only Master mode, defines number clocks each code byte transfer. Must Code Slave mode. VCLKx2 cycle VCLKx2 cycles Endian: Defines byte ordering when using 16-bit code slave interface. Must Master mode 8-bit Slave mode. first byte (`FF' `FFD8' code) DATA first byte (`FF' `FFD8' code) CODE Code16: Defines code width slave mode only. Must Master mode. 8-bit code 16-bit code
SyncRst: Resets video sync generator. reset Resets sync generator. Starts horizontal vertical counting from sync generator maintained reset state until host writes this bit. Load: Loads internal memory parameters (including tables) respective internal working stores. After writing Load ZR36060 sets Busy until load complete ZR36060 ready operate. Load must
ZR36060 Integrated JPEG Codec
Codec Mode Register
0x003 type default COMP PASS2
Address 0x003
Interrupt Mask Register
0x007 type default EOAV
Address 0x007
DATERR
11000100 Auto Two-Pass Compression 10000100 Statistical Compression Pass 10100100 Compression Pass with Variable Scale Factor 10100110 Compression Pass with Fixed Scale Factor 10110000 Tables-Only Compression Pass 00000000 Decompression Pass other combinations register bits illegal
DATERR: Enable interrupt assertion DATERR during process Interrupt disabled Interrupt enabled END: Enable interrupt assertion process Interrupt disabled Interrupt enabled EOI: Enable interrupt when asserted, i.e., when marker being read written code interface Interrupt disabled Interrupt enabled EOAV: Enable interrupt End-Of-Active-Video area during process Interrupt disabled Interrupt enabled
Reserved
0x004 type default
Address 0x004
Must programmed 0x00 correct operation.
Interrupt Status Register (Read Only) Maximum Block Code Volume Register
0x005 type default MBCV
Address 0x008
EOAV
DATERR
Address 0x005
0x008 type default
ProCnt1 ProCnt0
MBCV: Maximum Block Code Volume. compression modes, MBCV imposes upper limit number bits that used encode each block samples. number bits twice value coded this register. MBCV=01 represents bits block, MBCV=FF represents bits block.
DATERR: Status DATERR output DATERR asserted (normal operation) DATERR asserted (data corruption) END: Status output asserted (process progress) asserted (process ended IDLE state) EOI: Status output marker event occur marker been read written host EOAV: Latch event upon End-Of-Active-Video area during process EOAV event occur (video still being input output) EOAV event occurred (active area video finished) ProCnt1:0 2-bit cyclic process (compression decompression) counter. incremented START each field process. Note: ProCnt appears here only status, interrupt-generating event.
Markers Enable Register
0x006 type default
Address 0x006
compression, this register specifies which optional marker segments include compressed data. used decompression. programmed respective marker segment included. programmed ZR36060 performs following action: APP: Reads Application segment from Internal Memory writes compressed data during Compression Pass. Also Tables-only pass. COM: Reads Comment segment from Internal Memory writes compressed data during Compression Pass. Also Tables-only pass. DRI: Define Restart Interval. Enables restart mechanism writes marker segment compressed data during Compression Pass. When restart interval zero, restart function disabled. DQT: Define Quantization Tables. Reads base Quantization Tables defined segment Internal Memory, multiplies quantization values Scale Factor (SF), rounds eight bits writes results together with marker parameters compressed data during Compression Pass Tables-Only Pass. number Quantization Tables processed inferred from (segment length) parameter segment. Note: identical scaled tables used compress data. DHT: Define Huffman Tables. Reads Huffman Tables defined segment Internal Memory, writes segment compressed data during Compression Pass Tables-only Pass.
Target Code Volume Register
0x009 0x00A 0x00B 0x00C type default TCV_NET31:24 TCV_NET23:16 TCV_NET15:8 TCV_NET7:0
Address 0x009 0x00C
TCV_NET31:0: Target Code Volume. Must programmed host Compression Pass Auto Two-Pass compression. TCV_NET used ZR36060 calculation Scale Factor (SF) Compression Pass second pass Auto Two-Pass compression. Target Code Volume bits compressed data excluding marker segments.
ZR36060 Integrated JPEG Codec
Target Data Code Volume Register
0x00D 0x00E 0x00F 0x010 type default TCV_DATA31:24 TCV_DATA23:16 TCV_DATA15:8 TCV_DATA7:0
Address 0x00D 0x010
Accumulated Total Activity Register
0x01A 0x01B 0x01C 0x01D type default ACT31:24 ACT23:16 ACT15:8 ACT7:0
Address 0x01A 0x01D
TCV_DATA31:0: Target Data Code Volume. Required ZR36060 only Auto Two-Pass compression Statistical Pass. TCV_DATA used ZR36060 calculate Scale Factor (SF) Allocation Factor (AF) after Statistical Pass. Target Code Volume bits compressed data excluding marker segments, (end-of-block) Huffman codes, byte stuffing, stuffing (which completes last data byte). Note: byte stuffing typically represents about code volume.
ACT31:0: Accumulated Total Activity image, measure used internal rate control calculations. written here ZR36060 Statistical Pass Auto Pass compression modes. 32-bit binary integer.
Accumulated Truncated Bits Register
0x01E 0x01F 0x020 0x021 type default
Address 0x01E 0x021
Scale Factor Register
0x011 0x012 type default
Address 0x011 0x012
SF15:8 (integer part SF7:0 (fractional part
ACV_TRUN31:24 ACV_TRUN23:16 ACV_TRUN15:8 ACV_TRUN7:0
SF15:0: Scale Factor. used scaling quantization table values. should provided ZR36060 parameter beginning every compression operation. Variable option used, this register internally computed updated every compression pass order converge desired TCV. 16-bit fixed point binary number, with bits after binary point.
ACV_TRUN31:0: Total number bits truncated result block truncation, measure used internal rate control calculations Compression Pass Auto Two-Pass modes. ACV_TRUN written here ZR36060 these modes. 32-bit binary integer.
Testing Registers
Identification Registers (Read Only) Address 0x022 0x023
Allocation Factor Register
0x013 0x014 0x015 type default AF23:16 AF15:8 AF7:0
Address 0x013 0x015
0x022 type default 0x023 type default
DeviceID Revision
AF23:0: Allocation Factor. used rate control compute Allocated Code Volume each block. computed ZR36060 written register Statistical Pass. This value later used Compression Pass; otherwise Compression Pass without prior Statistical Pass, must programmed 0xFFFFFF. 24-bit fixed point binary number, with bits after binary point.
DeviceID: Hardwired chip device number (0x33). Revision: Hardwired current chip revision number (0x01).
Test Control Registers
0x024 0x025 type default
Address 0x024 0x025
Accumulated Code Volume Register
0x016 0x017 0x018 0x019 type default ACV31:24 ACV23:16 ACV15:8 ACV7:0
Address 0x016 0x019
Reserved: Reserved test mode. Must initialized 0x00 correct operation.
ACV31:0: Accumulated Code Volume. 32-bit binary integer. written ZR36060, read host compression operation. different interpretations, depending compression operation: ACV_DATA: Code Volume bits excluding marker segments, codes byte stuffing completion Statistical Pass. ACV_NET: Code Volume bits excluding marker segments completion every Compression Pass. ACV_NET number bytes passing through Code FIFO excluding marker segments. does include padding bytes double-word alignment.
ZR36060 Integrated JPEG Codec
Video Registers
Scaling Register Video Control Register
0x030 type default Video8 Range FIDet
FIVedge
Address: 0x032
VScale HScale
Address 0x030
FIExt
SyncMstr
0x032 type default
SyncMstr: Configures ZR36060 video sync Master Slave. Video sync Slave Video sync Master FIExt: Field detection external decoding from HSYNC VSYNC. Even/odd field detection latching HSYNC with VSYNC Even/odd field detection means dedicated FIVedge: Defines start video field leading trailing edge VSYNC (affects reset point vertical counters, signal state change, next field decision after START, DATERR assertion when VSYNC arrives before process). Leading edge VSYNC Trailing edge VSYNC FIDet: Interpretation detected field type (detection controlled FIExt). fields: low, VSYNC latches HSYNC pulse fields: high, VSYNC latches middle line Range: Defines full-scale range video pixels decompression. effect compression. Pixel values full-scale with levels. Pixel values limited range [16,235] (per CCIR 601.) Video8: Defines video width. 16-bit video 8-bit video
HScale: Horizontal down scaling compression decompression) scaling scaling ratio, with horizontal filtering scaling ratio, with horizontal filtering used VScale: Vertical down scaling compression decompression) scaling compression, only even indexed lines (0,2,.) processed. decompression, lines duplicated
Background Color Registers
0x033 0x034 0x035 type default BackY7:0 BackU7:0 BackV7:0
Address: 0x033 0x035
BackX: components background color (used only decompression)
Video Polarity Register
0x031 type default
VCLKPol
Address 0x031
PoePol
SImgPol
PValPol
BLPol
FIPol
HSPol
VSPol
VSPol: Polarity VSYNC signal (note that this parameter completely independent FIVedge parameter) Sync pulse active Sync pulse active high HSPol: Polarity HSYNC signal Sync pulse active Sync pulse active high FIPol: Polarity Field Identification signal during fields high during fields BLPol: Polarity BLANK signal BLANK area active BLANK area active high SImgPol: Polarity SUBIMG signal SUBIMG before SVStart, SHStart after SVEnd, SHEnd SUBIMG high before SVStart, SHStart after SVEnd, SHEnd PoePol: Polarity signal permit floating (disabling) ZR36060 video during decompression: Disable when Disable when high PValPol: Polarity PVALID signal Pixels valid when PVALID Pixels valid when PVALID high VCLKPol: Polarity VCLK signal (relevant 16-bit video width only) Pixels valid when VCLK Pixels valid when VCLK high
ZR36060 Integrated JPEG Codec
Sync Generator Registers
0x036 0x037 0x038 0x039 0x03A 0x03B 0x03C 0x03D 0x03E 0x03F 0x040 0x041 type default Vtotal 15:8 Vtotal Htotal Htotal VsyncSize HsyncSize BVstart BHstart BVend 15:8 BVend BHend BHend
Address: 0x036 0x041
Active Area Registers
0x042 0x043 0x044 0x045 0x046 0x047 0x048 0x049 type default Vstart 15:8 Vstart Vend 15:8 Vend Hstart Hstart Hend Hend
Address: 0x042 0x049
Parameters used internal video sync generator when Master mode (SyncMstr=1). Horizontal measures number VCLKs VCLK pixel, regardless video width), from leading edge HSYNC. Vertical measures number HSYNCs HSYNC line), from leading trailing edge VSYNC specified FIVedge parameter. Vtotal 15:0: Number lines frame. Writing indicates that frame lines. (e.g. Vtotal 524, NTSC, lines frame) Maximum permitted value 65535. Htotal 9:0: Number pixel periods (VCLKs) line. Writing indicates that line VCLKs. (e.g. Htotal 857, NTSC-CCIR, pixels line) Maximum permitted value 1023. VsyncSize 7:0: Length VSYNC pulse measured lines. Writing indicates that sync pulse width lines. (e.g. VsyncSize 6-line vertical sync interval) HsyncSize 7:0: Length HSYNC pulse measured VCLKs (pixels). Writing indicates that sync pulse width pixels. (e.g. HsyncSize 32pixel horizontal sync interval) BVstart 7:0: Length from active VSYNC edge first non-BLANK line measured lines. Writing indicates that first non-BLANK line line N+1. (e.g. BVstart have first non-BLANK line line number BHstart 7:0: Length from HSYNC leading edge first non-BLANK pixel measured pixels (VCLKs). Writing indicates that first non-BLANK pixel pixel number N+1. (e.g. BHstart have first non-BLANK pixel VCLK number 100) BVend 15:0: Length from active VSYNC edge last non-BLANK line measured lines. Writing indicates that last non-BLANK line line (e.g. BVend 241, have last non-BLANK line line number 241) BHend 9:0: Length from HSYNC leading edge last non-BLANK pixel measured pixels (VCLKs). Writing indicates that last non-BLANK pixel pixel number (e.g. BHend 720, have last non-BLANK pixel VCLK number 720)
Parameters that define active area rectangle processed video. Horizontal measures number VCLKs VCLK pixel, regardless video width), from leading edge HSYNC. Vertical measures number HSYNCs HSYNC line), from leading trailing edge VSYNC specified FIVedge parameter. Vstart 15:0: Length from VSYNC edge first active (processed) line measured lines. Writing indicates that first active line line N+1. (e.g. Vstart have first active line line number 12). Vstart must Vend 15:0: Length from VSYNC edge last active (processed) line measured lines. Writing indicates that last line line (e.g. Vend 241, have last line line number 241). Maximum permitted value (Vend Vstart) 32768. Vend must (NTF 10), where total number lines field. (NTF=262 NTSC, PAL) Hstart 9:0: Length from HSYNC leading edge first active (processed) pixel measured pixels. Writing indicates that first active pixel pixel number N+1. (e.g. Hstart have first active pixel VCLK number 100). Hstart must compression, must decompression. Hend 9:0: Length from HSYNC leading edge last active (processed) pixel measured pixels. Writing indicates that last active pixel pixel number (e.g. Hend 720, have last active pixel VCLK number 720). Maximum permitted value (Hend Hstart) 768. Note: active video area must overlap VSYNC pulse. other words, active area must always contained between trailing edge VSYNC next leading edge (see Figure
ZR36060 Integrated JPEG Codec
Sub-image Window Registers
0x04A 0x04B 0x04C 0x04D 0x04E 0x04F 0x050 0x051 type default SVstart 15:8 SVstart SVend 15:8 SVend SHstart SHstart SHend SHend
Address: 0x04A 0x051
APP, COM. SOI, markers supported automatically ZR36060. Before starting compress sequence images, host must program appropriate marker segments internal memory, issue Load command load them. Only markers actually used need programmed: required markers SOS, whichever optional markers specified Markers Enable register. Note that starting location each marker segment internal memory fixed, length content marker segment variable. host does have program marker segments order decompress image bitstream that contains necessary tables. bitstream abbreviated format lacks more tables, host must preload them, programming appropriate tables internal memory, issuing Load command before starting decompress sequence images that uses same tables images.
Parameters that define sub-image rectangle video. Horizontal measures number VCLKs VCLK pixel, regardless video width), from leading edge HSYNC. Vertical measures number HSYNCs HSYNC line), from leading trailing edge VSYNC specified FIVedge parameter. SVstart 15:0: Length from active VSYNC edge first sub-image line measured lines. Writing indicates that first sub-image line line N+1. (e.g. SVstart have first sub-image line line number 12). SVend 15:0: Length from active VSYNC edge last sub-image line measured lines. Writing indicates that last line line (e.g. SVend 241, have last line line number 241). Maximum permitted value (SVend SVstart) 32768. SHstart 9:0: Length from HSYNC leading edge first sub-image pixel measured pixels. Writing indicates that first sub-image pixel pixel number N+1. (e.g. SHstart have first sub-image pixel VCLK number 100). SHend 9:0: Length from HSYNC leading edge last sub-image pixel measured pixels. Writing indicates that last sub-image pixel pixel number (e.g. SHend 720, have last sub-image pixel VCLK number 720). Maximum permitted value (SHend SHstart) 1023.
Table ZR36060 JPEG Marker Segments
Address Content SOF0 SOF0 Value Description Start Frame marker (FFC0). This segment contains bytes that define components (Y,U,V) MCU, quantization table used each component. Length this segment (without marker) Precision bits) Number lines active area (must always equal Vend Vstart)
LEN_H LEN_L HY,VY HU,VU HV,VV
JPEG Marker Segments
Table shows mapping JPEG markers ZR36060 internal memory. Value column contains common values (hexadecimal) used 4:2:2 format images supported ZR36060. There default values, therefore user must pre-load correct values before operating device. compression, SOF0 marker segments always copied from memory into compressed image bitstream header. other marker segments optional, their inclusion bitstream controlled Markers Enable register. decompression, marker segments contained compressed bitstream automatically copied ZR36060 into internal memory appropriate starting locations. decompression, host read them desired. Note that compressed image contains more than marker same type, only last will contained memory process. example, there segments, first defining Huffman tables, second defining Huffman tables, only tables read from memory process. course, tables will used required decompression. marker segments Internal Memory have exactly same syntax marker segments specified JPEG standard. These segments are: SOF, SOS, DRI, DQT, DHT,
073-079
Number pixels active area (must always equal Hend Hstart)
Number Color Components (YUV components) Component Number appearances MCU, horizontally vertically Quantization table Component Number appearances MCU, horizontally vertically Quantization table Component Number appearances MCU, horizontally vertically Quantization table Unused
Start Scan marker (SOS). Specifies Huffman table with each color component.
ZR36060 Integrated JPEG Codec
Table ZR36060 JPEG Marker Segments
Address 088-0BF 0C6-0CB 0D0. RI_H RI_L Typical segment length, with tables LEN_H LEN_L Contents segment Comment marker segment. Limited bytes maximum length including marker compression, this byte programmed instead possible include second segment bitstream instead segment Maximum length bytes Unused Define Quantization Tables. Length this segment (without marker) Length Restart Interval units. Content LEN_H LEN_L TYd,TYa TUd,TUa TVd,TVa Value Description Length this segment (without marker) Number Components this scan Component Huffman table selections Component Component Huffman table selections Component Component Huffman table selections Component Constant Constant Constant Unused Define Restart Interval.
Table ZR36060 JPEG Marker Segments
Address 1D8. Content Value Description Typical segment data AC): Unused Application marker segment. Limited bytes maximum length including marker n=0,.,F Maximum length bytes
Typical segment data tables): Typical segment length, with tables more bytes optional third table, remainder unused Define Huffman Tables.
.3FF
LEN_H LEN_L
Contents segment (End ZR36060 internal memory)
ZR36060 Integrated JPEG Codec
ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
Storage Temperature .-65°C +150°C Supply Voltage (VDD).-0.5 +5.0 Output Voltage -0.5 VDD+0.5 Input Voltage.-0.5 +6.0 Output Current. +-20 mA/output, Max. Input Current.
Note: Stresses above these values cause permanent device failure. Functionality above these limits implied. Exposure absolute maximum ratings extended periods affect device reliability.
OPERATING RANGE
Temperature.0°C +70°C Supply Voltage
CHARACTERISTICS
Table Input Characteristics
Symbol
Parameter Input Voltage Input Voltage High Input leakage current Input Capacitance Power Supply Current Stand-by (SLEEP) current
-0.3
Unit
Test Conditions
ZR36060-27 VCLKx2 ZR36060-29.5 29.5 VCLKx2
Table Output Characteristics
Symbol COUT Parameter Output Voltage Output Voltage High Output Leakage Current Output Capacitance Unit Test Conditions
ZR36060 Integrated JPEG Codec
TIMING CHARACTERISTICS
Unless otherwise specified, timing characteristics apply both ZR36060-27 ZR36060-29.5.
Table Video Input Timing
Symbol FVCLKx2 Parameter VCLKx2 Frequency 22.2 22.2 33.8 37.0 27.0 29.5 Unit Comments ZR36060-27 ZR36060-29.5 duty cycle ZR36060-27 ZR36060-29.5 multiplies VCLKx2 frequency tCLK used reference variable other timing parameters.
tV2P tCLK
VCLKx2 Period Internal Clock Period
tV2P tCLK
tV2T tVIS tVIH
VCLKx2 Rise/Fall Transition VCLK Rise/Fall Transition Video Input Setup Video Input Hold
tV2P VCLKx2
tV2T
tV2T
tVIS VCLK
tVIH
tVIS INPUTS
tVIH
Note: this diagram VCLKPol 16-bit interface mode inputs sampled VCLKx2 rising edges qualified VCLK. 8-bit interface mode inputs sampled VCLKx2 rising edges.
Figure Video Input Timing
Table Video Output Timing
Symbol tVBO tVBO8 Parameter Video Output Delay (16-bit) Video Output Delay (8-bit) tCLK 0.5tCLK tCLK 0.5tCLK Unit 50pf load 50pf load Comments
tCLK VCLKx2
VCLK
tVBO Video Output (16-bit) tVBO8 Video Output (8-bit) tVBO8
tVBO
Figure Video Output Timing
ZR36060 Integrated JPEG Codec
Table Host Interface Timing
Symbol tCAS tCAH tWDUR tWACK tRDUR tRACK tOPD tREC Parameter ADDR1:0 setup falling edge ADDR1:0 hold from rising edge Minimum strobe pulse width assertion (low) Input Data Setup rising edge Input Data Hold from rising edge Minimum strobe pulse width assertion (low) output data valid Output Data Hold, rising edge data float rising edge next falling edge rising edge rising edge tCLK tCLK tCLK tCLK tCLK tCLK tCLK tCLK tCLK tCLK Unit load load load Comment
tCAS
tCAH
tCAS
tCAH
ADDR1:0
tWDUR
tREC
tRDUR
tWACK
tRACK
DATA7:0 Host Data Valid
tOPD ZR36060 Data Valid
Figure Host Interface Timing
ZR36060 Integrated JPEG Codec
Table Code Slave Interface Timing
Symbol tCAS tCAH tDUR tACK tOPD tREC Parameter ADDR1:0 setup falling edge ADDR1:0 hold from rising edge Minimum strobe pulse width 8-bit mode: 16-bit mode: assertion (low) Input Data Setup rising edge Input Data Hold from rising edge output data valid Output Data Hold rising edge data float rising edge next falling edge rising edge rising edge CBUSY falling edge falling edge tCLK tCLK tCLK tCLK tCLK tCLK tCLK tCLK Unit load load load Comment
tCAS
tCAH
tCAS
tCAH
ADDR1:0
tDUR
tREC
tDUR
tACK
tACK
DATA7:0 CODE7:0 Host Data Valid
tOPD ZR36060 Data Valid
CBUSY
Figure Code Slave Interface Timing
ZR36060 Integrated JPEG Codec
Table Code Master Interface Timing Compression
Symbol tCPD tSPD tDPD tBSU Parameter Propagation Delay Propagation Delay Hold Delay Code Data Propagation Delay Code Data Turn-on Delay (Float Drive) Code Data Hold Delay (Drive Float) CBUSY Setup CBUSY Hold tCLK tCLK tCLK tCLK Unit
Comment
These signals triggered edge internal clock that falls half between positive edges VCLKx2. Thus delay times relative VCLKx2 specified terms tCLK, period clock. termination CODE cycle, when cycle does start immediately, ZR36060 stops driving CODE floats. this case, data hold time determined decay time capacitance pullup resistors connected
VCLKx2
tCPD
tCPD
tCPD
tSPD
tBSU CBUSY tDPD CODE7:0 (Output)
tDPD Byte Byte Byte
Figure Code Master Interface Timing Compression
ZR36060 Integrated JPEG Codec
Table Code Master Interface Timing Decompression
Symbol tCPD tSPD tDSU tBSU Parameter Propagation Delay Propagation Delay Hold Delay Code Data Input Setup Code Data Input Hold CBUSY Setup CBUSY Hold tCLK tCLK+7 Unit
Comment
This signal triggered edge internal clock that falls half between positive edges VCLKx2. Thus delay time relative VCLKx2 specified terms tCLK, period clock.
VCLKx2
tCPD
tCPD
tCPD
tSPD tBSU CBUSY
tSPD
tDSU CODE7:0 (Input) Byte
tDSU Byte
Figure Code Master Interface Timing Decompression
ZR36060 Integrated JPEG Codec
10.0 PINOUT
Table 100-Pin Quad Flat Pack Assignment
Name Type Name NC[2] NC[2] HSYNC VSYNC BLANK PVALID SUBIMG SLEEP VCLKX2 VDDPLL VCLK Type[1] Name CODE7 CODE6 CODE5 CODE4 CODE3 CODE2 CODE1 CODE0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 Type[1] Name DATA0 NC[2] COMP CBUSY RESET ADDR1 ADDR0 DATERR RTBSY JIRQ START FRAME Type[1]
P=power, I=input, O=output. Must left unconnected. VDDPLL must connected VDD. minimize clock jitter, following power supply decoupling recommended: microfarad capacitor close possible each pin. microfarad 0.001 microfarad capacitor VDDPLL pin. microfarad larger) tantalum electrolytic power plane. This output clock doubler. must left unconnected.
ZR36060 Integrated JPEG Codec
index mark, notched corner, both
FRAME START JIRQ RTBSY DATERR ADDR0 ADDR1 RESET CBUSY COMP
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 CODE0 CODE1 CODE2 CODE3 CODE4 CODE5 CODE6 CODE7
ZR36060
(TOP VIEW)
HSYNC VSYNC BLANK PVALID SUBIMG SLEEP VCLKX2 VDDPLL VCLK
ZR36060 Integrated JPEG Codec
11.0 MECHANICAL DATA
Package Outline Drawing ZORAN lead Metric
(.941 ±0.016) 23.90 ±0.40
(.787 ±0.008) 20.00 ±0.20
VIEW
(.012 ±0.004) ±0.10
(.0256 basic) basic
(.551 ±0.008) 14.00 ±0.20
(.007 +.0016/-.003) +.04/-.08
Seating Plane (.010 +.010/-.006) +.25/-.15 (.035 ±0.008) ±0.20 (.705 ±0.016) 17.90 ±0.40
(.004)
(.134 max) 3.40
NOTE: Principal dimensions millimeters, dimensions brackets inches.
ZR36060 Integrated JPEG Codec
ORDERING INFORMATION
36060
PACKAGE Plastic Quad Flat Pack (EIAJ) CLOCK FREQUENCY SCREENING PACKAGE PART NUMBER PREFIX CLOCK FREQUENCY VCLKx2 Frequency 29.5 VCLKx2 Frequency 29.5 SCREENING +70°C
(VCC 4.75V 5.25V)
SALES OFFICES
U.S. Headquarters Zoran Corporation 3112 Scott Blvd. Santa Clara, 95054 Telephone: 408-919-4111 FAX: 408-919-4122 Israel Design Center Zoran Microelectronics, Ltd. Advanced Technology Center 2495 Haifa, 31024 Israel Telephone: 972-4-854-5777 FAX: 972-4-855-1550 Japan Office Zoran Japan 2-26-2 Sasazuka Shibuya-ku, Tokyo Japan Telephone: 03-5352-0971 FAX: 03-5352-0972
material this data sheet information only. Zoran Corporation assumes responsibility errors omissions reserves right change, without notice, product specifications, operating characteristics, packaging, etc. Zoran
Corporation assumes liability damage resulting from information contained this document.
DS36060R4-0198
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