L64105 integrated, low-cost source audio/video (A/V) decoder MPEG-2 de

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

L64105 integrated, low-cost source audio/video (A/V) decoder MPEG-2 de

Datasheet Thumbnail

Top Searches for this datasheet

L64105 MPEG-2 Audio/Video Decoder
L64105 integrated, low-cost source audio/video (A/V) decoder MPEG-2 decoding systems. system block diagram Figure shows application L64105 within MPEG-2 system. Figure L64105 MPEG-2 Decoder System Block Diagram
Optional SDRAM
SmartCards
Port
IEEE1284 Line Driver
RS232 Line Driver
Clock
DRAM
SDRAM
Satellite Cable Input Tuner
L64724/L64768 QPSK/QAM Receiver
L64X08 Internal MPEG-2 Transport ACLK Demultiplexer
L64105 MPEG-2 Decoder
L64X08 Ext.
Receiver
Flash
NTSC/PAL S-Video
PAL/NTSC Encoder
Video
Audio
Audio
Audio
MD97.275
April 1999
Copyright 1995-1997 Logic Corporation. rights reserved.
L64105's versatility allows used variety applications including digital set-top boxes, PC-based MPEG-2 applications. ease enables system manufacturers design next generation's systems today. L64105 builds upon Logic's proven MPEG-2 decoder, L64005, with features enhance performance with true video letterboxing while maintaining host processor overhead requirements system cost. L64105 receives coded inputs produces decoded outputs. L64105 input/output interfaces optimized low-cost integration into MPEG-2 system (stand-alone PC-based) set-top box. Logic's digital video architecture L64105 incorporates many unique features capabilities. These architectural elements include flexible preparsing system streams packetized elementary streams (PES), processing sequence layer, flexible display controller. television format supported with minimum memory requirement using less than 2.75 frame stores. This feature allows fullscreen graphic overlay while decoding video. L64105 available 160-pin plastic quad flat package (PQFP), keeping with other members Logic's MPEG-2 decoder family. manufactured using 0.35-micron 3.3-V CMOS process.
Features Benefits
Video Decoding
Integrated studio quality MPEG-2 video decoder Fully complies with Main Profile Main Level MPEG-2 standard,
13818-2
Decodes MPEG-2 bitstream, including MPEG-2 program streams
(PS)
Decodes MPEG-1 bitstream defined 11172, including
MPEG-1 system layer
Operates image sizes CCIR601 resolution pixels
NTSC
MPEG-2 Audio/Video Decoder
Audio Decoding
Combines MPEG audio decoding with support Linear data Decodes dual channel MPEG audio, Layer 11172-3 supporting rates 8-448 Kbps sampling rates 22.05, 44.1,
Allows input samples host interface
Video Display Graphics Support
Integrates flexible 256-color, on-screen display (OSD) controller Allows connection external generator Programmable display management Programmable channel buffer display buffer size Slave video timing operation Supports trick modes commonly needed MPEG-2 systems, such
fast forward, fast reverse, freeze frame, slow motion
Integrates postprocessing filters image resizing (horizontal vertical)
Integrates vertical filter letterbox format display Implements pull-down directly from bitstream hardware Supports software control pull-down Supports horizontal scan with pixel accuracy Supports vertical scan lines resolution Supports 4:2:0 4:2:2 sampling filters 16-level alpha blending
Data Error Handling Capabilities
20-Mbits/s sustained input channel data rate mode 40-Mbits/s sustained input channel data rate transport systems
Input data format: 8-bit parallel through dedicated channel interface Output: 8-bit slave mode Complete on-chip channel buffer display buffer controls
MPEG-2 Audio/Video Decoder
Error concealment maintains display images during channel errors
while avoiding ripping tearing effects
Mute error concealment audio decoder external microcode external logic required
Cost-Effective System Implementation
Programmable preparser accepting PES, elementary streams (ES),
Direct connection 16-Mbit SDRAMs Input/output interfaces optimized glueless integration into consumer video systems
Operates from single 27-MHz clock, with additional audio sample
clock input
Total external memory required audio video decoding:
16-Mbit SDRAM CCIR601 resolution
8-bit host interface allows connection Intel Motorola-style host
initialization, testing, status monitoring
Direct interface off-the-shelf NTSC/PAL encoders Direct interface off-the-shelf audio DACs 160-pin PQFP package power 3.3-V process TTL-compatible pins
MPEG-2 Audio/Video Decoder
Functional Description
Figure provides block diagram L64105's major functional units. overview major functions L64105 follows diagram. Figure L64105 Block Diagram
Audio Decoder SYSCLK ACLK Host Interface Interrupt Interrupt Generator Control Host Data FIFO Video Decoder Display Control MPEG-2 Video Decoder MPEG-2 Serial Output ACLK 1/300 Clock Divider Counter Stereo Audio
Address
Filters Baseband NTSC/PAL Video Encoder
OSD/Graphics MPEG-2 Program Stream Strobe Data Data Request Channel Interface
Display Controller
Data Timing
Programmable Preparser
SDRAM Interface
Data
Address
Control
L64105
SDRAM
Optional SDRAM
MD97.276
MPEG-2 Audio/Video Decoder
Video Audio Decoding
L64105 decode separate video audio ESs, (from transport decoders), containing both audio video streams. addition, decoding parse critical headers presentation time stamp (PTS) decoding time stamp (DTS) information needed video audio synchronization. Video Decoding This section includes description major components involved handling decoding video. Topics include:
Video Decoder Video Postprocessing Filters Letterbox Display On-Screen (OSD) Display Controller with Graphics Support
Video Decoder L64105 operates optimally image sizes pixels, with frame rate NTSC PAL). These resolutions sometimes referred Main Profile Main Level MPEG-2. Therefore, L64105 also decode MPEG-1 sequences. coded data channel have sustained rate Mbit/s. L64105 also supports images with resolution lower than pixels described next paragraph). Video Postprocessing Filters Letterbox Display Images with resolutions below pixels interpolated full size using on-chip filters. This allows programming produced different resolutions decoded displayed televisions with standard NTSC timing, allows digital analog NTSC encoders operating standard television frequencies (typically MHz). addition, filters provide capability scan MPEG image 1/8-pixel accuracy. L64105 also supports 16:9 letterboxing with integrated vertical filter decimation (720 images decimated pixels).
MPEG-2 Audio/Video Decoder
On-Screen (OSD) Display Controller with Graphics Support L64105 integrates controller capable overlaying image pixels (720 PAL) bits/pixel MPEG video sequence while decoding. Audio Decoding L64105 integrates MPEG (MUSICAM) audio decoder with support Linear audio passthru. decode channels MPEG audio Layer Layer over full range compliant rates sample rates. audio decoder uses same memory video decoder channel buffers, which eliminates need extra memory found other nonintegrated audio solutions.
External Interfacing
L64105 includes following external interfaces:
Host Interface Channel Interface Memory Interface Video Output Audio Output
Host Interface stand-alone, dedicated host interface allows user program variety options monitor L64105 operation. addition, user data present data channel errors flagged L64105 read through this port. device does maintain unread user data indefinitely. host interface includes FIFO which more data written once FIFO becomes full. Subsequent data will lost. system controller must read data transmitted user data records MPEG bitstream, even that data subsequently used control some aspect video display subsystem. controller must read this data, then write L64105 internal state registers, necessary. host interface also allows user read data from write data memory channel buffer access.
MPEG-2 Audio/Video Decoder
Channel Interface L64105 includes independent parallel interface direct connection upstream error correction devices. interface uses simple signal handshaking compressed stream transfer decoder. L64105's channel interface handles incoming coded data, which assumed MPEG-2 compliant bitstream, provides error detection reporting. channel interface detects data bitstream that does meet MPEG-2 syntax grammar rules flag data exception processing. Hardware error handling includes error masking application concealment vectors video. Audio error concealment includes muting errors searching error-free frames. channel interface flags gross errors bitstream that channel buffer overrun underrun nonconformance bitstream. error flagging performed errors masked display audio output. external microcontroller programmed with error recovery mechanism handle catastrophic errors. Memory Interface L64105 supports direct connection commercial SDRAM frame stores, channel buffers, overlay memory. L64105 uses frame stores intermediate frame reconstruction display, separate video audio channel buffers rate matching, zero more regions graphic overlays. This storage combined into single, contiguous memory space accessed over 16-bit wide bus. most cases, this 16-bit SDRAM, total memory space Mbytes. second 16-bit SDRAM optional. interface between L64105 SDRAM requires external components. L64105 pinout allows connection SDRAM single layer. During normal operation, L64105 exclusively controls SDRAM frame stores. However, possible access SDRAM through host port L64105 test, verification, access overlay stores channel information.
MPEG-2 Audio/Video Decoder
Video Output L64105 provides digitized video output subsequent display. This data CCIR601 color space. video output operates with luminance sample rate that always exactly half device clock, nominally 13.5 from 27-MHz input clock. L64105 accept external synchronization signals slave mode. L64105 supports number trick modes specific needs MPEG-2 systems, including fast forward, fast reverse, freeze frame, slow motion. Audio Output audio decoder produces serial output that compatible with commonly available commercial audio DACs. audio decoder includes circuitry maintain correct audio output sample rate based upon external audio clock. decoder also provides audio oversampling output clock external audio DAC; this audio output clock selected from audio clock inputs.
MPEG-2 Audio/Video Decoder
Signal Descriptions
This section provides detailed information L64105 signals. Figure shows interfaces L64105. signal name with "_N" appended means active-LOW. Otherwise, active-HIGH. Figure L64105 Interfaces
WAIT_N DTACK_N A[8:0] D[7:0] Host Interface AS_N CS_N READ INTR_N BUSMODE DS_N DREQ_N BCLK LRCLK ASDATA ACLK_441 ACLK_48 ACLK_32 A_ACLK AUDIO_SYNC PREQ_N Audio Interface SBD[15:0] SBA[11:0] SCAS_N SWE_N SRAS_N SCLK SCS_N SCS1_N SDQM Memory Interface
Channel Interface
CH_DATA[7:0] REQ_N AREQ_N VVALID_N VAVALID_N ERROR_N
L64105 MPEG-2 Decoder
Test Interface
ZTEST SYSCLK RESET_N SCAN_TE TM[1:0]
Miscellaneous
PLLVDD PLLVSS
BLANK PD[7:0] Video Output OSD_ACTIVE Interface CREF EXT_OSD[3:0]
MPEG-2 Audio/Video Decoder
Host Interface
A[8:0] Address Input This 9-bit address line provides access L64105's internal registers. address value these lines latched falling edge AS_N (Motorola mode) falling edge READ_N/WRITE_N (Intel mode). Address Strobe (Motorola Mode only) Input falling edge signal, AS_N latches L64105 address currently A[8:0] bus. AS_N also indicates start cycle transaction. AS_N CS_N indicate start transaction. rising edge AS_N indicates transaction. Controller Select Input This signal specifies whether host Intel Motorola-style microprocessor. When HIGH, Motorola mode selected. When LOW, Intel mode selected. Motorola processor uses specify read write transfers. Intel processor uses separate pins specify read write transfers. Please DS_N signal definition below. Chip Select (Motorola Intel Mode) Input This active-LOW signal indicates attempt external host access L64105 either read write cycle. event CS_N AS_N indicates start transaction Motorola mode. CS_N READ_N WRITE_N indicates start cycle Intel mode. actual transaction type (either read write) determined READ polarity (Motorola type interface) READ_N WRITE_N polarity (Intel type interface). cycle determined rising edge AS_N (Motorola mode) rising edge READ_N WRITE_N (Intel mode). CS_N stay active more than transaction cycle.
AS_N
BUSMODE
CS_N
MPEG-2 Audio/Video Decoder
D[7:0]
Host Data Bidirectional This host data 8-bit bidirectional data line used data communication between host L64105. During read cycle, D[7:0] carries valid information from internal L64105 register. DTACK WAIT_N indicates when data host data valid. rising edge WRITE_N (Intel) DS_N (Motorola) indicates L64105 when strobe data into chip. Transfer Request Output This signal active-LOW output that indicates when decoder ready receive byte data. decoder considered ready when interface ready internal write FIFO full, internal read FIFO empty. these conditions met, DREQ_N asserted. maximum transfer rate over this interface Mbit/s. Data Acknowledge (Motorola Mode) 3-State Output RDY_N (Intel Mode) This signal active when used DTACK_N (Motorola mode). When used RDY_N (Intel mode), this signal active LOW. When used DTACK_N, L64105 drives this signal indicate external host that current transaction completed. signal 3-stated CS_N active. L64105 drives DTACK_N HIGH when ready cycle, drives DTACK_N when ready cycle. When used RDY_N, L64105 drives this signal indicate external host that L64105 ready complete current transaction. L64105 drives RDY_N HIGH when L64105 ready. signal 3-stated CS_N active.
DREQ_N
DTACK_N RDY_N
INTR_N
Interrupt Output This signal open drain, active-LOW interrupt output. L64105's host interface drives this signal send interrupt host CPU.
MPEG-2 Audio/Video Decoder
DS_N WRITE_N
Data Strobe (Motorola Mode) Input Write_N (Intel Mode) DS_N (Motorola mode) indicates when strobes data L64105. During read cycle, start read transaction triggered when DS_N, CS_N, AS_N LOW. During write cycle, rising edge DS_N indicates when L64105 latches data present D[7:0]. When WRITE_N (Intel mode) indicates that external host performing write cycle. READ/READ_N must HIGH during write cycle. CS_N indicates that host attempting write L64105's internal registers. address registered falling edge READ_N. rising edge WRITE_N, L64105 latches data present D[7:0].
READ READ_N
Read/Write Strobe (Motorola Mode) Input READ_N (Intel Mode) READ (Motorola mode) indicates whether current cycle read write. When READ HIGH, read cycle progress. When READ LOW, write cycle progress. CS_N must access L64105. READ_N (Intel mode) when external performing read cycle. WRITE_N must HIGH during read cycle. When both CS_N READ_N LOW, host reading from L64105's internal registers. address registered falling edge READ_N.
WAIT_N
Device Wait (Motorola Mode) 3-State Output (Intel Mode) This signal 3-state active when used WAIT_N signal. used interface processors other than Motorola Intel-style host CPUs. signal's function similar DTACK_N/RDY_N (described above); however, polarity inverted. L64105 drives this signal HIGH indicate external host that current transaction completed. signal 3-stated CS_N active. L64105 drives signal when ready cycle, drives signal HIGH when ready cycle.
MPEG-2 Audio/Video Decoder
Channel Interface
AREQ_N Audio Transfer Request Output When L64105 asserts this signal LOW, indicates that L64105 ready receive byte coded audio data system data system mode). L64105 considered ready when both interface ready there room audio channel buffer. this true, then AREQ_N asserted. maximum transfer rate over this interface Mbit/s. Audio Data Valid Input rising edge VAVALID_N writes next byte audio data data that present CH[7:0] pins. VAVALID_N used with data clock synchronous input L64105's channel interface.
VAVALID_N
CH_DATA[7:0] Channel Data Input CH_DATA[7:0] input that serves parallel path incoming channel data. Channel Data Clock Input free-running clock from external channel. Together, VALID_N signals write data synchronously L64105 channel input. Error Input ERROR_N active-LOW input signal. external channel device asserts this signal indicate that channel data contains error. ERROR_N signal latched with data rising edge VAVALID_N VVALID_N. ERROR_N indicates uncorrectable errors channel, invokes error handling L64105. ERROR_N used transfers. Video Transfer Request Output This signal active-LOW output. L64105 asserts REQ_N when ready receive byte coded video data. L64105 ready when both interface ready there room video channel buffer. these conditions true, REQ_N asserted. maximum transfer rate over this interface Mbit/s.
ERROR_N
REQ_N
MPEG-2 Audio/Video Decoder
VVALID_N
Video Data Valid Input rising edge VVALID_N writes into channel buffer next byte video data that present CH[7:0] data bus. VVALID_N used system modes. VVALID_N used together with data clock synchronous input L64105 channel.
Memory Interface
SBA[11:0] SDRAM Address Output This 12-bit output address specifies row/column address connects directly external SDRAM memory. L64105 uses external SDRAM memory picture reconstruction channel buffering. SDRAM Data Bidirectional This 16-bit bidirectional data connects directly external 16-bit SDRAM memory. L64105 uses external SDRAM memory picture reconstruction channel buffering. SDRAM Column Address Select Output This active-LOW signal that drives attached SDRAM. SDRAM 81-MHz Clock Bidirectional This 81-MHz clock signal drives attached SDRAM. Chip Select SDRAM Output SCS_N active-LOW signal that selects lowaddress bank SDRAM, which used first Mbits memory. Chip Select Second SDRAM Output SCS1_N active-LOW signal that selects highaddress bank SDRAM. This signal used systems that have more than Mbits DRAM. SDRAM Control Output SDQM active-HIGH output signal SDRAM data control mask.
SBD[15:0]
SCAS_N
SCLK
SCS_N
SCS1_N
SDQM
MPEG-2 Audio/Video Decoder
SRAS_N
SDRAM Address Select Output This active-LOW signal that drives attached SDRAM. SDRAM Write Enable Output This active-LOW signal that drives external SDRAM. L64105 asserts this signal enable SDRAM write operation.
SWE_N
Video Output Interface
BLANK Blank Output BLANK composite blank output from L64105 display controller. polarity active-HIGH. Display Controller Output Output This display controller output signal serves Chroma reference. CREF HIGH during component Chroma.
CREF
EXT_OSD[3:0] Palette Selection Input This four-bit input selects from colors on-chip color palette external function. EXT_OSD[3:0] data sampled SYSCLK/4 6.75 MHz, providing with resolution pixels. Horizontal Sync Input horizontal sync signal, which resets horizontal counters display controller. horizontal sync signal must synchronous SYSCLK.
OSD_ACTIVE On-Screen Display Output This active-HIGH signal that indicates on-chip active. This indicates which pixels have mixed pixel port. Active output occurs pixel containing mixed data. PD[7:0] Pixel Data Output Output data PD[7:0] represents pixel data reconstructed picture. pixel data formatted CCIR601 chromaticity. Vertical Sync Odd-Even Field Input host program L64105 that either conventional Vertical Sync input odd-even field indicator. When odd-even field indicator mode,
MPEG-2 Audio/Video Decoder
internal display controller counters reset each time changes state beginning each field). parity field controlled timing relative odd-even field indicator should synchronous SYSCLK.
Audio Interface
A_ACLK Audio Clock Output A_ACLK audio output clock that selected from audio input clocks (ACLK_32, ACLK_441, ACLK_48). Audio Clock (32) Input This audio clock where equals 768, 512, 384, 256. Audio Clock (48) Input This audio clock where equals 768, 512, 384, 256. Audio Clock (44.1) Input This audio clock 44.1 where equals 768, 512, 384, 256. Audio Serial Data Line Output ASDATA output serial audio data. host program format either output mode.
ACLK_32
ACLK_48
ACLK_441
ASDATA
AUDIO_SYNC Audio Synchronization Output This signal provides audio sync indication transport systems that require hardware sync controls. BCLK Serial Clock Output This signal clocks ASDATA into BCLK's rising edge. BCLK programmable frequency that host during initialization. Serial Left-Right Clock Output This output clock, which programmable frequency, indicates which samples belong left right stereo channels. FIFO Request Output This signal provides request external controller indicating that file full.
LRCLK
PREQ_N
MPEG-2 Audio/Video Decoder
Miscellaneous Test Interfaces
PLLVDD PLLVSS RESET_N Power Supply Phase-locked loop dedicated power input pin. Ground Phase-locked loop dedicated ground input pin. Input Input
Reset Input This active-LOW input signal. When external source asserts RESET_N, L64105 resets itself. minimum RESET pulse width eight cycles SYSCLK. SYSCLK must running during reset. Scan Test Enable Input When asserted, this signal enables scan test mode. This mode used only during manufacturing test. During normal system operation, this LOW. Device Clock Input SYSCLK L64105's input system clock. clock nominal frequency MHz. Picture reconstruction video timing referenced with respect this clock. Test Mode Input Logic uses these pins during manufacturing test. They intended other purpose. both pins during normal system operation. Test Mode Input This signal used only manufacturing test. During normal system operation, this HIGH through resistor. value recommended.
SCAN_TE
SYSCLK
TM[1:0]
ZTEST
MPEG-2 Audio/Video Decoder
Specifications
This section contains electrical parameters L64105 MPEG-2 Decoder. Table lists absolute maximum ratings. Exceeding these values cause damage L64105. Table defines recommended operating supply voltage temperature. Table shows capacitance. Table lists characteristics
MPEG-2 Audio/Video Decoder
Table Absolute Maximum Ratings
Symbol TSTGP Parameter Supply Compatible Input Voltage Input Current Storage Temperature Range (PQFP Package) Limits1 -0.3 +3.9 -1.0 +6.5 +125 Units
Referenced VSS.
Table Recommended Operating Conditions
Symbol Parameter Supply Ambient Temperature Limits +3.14 +3.46 Units
Table Capacitance
Symbol COUT Parameter1 Input Capacitance Output Capacitance Units
Measurement conditions (VIN tolerant buffers), clock frequency MHz.
MPEG-2 Audio/Video Decoder
Table Characteristics
Symbol Parameter Voltage Input CMOS Voltage Input High CMOS Compatible Voltage Output 4-mA Output Buffers 8-mA Output Buffers Voltage Output High 4-mA Output Buffers 8-mA Output Buffers Current Input Leakage2 with Pull-down with Pull-up Current 3-State Output Leakage Quiescent Supply Current Dynamic Supply Current -4.0 -8.0 VOUT Condition1 Units
0.7VDD -214
-115
0.2VDD
Specified equals ambient temperature over specified range. CMOS inputs.
MPEG-2 Audio/Video Decoder
Pinout
this section, Figure shows L64105 pinout diagram Table provides list. Figure L64105 Pinout Diagram
PLLVSS PLLVDD SDQM SWE_N SCAS_N SRAS_N SCS_N SCS1_N SBA_11 SBA_10 SBA_0 SBA_1 SBA_2 SBA_3 SBA_4 SBA_5 SBA_6 SBA_7 SBA_8 SBA_9 SCLK SBD_8 SBD_9 SBD_10 SBD_11 SBD_12 SBD_13
SBD_7 SBD_6 SBD_5 SBD_4 SBD_3 SBD_2 SBD_1 SBD_0 CH_DATA_0 CH_DATA_1 CH_DATA_2 CH_DATA_3 CH_DATA_4 CH_DATA_5 CH_DATA_6 CH_DATA_7 ERROR_N VAVALID_N VVALID_N REQ_N AREQ_N
View
SBD_14 SBD_15 PREQ_N SCAN_TE ZTEST AUDIO_SYNC ASDATA LRCLK BCLK A_ACLK ACLK_32 ACLK_48 ACLK_441 EXT_OSD_3 EXT_OSD_2 EXT_OSD_1 EXT_OSD_0 CREF BLANK PD_7 PD_6 PD_5
pins connected.
SYSCLK RESET_N DREQ_N INTR_N BUSMODE DTACK_N READ DS_N WAIT_N AS_N CS_N OSD_ACTIVE PD_0 PD_1 PD_2 PD_3 PD_4
MPEG-2 Audio/Video Decoder
Table
Signal
L64105 List
Signal
DTACK_N ERROR_N EXT_OSD_0 EXT_OSD_1 EXT_OSD_2 EXT_OSD_3 INTR_N LRCLK
Signal
PREQ_N READ REQ_N RESET_N SBA_0 SBA_1 SBA_2 SBA_3 SBA_4 SBA_5 SBA_6 SBA_7 SBA_8 SBA_9 SBA_10 SBA_11 SBD_0 SBD_1 SBD_2 SBD_3 SBD_4 SBD_5 SBD_6 SBD_7 SBD_8 SBD_9 SBD_10 SBD_11 SBD_12 SBD_13 SBD_14 SBD_15 SCAN_TE SCAS_N SCLK SCS_N SCS1_N SDQM SRAS_N SWE_N SYSCLK
Signal
VAVALID_N VVALID_N WAIT_N ZTEST
A_ACLK ACLK_32 ACLK_48 ACLK_441 AREQ_N AS_N ASDATA AUDIO_SYNC BCLK BLANK BUSMODE CH_DATA_0 CH_DATA_1 CH_DATA_2 CH_DATA_3 CH_DATA_4 CH_DATA_5 CH_DATA_6 CH_DATA_7 CREF CS_N DREQ_N DS_N
OSD_ACTIVE PD_0 PD_1 PD_2 PD_3 PD_4 PD_5 PD_6 PD_7 PLLVDD PLLVSS
pins connected.
MPEG-2 Audio/Video Decoder
Packaging
L64105 available 160-lead Plastic Quad Flat Package (PQFP). Figure provides mechanical drawings this package. Figure L64105 160-Lead PQFP Mechanical Drawing (Sheet
board layout manufacturing, obtain engineering drawings from your Logic marketing representative requesting outline drawing
MD96.PZ
MPEG-2 Audio/Video Decoder
Figure (Cont.) L64105 160-Lead PQFP Mechanical Drawing (Sheet
MD96.PZ
MPEG-2 Audio/Video Decoder
Ordering Information
Table provides ordering information L64105. Table L64105 Ordering Information
Clock Frequency
Order Number L64105QC-27
Package Type 160-lead PQFP
Operating Range Commercial
MPEG-2 Audio/Video Decoder
Notes
MPEG-2 Audio/Video Decoder
Notes
MPEG-2 Audio/Video Decoder
Sales Offices Design Resource Centers
Logic Corporation Corporate Headquarters Tel: 408.433.8000 Fax: 408.433.8989 NORTH AMERICA
Jersey Edison Tel: 908.549.4500 Fax: 908.549.4802 York York Tel: 716.223.8820 Fax: 716.223.8822 North Carolina Raleigh Tel: 919.783.8833 Fax: 919.783.8909 Oregon Beaverton Tel: 503.645.0589 Fax: 503.645.6612 Texas Austin Tel: 512.388.7294 Fax: 512.388.4171
Denmark Logic Development Centre Ballerup Tel: 45.44.86.55.55 Fax: 45.44.86.55.56 France Logic S.A. Paris Tel: 33.1.34.63.13.13 Fax: 33.1.34.63.13.19 Germany Logic GmbH Munich Tel: 49.89.4.58.33.0 Fax: 49.89.4.58.33.108 Stuttgart Tel: 49.711.13.96.90 Fax: 49.711.86.61.428 Hong Kong Industrial Hong Kong Tel: 852.2428.0008 Fax: 852.2401.2105 India LogiCAD India Private Bangalore Tel: 91.80.526.2500 Fax: 91.80.338.6591 Israel Logic Ramat Hasharon Tel: 972.3.5.403741 Fax: 972.3.5.403747 Netanya
Korea Logic Corporation Korea Seoul Tel: 82.2.561.2921 Fax: 82.2.554.9327 Singapore Logic Singapore Tel: 65.334.9061 Fax: 65.334.4749 Spain Logic S.A. Madrid Tel: 34.1.3672200 Fax: 34.1.3673151 Sweden Logic Stockholm Tel: 46.8.444.15.00 Fax: 46.8.750.66.47 Switzerland Logic Sulzer Brugg/Biel Tel: 41.32.536363 Fax: 41.32.536367 Taiwan Logic Asia-Pacific Taipei Tel: 886.2.718.7828 Fax: 886.2.718.8869 Cheng Fong Technology Corporation Tel: 886.2.910.1180 Fax: 886.2.910.1175 Lumax International Corporation, Tel: 886.2.788.3656 Fax: 886.2.788.3568 Macro-Vision Technology Inc. Tel: 886.2.698.3350 Fax: 886.2.698.3348 United Kingdom Logic Europe Bracknell Tel: 44.1344.426544 Fax: 44.1344.481039
California Irvine Tel: 714.553.5600 Fax: 714.474.8101 Diego Tel: 619.635.1300 Fax: 619.635.1350 Silicon Valley Sales Office Tel: 408.433.8000 Fax: 408.954.3353 Design Center Tel: 408.433.8000 Fax: 408.433.7695 Colorado Boulder Tel: 303.447.3800 Fax: 303.541.0641 Florida Boca Raton Tel: 561.989.3236 Fax: 561.989.3237 Georgia Atlanta Tel: 770.395.3808 Fax: 770.395.3811
Dallas Tel: 972.788.2966 Fax: 972.233.9234 Houston Tel: 281.379.7800 Fax: 281.379.7818 Washington Bellevue Tel: 206.822.4384 Fax: 206.827.2884 Canada Ontario Ottawa Tel: 613.592.1263 Fax: 613.592.3253 Toronto Tel: 416.620.7400 Fax: 416.620.5005 Quebec Montreal Tel: 514.694.2417 Fax: 514.694.2699 INTERNATIONAL Australia Reptechnic South Wales Tel: 612.9953.9844 Fax: 612.9953.9683
Illinois Schaumburg Tel: 847.995.1600 Fax: 847.995.1622 Kentucky Bowling Green Tel: 502.793.0010 Fax: 502.793.0040 Maryland Bethesda Tel: 301.897.5800 Fax: 301.897.8389
Tel: 972.9.657190
Fax: 972.9.657194 Italy Logic S.P.A. Milano Tel: 39.39.687371 Fax: 39.39.6057867 Japan Logic K.K. Tokyo Tel: 81.3.5463.7821 Fax: 81.3.5463.7820 Osaka Tel: 81.6.947.5281 Fax: 81.6.947.5287
Massachusetts Waltham Tel: 617.890.0180 Fax: 617.890.6158 Minnesota Minneapolis Tel: 612.921.8300 Fax: 612.921.8399
Sales Offices with
Design Resource Centers
receive product literature, call 1-800-574-4286 (U.S. Canada); +32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, Europe) Department JDS; visit http://www.lsilogic.com
9000 Certified
Printed Recycled Paper
This document preliminary. such, contains data derived from functional simulations performance estimates. Logic verified functional descriptions electrical mechanical specifications using production parts. Logic logo design registered trademark Logic Corporation. other brand product names trademarks their respective companies.
Printed Order I15024 Doc. DB08-000065-00
Logic Corporation reserves right make changes products services herein time without notice. Logic does assume responsibility liability arising application product service described herein, except expressly agreed writing Logic; does purchase, lease, product service from Logic convey license under patent rights, copyrights, trademark rights, other intellectual property rights Logic third parties.
MPEG-2 Audio/Video Decoder

L64105 integrated, low-cost source audio/video (A/V) decoder MPEG-2 de

Top Searches for this datasheet

Other recent searches