L64021 Audio/Video Decoder balances high integration cost single chip

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L64021 Audio/Video Decoder balances high integration cost single chip

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L64021 MPEG-2 Digital Video Disk Decoder
L64021 Audio/Video Decoder balances high integration cost single chip design that delivers quality performance systems. Logic's integrated MPEG-2, Dolby Digital (AC-3) core provides full support both consumer-based players applications. Backward compatible with both existing CD-ROM Video formats, L64021 enables designers develop low-cost next generation systems. L64021 extends capabilities Logic's time-tested market-proven MPEG-2 decoders integrating licensed Content Scrambling System (CSS) technology. integrated unit provides secure authentication descrambling protected content. same time, L64021 maintains processor overhead system cost. L64021 Decoder receives coded audio, video, private data produce decoded audio/video output with subpicture graphics overlay. Logic optimized input/output interfaces cost integration into number system architectures. block diagram Figure illustrates L64021 system implementation. Figure System Block Diagram
Host
Source Drive Unit Motor Spindle Power Pickup
Host Interface Channel Control Demodulator NTSC/PAL Encoder Audio DACs Baseband Video Stereo Audio S/PDIF 4-Mbit DRAM 16-Mbit SDRAM
L64021 Decoder
Processor
April 1999
Copyright 1995-1997 Logic Corporation. rights reserved.
Logic's digital video architecture L64021 incorporates many unique features capabilities. These architectural elements include flexible preparsing system streams, processing sequence layer, flexible display controller, 24-bit/96-kHz Linear support, multitap filter. Video features include host programmable, high quality trick play modes. Logic's programmable trick play provides system designers flexibility develop unique features easy product differentiation. L64021 Decoder available 160-pin plastic quad flat package (PQFP) that compatible with other members Logic decoder family. L64021 manufactured using 0.25 micron lowpower CMOS process available 3.3-V version.
Features
Video Decoding
Includes embedded RISC Processor Integrates studio quality MPEG-2 video decoder Fully complies with Main Profile Main Level MPEG-2 standard,
13818-2
Decodes MPEG-2 bitstreams, including MPEG-2 program stream,
with private stream support
Decodes MPEG-1 bitstream defined 11172, including
MPEG-1 system layer
Operates image sizes CCIR601 resolution
pixels NTSC
Audio Decoding
Several audio output options available:
through Bypass ch.) Decoded from MPEG, LPCM, AC-3 ch.) AC-3 coded stream with multichannel extensions (5.1 ch.) MPEG coded stream with multichannel extensions ch.)
L64021 MPEG-2 Digital Video Disk Decoder
Combines MPEG Dolby Digital audio decoding with support
Linear data
Decodes dual channel MPEG audio, Layer 11172-3
supporting rates 8-448 Kbps sampling rates 22.05, 44.1,
Decodes channel Dolby Digital, downmixing outputs over
entire range compliant rates sampling rates
Supports Linear streams with sample rates Supports Dolby Logic downmix
Data Error Handling Capabilities
20-Mbits/s sustained input channel Adata rate Input data format: 8-bit parallel through dedicated channel interface
output: 8-bit slave mode
Complete on-chip channel buffer display buffer controls Error concealment maintains display images during channel errors Mute error concealment audio decoder external microcode external logic required
Video Display Graphics Support
Integrates flexible 256-color on-screen display (OSD)
controller
Allows connection external generator Programmable display management Programmable channel buffer display buffer size Slave video timing operation Supports trick modes commonly needed systems Integrates postprocessing filters image resizing (horizontal
vertical)
Integrates vertical filter letterbox format display Implements subpicture data processing on-chip Implements pulldown directly from bitstream
L64021 MPEG-2 Digital Video Disk Decoder
Supports scan with pixel accuracy from bitstream Supports 4:2:0 4:2:2 sampling filters 16-level alphablending
Cost Effective System Implementation
Programmable preparser accepts PES, streams Directly connects commodity SDRAM Input/output interfaces optimized glueless integration into
consumer video systems
Channel interface includes embedded Content Scramble System
(CSS) Unit descrambling authentication.
Operates from single 27-MHz clock, with additional audio sample
clock input
Total external memory required audio video decoding: 16Mbit SDRAM CCIR601 resolution
Interfaces Intel Motorola 8-bit Host initialization, testing,
status monitoring
Directly interfaces off-the-shelf NTSC/PAL encoders Directly interfaces off-the-shelf audio DACs 160-pin PQFP package power 3.3-V process TTL-compatible pins
L64021 MPEG-2 Digital Video Disk Decoder
Functional Description
Figure provides block diagram L64021's major functional units. overview major functions L64021 follows diagram. Figure L64021 Block Diagram
Audio Decoder
Counter MPEG-2 Host Interface Interrupt Control Data Address FIFO MPEG-2 Video Decoder RISC Processor Channel Interface MPEG-2 Program Stream Strobe Data Data Request Unit Programmable Preparser SDRAM Interface OSD/Graphics Dolby Digital Interrupt Generator Linear Serial Output Bypass
SYSCLK
1/300 Clock Divider
ACLK
Stereo Audio
S/PDIF (IEC958)
Host
Video Decoder Display Control
Filters Display Controller Data Timing NTSC/PAL Encoder Baseband Video
Data
Address Control
L64021
16-Mbit SDRAM
Video Audio Decoding
L64021 decode separate video audio elementary streams, streams (from transport decoders), program elementary stream (PES) containing both audio, video, private streams. addition, decoding parse critical headers both Presentation Time Stamp (PTS) Decoding Time Stamp (DTS) information necessary video audio synchronization.
L64021 MPEG-2 Digital Video Disk Decoder
Video Decoding
This section includes description major components involved handling decoding video:
Video Decoder Video Postprocessing Filters Letterbox Display On-Screen Display with Graphics Support Decoder
Video Decoder L64021 operates optimally image sizes pixels, with frame rate NTSC PAL). L64021 also decode MPEG-1 sequences. coded data channel have sustained rate Mbit/s. L64021 also supports images with resolution lower than pixels (see Video Postprocessing Filters). Video Postprocessing Filters Letterbox Display Images with resolutions below pixels interpolated full size using on-chip filters. This allows programming produced different resolutions decoded displayed televisions with standard NTSC timing, allows digital analog NTSC encoders operating standard television frequencies (typically MHz). addition, filters provide capability scan MPEG image 1/8-pixel accuracy. L64021 also supports letterbox display format with integrated vertical filter decimation (720 images decimated pixels). On-Screen Display Controller with Graphics Support Decoder L64021 integrates on-screen display (OSD) controller capable overlaying image pixels (720 PAL) bits/pixel MPEG video sequence while being decoded. addition, L64021 contains on-chip Subpicture Unit (SPU) decoder cost-effective integration graphics function. decodes graphic overlay executes instructions graphic display changed without intervention.
L64021 MPEG-2 Digital Video Disk Decoder
Audio Decoding
L64021 integrates MPEG (Musicam) Dolby Digital audio decoder with support Linear audio. decode channels MPEG audio Layer Layer over full range compliant rates sample rates. also decode channels Dolby Digital downmix this information channels audio output over full range compliant rates sample rates. audio decoder uses same memory video decoder channel buffers- which eliminates need extra SDRAM found other nonintegrated audio solutions.
External Interfacing
L64021 includes following external interfaces:
Host Interface Channel Interface Memory Interface Video Output Audio Output Audio Input
Host Interface stand-alone, dedicated host interface allows user program variety options monitor operation L64021. addition, through this port read user data that present data channel read errors flagged L64021. device does maintain unread user data indefinitely. host interface includes FIFO which more data written once FIFO becomes full. Subsequent data will lost. system controller must read data transmitted user data records MPEG bitstream, even that data subsequently used control some aspect video display subsystem. controller must read this data, then write L64021 internal state registers, necessary. host interface also allows read write data into memory channel buffer access.
L64021 MPEG-2 Digital Video Disk Decoder
Channel Interface L64021 includes independent parallel interface direct connection upstream error correction devices. interface uses simple signal handshaking compressed stream transfer decoder. L64021's channel interface handles incoming coded data, which assumed MPEG-2 compliant bitstream, provides error detection, reporting, content descrambling, disk/title authentication. channel interface detects data bitstream that does meet MPEG-2 Dolby Digital syntax grammar rules flag data exception processing. Hardware error handling includes error masking application concealment vectors video. Audio error concealment includes muting errors searching error-free frames. channel interface flags gross errors bitstream that channel buffer overrun underrun nonconformance bitstream. error flagging done errors masked display audio output. handle gross errors, program external microcontroller with error recovery mechanism. L64021 channel interface also includes fully integrated unit that provides on-core disk/title authentication descrambling. unit five modes: bypass, data extraction, descrambling, authentication disk extraction, authentication title decryption mode. Memory Interface L64021 supports direct connection commercial SDRAM frame stores, channel buffers, overlay memory. L64021 uses frame stores intermediate frame reconstruction display, separate video audio channel buffers rate matching, zero more regions graphic overlays. This storage combined into single, contiguous memory space accessed over 16-bit wide bus. most cases, this 16-bit SDRAM, total memory space Mbytes. interface between L64021 SDRAM requires external components. L64021 pinout allows connection SDRAM made single layer. During normal operation, L64021
L64021 MPEG-2 Digital Video Disk Decoder
exclusively controls SDRAM frame stores. However, possible access SDRAM through host port L64021 test, verification, access overlay stores channel information. Video Output L64021 provides digitized video output subsequent display. This data CCIR601 color space. video output operates with luminance sample rate that always exactly half device clock-nominally 13.5 from 27-MHz input clock. L64021 accept external synchronization signals slave mode. L64021 supports number trick modes specific needs systems, including freeze frame, skip pictures, skip pictures, search GOP. Audio Output audio decoder produces serial output that compatible with most commercial audio DACs. audio decoder includes circuitry maintain correct audio output sample rate based upon external audio clock. decoder also provides audio oversampling output clock external audio DAC; this audio output clock selected from audio clock inputs. addition, decoder supports IEC958 output format samples, transporting compressed Dolby Digital bitstreams, MPEG-2 multichannel extensions. Audio Input L64021 supports several audio input modes. supports connection Sony/Philips Digital Interface Format (S/PDIF) input that routed directly S/PDIF output. device also handles input signals that connected directly from CD-ROM player output.
Signal Descriptions
This section provides detailed information L64021 signals. signal descriptions useful hardware designers interfacing L64021 with other devices. Figure shows logic symbol L64021. Signals that active LOW. Otherwise, active HIGH.
L64021 MPEG-2 Digital Video Disk Decoder
Figure
L64021 Logic Symbol
WTN/WAITn DTACKn/RDYn A[8:0] D[7:0] SBD[15:0] SBA[11:0] SCASn SWEn SRASn SCLK SCSn SCS1n SDQM Memory Interface
Host Interface
READ/READn INTRn BUSMODE DSn/WRITEn DREQn
Channel Interface
CH_DATA[7:0] VREQn AREQn VVALIDn AVALIDn ERRORn
L64021 Decoder
SPDIF_OUT SPDIF_IN BCLK LRCLK ASDATA CD_BCLK CD_LRCLK Audio CD_ASDATA Interface CD_ACLK ACLK_441 ACLK_48 ACLK_32 A_ACLK AUDIO_SYNC
Test Interface
ZTEST SYSCLK RESETn SCAN_TE TM[1:0]
Miscellaneous
PLLVDD PLLVSS
BLANK PD[7:0] Video Output OSD_ACTIVE Interface CREF EXT_OSD[3:0]
L64021 MPEG-2 Digital Video Disk Decoder
L64021 major signal interfaces:
Host Interface page Channel Interface page Memory Interface page Video Output Interface page Audio Interface page Miscellaneous Test Interfaces page
Host Interface
A[8:0] Address Input This 9-bit address line provides access L64021's internal registers. address value these lines latched falling edge (Motorola) falling edge READn/WRITEn (Intel). Address Strobe (Motorola Mode only) Input This signal latches L64021) address currently A[8:0] bus. address latches falling edge signal. also indicates start cycle transaction. indicate start transaction. rising edge indicates transaction. Controller Select Input This signal specifies whether Host Intel Motorola microprocessor. When HIGH, Motorola mode selected. When LOW, Intel mode selected. Motorola processor uses specify read write transfers. Intel processor uses separate pins specify read write transfers. Please signal definition below. Chip Select (Motorola Intel Mode) Input This active-LOW signal indicates attempt external host access L64021 either read write cycle. event indicates start transaction Motorola mode. READn WRITEn indicates start cycle Intel mode. actual transaction type (either read write) determined
BUSMODE
L64021 MPEG-2 Digital Video Disk Decoder
READ polarity (Motorola type interface) READn WRITEn polarity (Intel type interface). cycle determined rising edge (Motorola) rising edge READn WRITEn (Intel). stay active more than transaction cycle. D[7:0] Host Data Bidirectional This host data 8-bit bidirectional data line used data communication between host L64021. During read cycle, D[7:0] carries valid information from internal L64021 register. DTACK WAITn indicate when data host data valid. rising edge WRITEn (Intel) (Motorola) indicates L64021 when strobe data into chip. Transfer Request Output This signal active-LOW output that indicates when decoder ready receive byte data. decoder considered ready when interface ready internal write FIFO full, internal read FIFO empty. these conditions met, DREQn asserted. maximum transfer rate over this interface Mbit/s. Data Acknowledge (Motorola) RDYn (Intel) 3-State Output This signal active when used DTACKn (Motorola mode). When used RDYn (Intel mode), this signal active LOW. When used DTACKn, L64021 drives this signal indicate external host that current transaction completed. signal 3-stated active. L64021 drives DTACKn HIGH when ready cycle, drives DTACKn when ready cycle. When used RDYn, L64021 drives this signal indicate external host that L64021 ready complete current transaction. L64021 drives RDYn HIGH when L64021 ready. signal 3-stated active.
DREQn
DTACKn RDYn
L64021 MPEG-2 Digital Video Disk Decoder
INTRn
Interrupt Output This signal active-LOW interrupt output. open drain. L64021's host interface drives this signal send interrupt Host CPU. Data Strobe (Motorola) WRITEn (Intel) Input (Motorola mode) indicates when strobes data L64021. During read cycle, start read transaction triggered when DSn, CSn, LOW. During write cycle, rising edge indicates when L64021 latches data present D[7:0]. When WRITEn (Intel mode) indicates that external host performing write cycle. READ/READn must HIGH during write cycle. indicates that host attempting write L64021's internal registers. address registered falling edge READn. rising edge WRITEn, L64021 latches data present D[7:0].
WRITEn
READ READn
Read/Write Strobe (Motorola) READn (Intel) Input READ (Motorola mode) indicates whether current cycle read write. When READ HIGH, read cycle progress. When READ LOW, write cycle progress. must access L64021. READn (Intel mode) when external performing read cycle. WRITEn must HIGH during read cycle. When both READn LOW, host reading from L64021's internal registers. address registered falling edge READn.
WAITn
Device Wait (Motorola) Device Wait (Intel) 3-State Output This signal 3-state active when used WAITn signal. used interface processors other than Motorola Intel host CPUs. signal's function similar DTACKn/RDYn (described earlier); however, polarity inverted. L64021 drives this signal HIGH indicate external host that current transaction completed. signal
L64021 MPEG-2 Digital Video Disk Decoder
3-stated active. L64021 drives signal when ready cycle, drives signal HIGH when ready cycle.
Channel Interface
AREQn Audio Transfer Request Output When L64021 asserts this signal LOW, indicates that L64021 ready receive byte coded audio data system data system mode). L64021 considered ready when both interface ready there room audio channel buffer. this true, then AREQn asserted. maximum transfer rate over this interface Mbit/s. system, AREQn AVALIDn input program stream that present CH_DATA[7:0]. Audio Data Valid Input rising edge AVALIDn writes next byte audio data program stream data that present CH[7:0] pins. AVALIDn used with data clock synchronous input L64021's channel interface. Channel Data Input CH_DATA[7:0] input that serves parallel path incoming channel data. Channel Data Clock Input free-running clock from external channel. Together, VALIDn signals write data synchronously L64021 channel input. Error Input ERRORn active-LOW input signal. external channel device asserts this signal indicate that channel data contains error. ERRORn signal latched with data rising edge AVALIDn VVALIDn. ERRORn indicates uncorrectable errors channel, invokes error handling L64021. ERRORn used transfers.
Note:
AVALIDn
CH_DATA[7:0]
ERRORn
L64021 MPEG-2 Digital Video Disk Decoder
Sector Input external channel device asserts during pack start code sector. L64021 uses error detection registers signal rising edge AVALIDn. Video Transfer Request Output This signal active-LOW output. L64021 asserts VREQn when ready receive byte coded video data. L64021 ready when both interface ready there room video channel buffer. these conditions true, VREQn asserted. maximum transfer rate over this interface Mbit/s. system, VREQn VVALIDn pins used. Video Data Valid Input rising edge VVALIDn writes into channel buffer next byte video data that present CH[7:0] data bus. VVALIDn used system program stream modes. VVALIDn used together with data clock synchronous input L64021 channel.
VREQn
Note:
VVALIDn
Memory Interface
SBA[11:0] SDRAM Address Output This 12-bit output address specifies row/column address connects directly external SDRAM memory. L64021 uses external SDRAM memory picture reconstruction channel buffering. SDRAM Data Bidirectional This 16-bit bidirectional data connects directly external 16-bit SDRAM memory. L64021 uses external SDRAM memory picture reconstruction channel buffering. SDRAM Column Address Select Output This active-LOW signal that drives attached SDRAM.
SBD[15:0]
SCASn
L64021 MPEG-2 Digital Video Disk Decoder
SCLK
SDRAM 81-MHZ Clock Bidirectional This 81-MHz clock signal drives attached SDRAM. Chip Select SDRAM Output SCSn active-LOW signal that selects lowaddress bank SDRAM, which used first Mbits memory. Chip Select Second SDRAM Output SCS1n active-LOW signal that selects highaddress bank SDRAM. This signal used systems that have more than Mbits DRAM. SDRAM Control Output SDQM active-HIGH output signal SDRAM data control mask. SDRAM Address Select Output This active-LOW signal that drives attached SDRAM. SDRAM Write Enable Output This active-LOW signal that drives external SDRAM. L64021 asserts this signal enable SDRAM write operation.
SCSn
SCS1n
SDQM
SRASn
SWEn
Video Output Interface
BLANK Blank Output BLANK composite blank output from L64021 display controller. polarity active-HIGH. Display Controller Output Output This display controller output signal serves Chroma reference. CREF HIGH during component Chroma. Palette Selection Input This four-bit input selects from colors on-chip color palette external function. EXT_OSD[3:0] data sampled SYSCLK/4 6.75 MHz, providing with resolution pixels.
CREF
EXT_OSD[3:0]
L64021 MPEG-2 Digital Video Disk Decoder
Horizontal Sync Input horizontal sync signal, which resets horizontal counters display controller. horizontal sync signal must synchronous SYSCLK. On-Screen Display Output This active-HIGH signal that indicates on-chip active. This indicates which pixels have mixed pixel port. Active output occurs pixel containing mixed data.
OSD_ACTIVE
PD[7:0]
Pixel Data Output Output data PD[7:0] represents pixel data reconstructed picture. pixel data formatted CCIR601 chromaticity. Vertical Sync Odd-Even Field Input host program L64021 that either conventional Vertical Sync input even/odd field indicator. When even/odd field indicator mode, internal display controller counters reset each time changes state beginning each field). parity field controlled timing relative odd/even field indicator should synchronous SYSCLK.
Audio Interface
A_ACLK Audio Clock Output A_ACLK audio output clock that selected from audio input clocks (ACLK_32, ACLK_441, ACLK_48). Audio Clock (32) Input This audio clock where equals 768, 512, 384, 256. Audio Clock (44.1) Input This audio clock 44.1 where equals 768, 512, 384, 256. Audio Clock (48) Input This audio clock where equals 768, 512, 384, 256.
ACLK_32
ACLK_441
ACLK_48
L64021 MPEG-2 Digital Video Disk Decoder
ASDATA
Audio Serial Data Line Output ASDATA output serial audio data. host program format either output mode. Audio Synchronization Output This signal provides audio sync indication transport systems that require hardware sync controls. (Typically, this signal used only systems.)
AUDIO_SYNC
BCLK
Serial Clock Output This signal clocks ASDATA into BCLK's rising edge. BCLK programmable frequency that host during initialization. External Audio Clock Input This clock provides reference source L64021's audio output stage that used when L64021 bypasses audio output. Typically, clock rate either
CD_ACLK
CD_ASDATA Audio Serial Data Line Input This signal serial audio data input that used when L64021 bypasses audio output. CD_BCLK Serial Clock Input This signal clocks ASDATA into L64021 clock's rising edge. L64021 uses this clock when bypassing audio output. Serial Left/Right Clock Input This input clock indicates which samples belong left right stereo channels. L64021 uses this clock when bypassing audio output. Serial Left/Right Clock Output This output clock, which programmable frequency, indicates which samples belong left right stereo channels. S/PDIF Input This input signal S/PDIF (IEC958) formatted data. During bypass mode, L64021 routes SPDIF_IN signal directly SPDIF_OUT pin.
CD_LRCLK
LRCLK
SPDIF_IN
L64021 MPEG-2 Digital Video Disk Decoder
SPDIF_OUT
S/PDIF Output This signal, whose frequency programmable, contains audio data Linear samples IEC958 consumer format. host configure L64021 provide this signal either MPEG Audio Dolby Digital compressed bitstream.
Miscellaneous Test Interfaces
Loop Filter Bidirectional system uses this connect external loop filter L64021. Power Supply Phase-locked loop dedicated power input pin. Ground Phase-locked loop dedicated ground input pin. Input Input
PLLVDD PLLVSS RESETn
Reset Input This active-LOW input signal. When external source asserts RESETn, L64021 resets itself. minimum RESET pulse width eight cycles SYSCLK. SYSCLK must running during reset. Scan Test Enable Input When asserted, this signal enables scan test mode. This mode used only during manufacturing test. During normal system operation, this LOW. Device Clock Input SYSCLK L64021's input system clock. clock nominal frequency MHz. Picture reconstruction video timing referenced with respect this clock. Test Mode Input Logic uses these pins during manufacturing test. They intended other purpose. both pins during normal system operation. Test Mode Input Test mode pin. This signal used only manufacturing test. this HIGH during normal system operation.
SCAN_TE
SYSCLK
TM[1:0]
ZTEST
L64021 MPEG-2 Digital Video Disk Decoder
Specifications
This section contains electrical parameters L64021 Decoder. Table lists absolute maximum ratings. Exceeding these values cause damage L64021. Table defines recommended operating supply voltage temperature. Table shows capacitance, Table lists characteristics. Table
Symbol TSTGP
Absolute Maximum Ratings
Parameter Supply Compatible Input Voltage Input Current Storage Temperature Range (PQFP Package) Limits1 -0.3 +3.9 -1.0 +6.5 +125 Units
Referenced VSS.
Table
Symbol
Recommended Operating Conditions
Parameter Supply Ambient Temperature Limits +2.15 Units
Table
Symbol COUT
Capacitance
Parameter1 Input Capacitance Output Capacitance Units
Measurement conditions (VIN tolerant buffers), clock frequency MHz.
L64021 MPEG-2 Digital Video Disk Decoder
Table
Symbol
Characteristics
Parameter Voltage Input CMOS Voltage Input High CMOS Compatible Voltage Output 4-mA Output Buffers 8-mA Output Buffers Voltage Output High 4-mA Output Buffers 8-mA Output Buffers Current Input Leakage2 with Pulldown with Pullup Current 3-State Output Leakage Current P-Channel Output Short Circuit (4-mA Output Buffers)3, Current N-Channel Output Short Circuit (4-mA Output Buffers)3, Quiescent Supply Current Dynamic Supply Current Condition1 Units
-4.0 -8.0 Max, VOUT Max, VOUT -214 -117
-115
IOSP4
IOSN4
Max, VOUT
Max,
Specified equals ambient temperature over specified range. CMOS inputs. more than output shorted time maximum duration second. These values scale proportionally output buffers with different drive strengths.
L64021 MPEG-2 Digital Video Disk Decoder
Pinout, Package, Ordering Information
L64021 available 160-lead Plastic Quad Flat Package (PQFP). Table provides L64021 order number. Figure supplies L64021 Decoder pinout diagram; Figure Figure contain package mechanical drawings. Table L64021 Ordering Information
Clock Frequency
Order Number 65032A1
Package Type 160-lead PQFP
Operating Range Commercial
L64021 MPEG-2 Digital Video Disk Decoder
Figure
L64021 160-Lead PQFP Pinout Diagram
PLLVSS PLLVDD SDQM SWEn SCASn SRASn SCSn SCS1n SBA_11 SBA_10 SBA_0 SBA_1 SBA_2 SBA_3 SBA_4 SBA_5 SBA_6 SBA_7 SBA_8 SBA_9 SCLK SBD_8 SBD_9 SBD_10 SBD_11 SBD_12 SBD_13
SBD_7 SBD_6 SBD_5 SBD_4 SBD_3 SBD_2 SBD_1 SBD_0 CH_DATA_0 CH_DATA_1 CH_DATA_2 CH_DATA_3 CH_DATA_4 CH_DATA_5 CH_DATA_6 CH_DATA_7 ERRORn AVALIDn VVALIDn VREQn AREQn
View
SBD_14 SBC_15 SCAN_TE ZTEST AUDIO_SYNC SPDIF_OUT ASDATA LRCLK BCLK A_ACLK SPDIF_IN CD_ASDATA CD_ACLK CD_LRCLK CD_BCLK ACLK_32 ACLK_48 ACLK_441 EXT_OSD_3 EXT_OSD_2 EXT_OSD_1 EXT_OSD_0 CREF BLANK PD_7 PD_6 PD_5
pins connected.
SYSCLK RESETn DREQn INTRn BUSMODE DTACKn READ OSD_ACTIVE PD_0 PD_1 PD_2 PD_3 PD_4
L64021 MPEG-2 Digital Video Disk Decoder
Figure
L64021 160-Lead PQFP Mechanical Drawing (Sheet
board layout manufacturing, obtain engineering drawings from your Logic marketing representative requesting outline
MD96.PZ
L64021 MPEG-2 Digital Video Disk Decoder
Figure
L64021 160-Lead PQFP Mechanical Drawing (Sheet
MD96.PZ
L64021 MPEG-2 Digital Video Disk Decoder
Notes
L64021 MPEG-2 Digital Video Disk Decoder
Notes
L64021 MPEG-2 Digital Video Disk Decoder
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L64021 Audio/Video Decoder balances high integration cost single chip

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