December, 1997 Order Number: 292206-003 Information this doc

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

December, 1997 Order Number: 292206-003 Information this doc

Datasheet Thumbnail

Top Searches for this datasheet

Audio Using 8x930Ax/Hx Controller Audio Codec
December, 1997
Order Number: 292206-003
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptios time, without notice. Copies documents which have ordering number referenced this document, other Intel literature, obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation 1997. *Third-party brands names property their respective owners.
Contents
INTRODUCTION Digital Audio Universal Serial Intel's 8x930Ax/Hx Controller Traditional Audio 2.3.1 Possible Drawbacks Using Sound Cards Audio Codec Background Selection Codec Basics ARCHITECTURE CONSIDERATIONS Performance Features Interface Signals 3.5.1 Serial 3.5.2 Parallel 8x930Ax/Hx Interface 8x930Ax/Hx Interface 8x930Ax/Hx Codec Interface 8x930Ax/Hx Codec Interface Example HIGH LEVEL SYSTEM CONSIDERATIONS AD1845 Details 8x930Ax/Hx AD1845 Interface Example Considerations Recommendations 5.4.1 5.4.2 Data Request 5.4.3 Matching Data Rates 5.4.4 Offsetting Conclusion References Firmware Template Communication Between 8x930Ax/Hx Audio Codec Firmware Guideline 8.1.1 Initialize 8.1.2 8.1.3 Codec Request Sample Subroutines Sample Firmware Subroutines Communication Between 8x930Ax/Hx Audio Codec 10.0 Schematics
Contents
Figures Generic Coding Decoding Block Diagram 8x930Ax/Hx AD1845 Block Diagram
AD1845 Timing Requirements 8x930Ax/Hx Parallel Port Write Timing Read Timings AD1845 Read Timings 8x930Ax/Hx Wait State) 8x930Ax/Hx AD1845 Offset Tables Sample Wire Between 8x930Hx Audio Codec
AP-648
INTRODUCTION
This application note provides introduction interfacing 8x930Ax/Hx with audio codec perform playback digital audio, presents overview relates digital audio, discusses codec background selection. also describes 8x930Ax/Hx interfacing, providing example with design recommendations.
rich combination integrated features makes 8x930Ax/Hx peripheral controller flexible powerful. contains MCS® microprocessor core, four 8-bit ports, three 16-bit timers, hardware watchdog timer, Programmable Counter Array (PCA), Serial port. purpose this application note provide introduction interfacing 8x930Ax/Hx with audio codec perform playback digital audio.
Digital Audio Universal Serial
Traditional Audio
Universal Serial (USB) industry standard interconnection designed support wide range peripherals around topology three elements: host, hubs, functions. host peripherals functions. Peripherals interface host cables protocol. enable variety peripherals, protocol defines four transfer types: Control, Isochronous, Interrupt Bulk. Every peripheral will need support control transfers that configuration command/status information flow between host peripheral. Isochronous transfers provide guaranteed access constant data rate support (computer-telephone integration) audio systems. Interrupt transfers designed support human input devices such joysticks, mice, keyboards. These devices need communicate small amounts data infrequently, with bounded service periods. Bulk transfers designed peripherals such printers digital cameras. These devices communicate large amounts data bandwidth becomes available. implements blocking bandwidth allocation scheme that denies access peripheral peripheral exceeds current bandwidth allocation latency requirements. allows bandwidth used isochronous interrupt transfers. remaining reserved control transfers. Bulk transfers only occur bandwidthavailable basis.
There currently predominant methods generating audio using first audio. Similar home stereo compact disk players, CDROM drive reads compact disk produces analog output. This analog signal inputted sound card, processed further, then outputted from using standard plug. second method generating audio performed reading file from memory into sound card. sound card performs decoding processing, converts digital data analog, outputs analog signal from standard plugs. This procedure used when user downloads audio file initiates playback from hard drive.
2.3.1
Possible Drawbacks Using Sound Cards
There several drawbacks using sound cards that install into card slot. sound card utilizes resources like interrupts ports. also additional cost. Since sound card inserted into box, reconfiguration required which viewed difficult many users. interior also noisy with electromagnetic interference (EMI). This limit sound quality `inside box' solutions, there analog signal that sent from CD-ROM sound card. design complexity, sound cards limited channels. This hamper their scalability preclude their multiple-channel surround sound systems without addition processing power speakers.
Intel's 8x930Ax/Hx Controller
Intel's 8x930Ax/Hx single chip, Specification Rev. compliant, peripheral controller. presence
AP-648
Audio
USB, however, lends itself nicely audio applications because `outside box'. audio data remains digital until outside converted back analog just prior speaker amplification circuitry, resulting improved sound quality. Digital audio typically higher fidelity, which obvious high-end speakers. based solution also scalable allowing speaker vendor increase quality audio without addition hardware between host controller. instance, possible have more than channels audio data, enriching user's multimedia experience. Similarly, ease plug play makes implementation attractive. data processing done host, providing cost savings speaker manufacturer. user need only pair capable speakers. also demonstrated ability handle bandwidth required audio applications. compact disk sample rate 44.1kHz bits sample. Since frame rate 1ms, audio peripheral will receive nine frames containing samples frame containing samples. other words, over time period 10ms, peripheral will receive 9*44 samples, which averages 44.1 samples millisecond equals sample rate 44.1kHz. Assuming channels audio data, bytes protocol overhead, worst-case stuffing 16%, playback system will need handle (45*16*2 10)*1.16 1682 bits/ms, approximately bytes/ms. Each frame data payload 1024 bytes. Therefore, playback stereo audio signal would
consume approximately available bandwidth. each 210B packet, there will (45*16*2) 180B audio data.
Codec Background Selection Codec Basics
Given that digital-to-analog conversion will occur inside peripheral, beneficial cover operation codecs. general, codecs used COde and/or DECode data. term somewhat general, that codecs available different types data; such audio video. also used occasion refer COmpression DECompression, which data encoded according algorithm (MPEG example). audio, industry accepted data format linear Pulse Code Modulation (PCM). More specifically, channels data (stereo) that represented 16-bit twos complement digital word. Figure shows general block diagram coding decoding. Coding done when analog signal sampled analog-to-digital converter (ADC) quantized digital word this example, 16-bit word with twos complement format). Depending application, digital signal processing (DSP) then performed digital samples purpose filtering, compression, etc. basic form doesn't compression, there block application. Decoding digital samples done digital-toanalog converter (DAC). output reconstructed analog signal. should noted that two-channel stereo application, there separate data paths with duplicate blocks that each channel controlled individually.
Analog Input
Analog Output
Sample Clock
A4439-01
Figure Generic Coding Decoding Block Diagram
AP-648
example coding recording audio waveform which entails first half system shown Figure page analog waveform digitized, compressed necessary, then stored medium such Audio playback second half system, where digital words read from medium, decompressed necessary, then converted from digital analog played through speaker.
Features
ARCHITECTURE CONSIDERATIONS
codec chip usually includes necessary filters support circuitry used converters. They generally provide amplifier circuits that drive speakers. output typical codec line level output (RCA type connectors). Therefore, standard audio amplifier circuitry used. Many codecs also output voltage references help with biasing amplifiers. Other features consider when choosing codec are: serial parallel interface, bi-directional transfer capability, buffering. Some codecs support byte-wide parallel transfer while others support bit-wide serial exchange. previously mentioned, frame contain bytes audio data. Therefore, controller must deliver data rate 180KBps codec. designer audio system must match processing needs codec processing capabilities controller. controller required process more than just audio data, beneficial parallel interface. This would increase controller resources available other processes. Bi-directional capability also increase codec's cost complexity. Support bi-directional transfers means that both coding decoding done; although simultaneously. Typically, reconfiguration necessary switch between playback record modes. Bi-directional support will increase interface complexity well. Finally, chip buffering feature consider. Some codecs provide FIFO buffers ease interface timing requirements microprocessors. Since data delivery must guaranteed, buffer allows some tolerance servicing codec's need data. This especially important controller will process more than task. clock rate controller will much higher than audio sample rate, system designer must take precautions assure that task switch overhead accommodated.
Several different circuit architectures exist performing analog-to-digital digital-to-analog conversions. 16-bit digital audio, appears that sigma delta ADCs DACs industry favorite. might expect, there design trade-offs that have made codec manufacturers. sigma delta architecture offers appropriate balance between speed conversion resolution bits. necessary casual user understand fine details conversion done. Conversely, process shouldn't considered black box. Sigma delta converters typically employ integrators, comparators, digital filters (decimation). theory operation rather involved, main principle that input oversampled, threshold approximations made, filtering done extract output. Since oversampling used, codec user should expect supply reference frequency substantially higher than sample rate audio data.
Performance
Another main consideration that should examined signal-to-noise ratio (SNR). SNR1 used figure merit ADCs DACs represents `cleanliness' output. typically computed Fast Fourier Transform (FFT) output signal under pure sinusoidal input. rule thumb that high quality audio requires least 75dB. typically find converters with 80dB. However, must understand that system into which codec placed great effect sound quality.
Interface Signals
ratio fundamental frequency compared other frequencies output.
number interface signals required codec depends number features type interface. Typically, there sets signals connecting codec controller: data control. possible find codecs that require relatively interface signals,
AP-648
this typically means that control data information multiplexed. Because multiplexing eases number interconnects, requires more management controller greater attention timing coding.
3.5.1
Serial
with serial case, number interconnects climb quickly with additional features. Some parallel codecs capable interfacing directly which complicate interface control issues. Likewise, bi-directional support could increase number interconnects.
serial interface will most likely require from interface signals. data control bundles usually separate. Control information passed signals: CDATA, CSHIFT, CLATCH. CDATA serial control data. This data used configure codec sampling rate, data format, filter programming, master clock frequency, etc. CSHIFT clock signal that clocks each bit, serially, into control buffer. CLATCH signal that latches control word into register initiates reconfiguration. Data passed similar manner SDATA, SSHIFT, LRCLK. SDATA serial data. SSHIFT clock signal that shifts each data into buffer. LRCLK indicates whether data word left right channel. example, bits left channel information clocked into buffer using SSHIFT. transition LRCLK latches data word then signals next bits right channel data. remaining signals vary from codec codec. There will least chip enable initialization signal. There could also separate control signals features like muting, power management, transfer direction. Support bi-directional transfers require additional interface signals. This sometimes depends whether codec becomes master remains slave. Keep mind number control signals complexity control logic.
8x930Ax/Hx Interface 8x930Ax/Hx Interface
implementation 8x930Ax/Hx divided into four sections: first-in, first-out (FIFO), Function Interface Unit (FIU), Serial Interface Engine (SIE), transceiver. 8x930Ax/Hx total eight FIFOs: four transmit FIFOs four receive FIFOs. transmit/receive FIFOs support four function endpoints (0-3). Endpoint bytes dedicated control transfers. Endpoint user configurable 1024 bytes, Endpoint bytes. Endpoints used interrupt, isochronous, control, bulk transfer types. transmit receive FIFOs circulating FIFOs which support separate data sets variable sizes contain byte count registers that access number bytes data sets. They also have flags that detect full empty FIFO have capability retransmitting current data set. FIU, SIE, transceiver make rest 8x930Ax/Hx's interface. transceiver circuitry detects drives signaling data lines. serial interface engine protocol interpreter. responsible stuffing/unstuffing ensuring that transmissions across cables least significant (LSb) first. controls operation FIFOs monitors data transaction. operation these three units isn't much concern user. However, more information found 8x930Ax, 8x930Hx Universal Serial User's Manual Given data payload size, audio applications will Endpoint More specifically, 1024 byte FIFO will configured into byte sections. During transmission audio stream, data from frame will read into section start frame (X+1), data section will valid incoming data from host will read into section start frame (X+2),
3.5.2
Parallel
parallel interface will require approximately interface signals. Control data information usually multiplexed over parallel bus. Data information passed DATA[7:0], DCLK, LRCLK. entire 8bit word will latched using signal. LRCLK required signify separation left/right data. Control data also output onto DATA[7:0]. additional control signals asserted notify codec whether incoming byte audio data control information. There will also reset initialization signal.
AP-648
data section will valid incoming data from host will overwrite section Note that re-transmit feature does apply isochronous transfers. Also note that protocol requires least significant bits least significant bytes first. takes care transmitting least significant most significant given byte, user need worry about first. user's responsibility, however, ensure that multi-byte data packets transmitting least significant bytes (LSB) first.
matter 8x930Ax/Hx configured page mode non-page mode. codec that uses parallel interface considered second memory device. codec control interface request data sample control information. After controller detects request, writes data onto system bus. great deal care must taken with address decoding timing. designer needs make sure that reads/writes memory acknowledged codec vice versa. Using 18-bit addressing modes 8x930Ax/Hx useful. external logic gate decode these signals generate codec's enable signals. transfer control signals done using ports Similar Serial method, signal transitions these pins must programmed explicitly.
8x930Ax/Hx Codec Interface
Once data been captured from cable into transceiver FIFOs, there methods which transfer data from 8x930Ax/Hx codec. first through Serial port. second through system ports isochronous transfers, 8x930Ax/Hx configured high speed device runs internally 12MHz. serial port supports communication with modems other external peripheral devices. operate full duplex asynchronous modes half duplex synchronous mode. half duplex mode (mode clock output while data received transmitted pin. Transfers controlled using Serial Port Control (SCON) Serial Buff (SBUFF) registers. Similar transmit/receive FIFO's, data transferred first. user must aware that peripheral cycle equal 8x930Ax/Hx's clock cycle. Peripheral cycles rate Fclk/6. internal clock rate 12MHz equates 2MHz clock rate pin. Additional interface signals controlled using remaining I/O's Port SCON register polled determine completion data sample transfer therefore trigger LRCLK signal. Since 8x930Ax/Hx only Serial port, transfer control information needs programmed explicitly. system (ports used communicate with external memory. external supports bits addressing bits data using ports interface. port used bits address information while other 8-bit port multiplexed with address data. From codec's perspective, does
8x930Ax/Hx Codec Interface Example
following example shows what would need implement playback digital audio using 8x930Ax/Hx AD1845 Parallel Port Stereo Codec from Analog Devices. This recommendation only design application example. Many codecs with parallel interfaces could conform this example. intended cover details designing audio system, merely address some issues faced system designers.
HIGH LEVEL SYSTEM CONSIDERATIONS
goals provide simple overall design playback stereo digital audio data. serial codecs considered this example required that data sent first. previously discussed, serial output from 8x930Ax/Hx first. This requires that reordering done. theory, could operations individually write bits 8x930Ax/Hx's output pins. However, assumed that timing restrictions coding overhead complex make this viable solution. Another possible solution would serial port conjunction with some external components. maximum peripheral clock rate from serial port 2MHz. audio data rate bytes/ms 1.44
AP-648
Mbits/s. Therefore, serial port's clock cycles need available transferring data. program code interrupt routines streamlined satisfy this throughput requirement. instance, program code could simplified that sole responsibility would transfer data from 8x930Ax/Hx receive FIFO serial port. external FIFO buffer, capable reordering bits each byte, could used state machine could designed FPGA control interface between FIFO codec. This would remove logic complexity from 8x930Ax/Hx. FPGA would responsible codec's configuration regulate flow data codec. Care would have taken, since codec speaker system would essentially asynchronous 8x930Ax/Hx system. 8x930Ax/Hx would simply pump data serial port into FIFO. FPGA would have monitor state codec fill level FIFO coordinate flow data between two. serial interface utilized other purposes, parallel codec solution also implemented. Although parallel codec typically more expensive than serial codec, some additional features prove beneficial provide lower overall cost. example, supports burst type transfer that simplifies handshaking. This helps ease latency requirements with controller. AD1845 also flexible part terms system configuration. programmed accept several data formats data rates, operational with range clock rates. Finally, many parallel codecs support bi-directional transfers power down modes, leaving room future development.
Addressing codec's registers performed ADR1:0 signals. These bits input select Index Address Register (IAR), Indexed Data Register (IDR), Status Register, Data Register. These four registers considered have direct forms addressing. There also registers that have indirect addressing. register holds bits data that signify addresses indirect registers. contains data that read/written register pointed IAR. other words, user selects particular control register driving ADR1:0 writing appropriate bits parallel port. This loads with indirect address. driving ADR1:0 register selected. next write parallel port loads data into particular indirect register that addressed IAR. Because necessary perform writes data writes signals update control register, setup initialization become cumbersome. However, AD1845 supports Direct Memory Access (DMA) protocol during data transfers. protocol similar burst type transfer. codec's buffer full, codec requests data. each request, controller acknowledges request proceeds output bytes data left/right pair). This type protocol helps down processing overhead. every interrupt request codec, 8x930Ax/Hx returns bytes data instead just byte. During playback, signaling follows: codec requests data asserting Playback Data Request (PDRQ) high. controller acknowledges asserting Playback Data Acknowledge (PDAK) low. controller then follows outputting data onto bus. Data clocked into codec WR#1 input. strobed data latched into codec rising edge WR#. AD1845 de-asserts PDRQ falling edge final strobe controller de-asserts PDAK after rising edge final strobe. This completes handshake codec will able issue another data request. should noted that inputs ignored while PDAK asserted. stop playback, user must reset bits control register using IDR. This must done between PDRQ data requests. PDRQ requests must acknowledged. controller stopping playback loaded maximum clock rate 6.25
AD1845 Details
(16-bit twos) complement data, AD1845 FIFO considers `sample' pair left/right data samples. Therefore, on-chip 16-sample FIFO will hold left/right pairs bytes bits audio data. data payload each frame bytes, AD1845 capable holding over third data frame. Additionally, AD1845 accepts data which transferred byte first. expects left channel, left, right, right. This same order that bytes transmitted host, there need byte reordering.
AP-648
latched data into register, PDRQ output codec, controller must acknowledge request. must output PDAK strobe four times. When codec de-asserts PDRQ, controller write finish stopping playback. power initialization AD1845 takes approximately 512ms. reads during initialization polled value other than determine when initialization completed. This indicates that controller will have perform reads from codec, even there bi-directional transfers. Similarly, when certain parameters changed during setup, AD1845 goes through routines that allow filters other circuitry settle. controller must again poll register.
example, assumed that code would contained external chip. on-chip memory should suffice scratch area there shouldn't need write external memory. first issue addressed timing interface signals. Figure indicates timing required AD1845 Figure indicates default timings 8x930Ax/Hx parallel port. timings see, setup hold data byte with respect 10ns; 15ns AD1845. equivalent times 8x930Ax/Hx 68ns 28ns, indicating that setup hold times compatible. However, there discrepancy width write pulse. AD1845 requires minimum width 100ns 8x930Ax/Hx default configuration only provides 71.8ns. Therefore, 8x930Ax/Hx must configured with extra wait state. This will increase width 154ns. Since program executing ROM, 8x930Ax/Hx signal connected only codec.
8x930Ax/Hx AD1845 Interface Example
general system block diagram shown Figure below. 8x930Ax/Hx provides on-chip data memory. code executed external memory (ROM RAM) on-chip ROM. this design
A8:15 PSEN# D0:7 A0:7 Data [7:0]
8x930Ax/Hx
EPROM
P1,P3
AD1845
A16:17
Amplifier Speaker
NOTES P1,P3 Ports used A16:17, INT0# other codec interface signals Codec interface signals WR#, CS#, PDAK#, PDRQ, ADR1:0, RESET#
A4437-01
Figure 8x930Ax/Hx AD1845 Block Diagram
AP-648
PDRQ PDAK Byte Byte
A4443-01
DATA (7:0)
Figure AD1845 Timing Requirements
71.8
Address
Data
A4442-01
Figure 8x930Ax/Hx Parallel Port Write Timing
DATA[7:0]
Byte
A4440-01
Figure Read Timings AD1845
AP-648
PSEN#
Address
Data
A4441-01
Figure Read Timings 8x930Ax/Hx Wait State) Reading from codec presents some additional problems since there must determining controller reading from memory chip codec. this assign codec memory address memory block. read from that particular location block ignored external ROM. 8x930Ax/Hx provides 16-, 17-, 18-bit addressing. Under 18-bit addressing, outputs (pins P1.7 P3.7) select four 64KB memory pages (00, FF). program code executing should easily inside 64KB block. This program code reside page defining codec page decode generate codec's read signal. Namely, ORing A16, A17, PSEN# will produce read signal codec. Required read timings shown above Figure Figure timings When addressing codec, bits address data sent onto system 8x930Ax/Hx irrelevant. With wait state, 8x930Ax/Hx requires valid data within 133ns after applying PSEN#. AD1845 deliver data being read 40ns, decoding logic roughly 90ns generate codec's read signal. Note that reads, including ones external chip, will have wait state. This will degrade program execution some degree, there will extra cycle latency from reads.
AP-648
Considerations Recommendations
5.4.3
Matching Data Rates
5.4.1
Although bandwidth allotment isochronous data guaranteed, there guarantee regarding exact placement isochronous data inside particular frame. Furthermore, exact byte count data will also vary. Since placement exact size data packet vary from frame frame, system designer must Start Frame (SOF) interrupt RXCNT register determine when data valid much data been received. previously mentioned, endpoint receive FIFO 1024 bytes configured byte FIFOs. Data each FIFOs qualified SOF. other words, tells user that frame started that isochronous data received previous frame must valid. SOFH register contains Start Frame (ASOF) which indicates that been received. This generate interrupt. interrupt routine then poll RXCNT register, which contains byte count data packet which received.
delivery isochronous data discrete packets presents some other issues that should addressed. average, delivery rate consumption rate same (44.1KHz). However, there phase synchronization between clock codec's clock. Therefore, there will phase misalignment. Clock jitter phase drift component variations will cause temporary mismatch delivery consumption rates. instance, imagine that samples delivered frame. This data must feed codec next 1ms. Since codec's sampling clock isn't synchronized, could through cycles time period. Similarly, frame deliver samples, codec only request Since delivery consumption could mismatched during time period, frame suffer from data starvation while next frame extra samples that aren't consumed. system designer must determine these issues will handled. Many codecs will replay last sample data available. easily drop samples moving next receive FIFO when interrupt received. data that received previous frame transferred codec simply used. This would simplest method handling much little data. course, adding dropping samples without interpolation averaging will degrade performance.
5.4.2
Data Request
8x930Ax/Hx's external interrupts (INT0# INT1#) used detect AD1845's request data (PDRQ signal). Edge triggered interrupts must highto-low transition stay least state times (666ns). PDRQ signal active high, must inverted. This absorbed into logic that contains logic. must realize that PDRQ minimum de-assertion time 320ns between requests. This should present problem, rather indicate degree turnaround that necessary when codec's buffer full. RXDAT register contains byte which currently active receive FIFO. FIFO pointers incremented automatically after each read user need only concerned with moving data from RXDAT output port. Data transmission done using loop. interior loop detects PDRQ, outputs PDAK, performs moves from RXDAT output port. RXCNT number bytes received particular frame signifies loop exit point.
5.4.4
Offsetting
problem with frame starvation lies fact that there will contention each time period (end each frame). 8x930Ax/Hx receives samples data packet must spread that data over time period. This will instigate race between arrival next frame emptying codec's buffer. example, assume 8x930Ax/Hx transmits last byte data from packet fills AD1845 buffer. AD1845 will deplete sample from buffer assert PDRQ. 8x930Ax/Hx will able respond. AD1845 will continue deplete samples from buffer while 8x930Ax/Hx waits next packet data.
AP-648
SOF1
SOF2 Samples, Packet
SOF3
Dummy Delta)
Samples Samples Delta)
Samples Samples
A4444-01
Figure 8x930Ax/Hx AD1845 Offset
solution this offset arrival frame emptying AD1845 buffer. This accomplished outputting dummy samples start isochronous transfer. Figure above. When isochronous transfer first started, samples worth dummy data sent codec bytes). This will delay consumption real audio data. arrival next frame will occur when codec's buffer half empty instead completely empty. Additional stewardship will necessary. Phase mismatch will still exist samples will have padded dropped. this, system designer will have determine point time when last sample should transmitted codec. This called point delta around point defined. timer count used roughly determine amount time that elapsed since SOF. loop variable hasn't reached RXCNT before timer count (count delta), then sample needs dropped. This keeps offset centered samples. Likewise, loop variable reaches RXCNT before timer value (count delta), then codec running fast requiring addition extra sample. Controlling offset also buys system designer some time handling interrupts. While 8x930Ax/Hx attending data packet, codec coasting last samples buffer.
Conclusion
conclude, playback digital audio data many advantages. quality sound delivered user improved while maintaining cost effectiveness ease use. variety audio codecs numerous integrated features 8x930Ax/Hx controller make well suited codec interfacing. Additionally, transmission audio data well within capabilities protocol 8x930Ax/Hx controller, allowing future development.
References
8x930Ax, 8x930Hx Microcontroller User's Manual order number: 272949-001.
AP-648
Firmware Template Communication Between 8x930Ax/Hx Audio Codec
purpose this template guide user developing communication code between 8x930Ax/Hx AD1845. Intel assumes liability whatsoever this template. Table below indicates example wire between 8x930Hx audio codec. Please refer Section 10.0, Schematics more details Table Sample Wire Between 8x930Hx Audio Codec Codec Data PDAK# PDRQ ADDR RESET# P3.6(WR#) P3.7 PSEN# Ground P1.0(T2) P1.3(CEX0) ADDR ADDR P1.1 (T2EX) Tied codec with timed necessary delay required power tied P1.5(CEX2) 8x930Hx 8x930Hx
PWRDWN# CDACK#
template been divided into three portions: Initialization Start Frame (SOF) CODEC Request
Sample subroutines provided Section below.
8.1.1
Firmware Guideline Initialize
8x930Hx powers 8x930Ax/Hx evaluation board initializes. positive edge triggered interrupts CEX0 interrupt priority level above interrupt
Assume 8x930Hx PAGE-MODE memory access. There additional state inserted into memory access. 8x930Hx strobe lengthened state length. This allowing sync with codec's read write cycle.
AP-648
Initialize codec with 8x930Hx Resynch subroutine used power MODE2 Indir_cntrl_reg_write 01001100B, 11011010B Crystal Clock select arbitrary frequency, other possibilities are: 24.576, 1431818, indir_cntrl_reg_write 01011101B, 01100000B Resynch subroutine used again codec resets itself codec 16-bit 44.1 sample rate Indir_cntrl_reg_write 01001000B, 01011011B codec transfers (write directly codec FIFO), Single channel DMA, Playback DISABLED (i.e. wait till data available from host) Indir_cntrl_reg_write 01001001B, 00000100B Clear (note: there will samples muted output now) Cntrl_reg_write 00000000B
8.1.2
Four possible situations have been considered: There audio data FIFO (check RXCON RXFFRC) currently playback codec Transfer audio data FIFO buffer chip memory byte count from RXCNT Data goes from RXDAT buffer byte time When transfer complete update buffer's data pointer Turn playback codec Indir_Cntrl_reg_write 00001001B, 00000101B above write enables codec transfer(write directly codec FIFO), Single Channel DMA, Playback ENABLED global variable "HubSamples" samples buffer i.e. RXCNT global variable "playback" TRUE There audio data FIFO playback occurring Transfer audio data FIFO buffer chip memory Update "HubSamples" Update data pointer buffer There audio data FIFO playback codec nothing There audio data FIFO playback occurring
AP-648
"HubSamples" then turn playback codec global variable "playback" FALSE This means that while there data FIFO there still data needed playback audio buffer "turn playback codec off" NOTE: codec cannot request data (i.e. PDRQ when trying write codec registers. Drive PDAK# before beginning write codec Write four bytes "dummy" sample (i.e. zeros) codec Drive PDAK# high after write cycle ended Indir_Cntrl_write_reg 00001001B, 00000100B (DMAtransfers, DISABLED)
SingleChannelDMA,
Playback
8.1.3
Codec Request
Interrupt comes from PCA: "HubSamples" then service request with "real" data Drive PDAK# before beginning write codec Write four bytes codec from buffer Drive PDAK# high after write Update data pointer buffer Decrement "HubSamples" Otherwise, "HubSamples" then nothing codec make feature replay last sample.
Sample Subroutines
cntrl_reg_read ADDRESS, TARGET REG{ Reads from directly addressable registers codec before memory read codec ADDRESS transmitted codec over P1.1 held stable until after read strobe returns high. This fulfills timing requirements codec. NOTE: Only first registers four direct registers AD1845 relevant this application. Pins conserved 8x930Hx tying upper ADDR1:0 codec ground. TARGET simply byte register where data will stored.
cntrl_reg_write ADDRESS, DATA{ Writes directly addressable registers codec before memory write codec bits ADDRESS transmitted codec over P1.2:1 held stable until after write strobe returns high. This fulfills timing requirements codec. resynch{ Waits codec reset itself
AP-648
using function cntrl_reg_read poll control register codec until reads indir_cntrl_reg_write ADDRESS, DATA{ Writes indirectly addressable registers codec. cntrl_reg_write ADDRESS indirect register write cntrl_reg_write DATA upper direct register address always
Sample Firmware Subroutines Communication Between 8x930Ax/Hx Audio Codec
This sample code meant assist user developing their communication code between 8x930Ax/Hx AD1845. This used only reference been thoroughly tested. Intel assumes liability whatsover this code.
Sample Subroutine code
InitilizeEmbeddedFunction: Call Call Call Call INIT_CODEC setb setb SOFIE IEN1.1 Enable Interrupts Enable Function INIT_VARIABLES SV_ResetRoutine INIT_FUNCTION_EP0 ;Initialize space required
Initialize subsystem lcall INIT_USERS_CODE
Call Users code initialization
;Sub Routine Name: INIT_CODEC ;Brief Description: Initializes codec interface 8x930Ax/Hx ;Registers Saved: Standard pushing poping registers used INIT_CODEC: directly related codec initialize global variables hubsamples playback Also configures receive data request interrupts from thecodec push WR0,#0000h playback,WR0 hubsamples,WR0 CCAPM0,#21h CEX0 IPH1,#01h Ensures that request Bumps interupt from level level priority. higher priority than Codec data Positive edge triger enable interrupt request
Resynch come ;IndirectCodecControlRegWrite: MACRO Addr, IndirectCodecControlRegWrite 01001100b,11011010b IndirectCodecControlRegWrite 01011101b,01100000b codec Resynch 44.1 IndirectCodecControlRegWrite 01001000b,01011011b IndirectCodecControlRegWrite 01001001b,00000100b CodecControlRegWrite00 00000000b COMMENT *-Function name SOF_ISR Brief Description Service SOF_ISR Interrupt This routine simply displays upper three bytes lower three bits LEDs LED_PORT does affect other LEDS. Very useful determining when function receivingSOFs service routine also transfers audio data buffer codec Regs preserved Reg. saved SCOPE resynch again allow reset codec 16-bit sample rate Codec transfers Single Channel transfers Playback DISABLED Clear make sure that codec reset MODE2 Crystal Clock
Sample Subroutine code
SOF_ISR: EmbeddedFunctionSofRoutine: ASOF, ExitSofIsr Check. call SV_SOF_ROUTINE ASOF push FUB_BOARD DISABLED LED_PORT #0F8h LED_PORT, SOFH #07h LED_PORT, ENDIF ExitSofIsr: HUB. this ASOF set, could
COMMENT *-SOF Service Routine Codec push Save registers push A,RXCON move RXCON RXFFRC A,#10h mask everything except RXFFRC dat_yes (data fifo) A,playback (playback FALSE) A,#0FFh then nothing) WR2,hubsamples elseif (hubsamples WR2,#0000h i.e. there samples buffer then nothing) lcall STOP_PLAY_BACK else (turn codec) playback,#0000h playback FALSE sjmp we're done! dat_yes: A,playback A,#0FFh turn_on buffer) lcall XFER_DATA sjmp turn_on: lcall XFER_DATA lcall START_PLAY_BACK sjmp bye: COMMENT *-Function name START_PLAY_BACK Brief Description global playback function TRUE codec playback audio data Regs preserved START_PLAY_BACK: playback,#0FFh playback TRUE IndirectCodecControlRegWrite 00001001B,00000101B above sequence ENABLES playback codec ;******* START_PLAY_BACK ******** COMMENT *-Function name STOP_PLAY_BACK Brief Description Playback codec disabled first satisfying codec's data then turning
(playback FALSE) then (turn codec transfer data
else (only transfer data buffer) we're done
we're done
Sample Subroutine code
playback off. Regs preserved preserved STOP_PLAY_BACK: push save regs WR4,#0000h move codec addr into double word WR6,#0000h drop PDAK# @DR4,WR4 move "dummy" samples codec @DR4,WR4 i.e. zeros setb drive PDAK# HIGH IndirectCodecControlRegWrite 00001001B,00000100B above sequence DISABLES playback codec ;******* STOP_PLAY_BACK ******** COMMENT *-Function name XFER_DATA Brief Description Transfer ISOC data from fifo buffer. process hubsamples updated. Regs preserved WR2, WR4, XFER_DATA: push push push move_it: WR2,#0000h WR2,RXCNTL hubsamples,WR2 WR4,audio_buf save registers
zero register divide byte count sample count write back value hubsamples initialize audio buffer pointer
begin loop WR2,#0000h (sample count see_ya then done) R6,RXDAT begin moving sample buffer @WR4,R6 WR4,#01d R6,RXDAT audio data from fifo @WR4,R6 transfer audio data buffer WR4,#01d increment buffer pointer R6,RXDAT @WR4,R6 WR4,#01d R6,RXDAT @WR4,R6 move sample buffer WR4,#01d WR2,#01d sample down (WR2) sjmp move_it loop audio_data_ptr,audio_buf reset pointer beginning buffer data see_ya: ;******** XFER_DATA ******** COMMENT *-Function name CODEC_ISR Brief Description Services Codec's request data sample time Regs preserved WR0,R2-5,WR6,DR12 CODEC_ISR:
Sample Subroutine code
push push push push push push push
DR12
;preserve register values
WR0,hubsamples WR0,#0000h finis
(hubsamples then exit i.e. there data codec repeat last sample
data entire sample R2,audio_data_ptr left byte R3,audio_data_ptr left high byte R4,audio_data_ptr right byte R5,audio_data_ptr right high byte WR12,#0000h WR14,#0000h load address codec into DR12 P1.0 drop PDAK# @DR12,R2 left byte codec @DR12,R3 left high byte codec @DR12,R4 right byte codec @DR12,R5 right high byte codec setb P1.0 drive PDAK# back high finis: DR12 ********* CODEC_ISR ********** WR0,#1D hubsamples,WR0 WR6,audio_data_ptr WR6,#04d audio_data_ptr,WR6 CCON,#00h decrement hubsamples update hubsamples increment pointer next sample clear Compare/Capture Flag CCON.0
10.0
Schematic
DGND DGND P1:2 AD1845 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA(7:0) 74ACT373 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 74ACT373 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P1.0 P1.1 P1.2 P1.3 P1.5 P1.7 20pF DGND 74HC32 7404 7404 74HC32 Size DGND Drawn 47uH 7404 DGND AGND DGND 47uH 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 74HC32 0.1uF AGND 10uF AVCC 7404 AGND AGND 74HC32 PSENNOT DGND DGND VREF_2_25V P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 AGND P2.(0:7)
Analog Devices SOCKET68 I265428
R_LINE R_MIC L_MIC L_LINE L_FILT VREF VREF_F GNDA GNDA L_AUX2 L_AUX1 L_OUT R_OUT R_AUX1 R_AUX2
AGND
8x930Ax/Hx evaluation board
74HC04
AGND
20pF
74HC04
P3.6
Intel Corporation Peripheral Controllers Group 5000 Chandler Blvd. Chandler, 85226
CODEC Board
CAGE Code Date Thursday, September 1997 Sheet
P1:1 P1.0 P1:3 P1:5
ADR1 GNDD DATA0 DATA1 DATA2 DATA3 GNDD DATA4 DATA5 DATA6 DATA7 GNDD DBEN# DBDIR
ADR0 CDAK# CDRQ PDAK# PDRQ GNDD XTAL1I XTAL1O GNDD XTAL2I XTAL2O PWRDWN# RESET# GNDD R_FILT
XCTL1 XCTLO GNDD M_OUT M_IN GNDD
LM386
8.86K
0.05uF 8.86K
470uF
LM386
AGND
0.05uF 8.86K AGND 8.86K
470uF
AGND

December, 1997 Order Number: 292206-003 Information this doc

Top Searches for this datasheet

Other recent searches