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Protection Without Relays Using Intel® Protection Interface Units (Intel® PIUs) Intel® LXT3008 T1/E1/J1
Order Number: 249532-002
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Copyright Intel Corporation, 2001 *Third-party brands names property their respective owners.
Protection without Relays
Contents
Abstract. Introduction System Architecture Protection Matrix Intel® Protection Interface Unit (Intel® PIU).10 Line Card/Protection Matrix Interface.11 Protection Matrix/Protection Card Interface Matrix Control Matrix Power Supply
Implementation Details
Summary
Figures
Relay Based Protection- Transmit Path Relay Based Protection- Receive Path System Architecture Protection Matrix Protection Switching, Transmit Path Protection Switching, Receive Path Line Card Protection Matrix Interface, Receive Direction.11 Line card Protection Matrix Interface, Transmit Direction Power Interface Protection Card Protection Matrix Control.14 Space Comparison.16
Tables
LXT3008 Tri-State Control Relays PIU.15
Protection without Relays
Revision History
Revision -002 Date 4/5/2001 Description Title change graphics improvements
Protection Without Relays
Abstract
This application note shows implement protection architecture without relays T1/E1/J1 applications. starts presenting traditional, relay based implementation discussing disadvantages. section "relay-less" system architecture based Intel® Protection Interface Unit (Intel® PIU) introduced. following section explains implementation details from technical perspective. Finally, section summarizes information presented previous sections lists advantages disadvantages proposed solution over traditional relay-based implementation.
Introduction
today's high speed internet economy, reliability critical network infrastructure elements primary concern. Down time critical communications link cost operator thousands dollars minute. address this reliability concern, telecom equipment manufacturers commonly include redundancy protection their systems. protection scheme, there protection board each active board system. This approach offers highest reliability level obviously expensive. more common approach protection scheme where single protection board replace primary boards. Traditionally, T1/E1/J1 protection been implemented using electromechanical relays. Figures show simplified diagram such implementation. independent protection card replace primary line cards. relay based protection matrix access input output signals. control board (not shown these diagrams) constantly monitors primary boards. When failure detected boards, command sent protection matrix re-route corresponding signals protection board. These simplified diagrams show additional control circuitry used decide board switch. They also include circuitry needed drive relay coils.
Figure Relay Based Protection- Transmit Path
PROTECTION MATRIX
Protection Without Relays
Figure Relay Based Protection- Receive Path
PROTECTION MATRIX
relay implementation very simple from architectural standpoint unfortunately, there many disadvantages
Parts count
example, let's suppose each line card T1/E1/J1 ports (Transmit Receive) that system includes protection board active boards (7+1 protection). Assuming DPDT (Dual Pole Double Throw) relay each TIP/RING pair, this results total 7*8*2 relays.
Space
Typical size miniature DPDT signal relay With total relays, will have much space left additional circuitry protection matrix.
Power Consumption
With T1/E1/J1 ports board will need activate total DPDT relays case failure. Even efficient DPDT relays require about each coil activation. That accounts total power consumption 2.26
Switching Speed
Typical time relays range plus bounce time approximately 0.5ms. With link running 1.544 Mbps, that time corresponds over 3000 bits lost information. This more than enough trigger alarm only takes contiguous periods lost signal according ANSI T1.231). This problem accentuated with higher speed links running 2.048 Mbps. concluded from discussion above, there number issues with relay based protection schemes. following paragraphs will introduce solution based Intel® that will address these problems.
Protection Without Relays
System Architecture
Figure detailed view possible system architecture with protection.
Figure System Architecture
Control
SUPERVISORY CARD PROTECTION MATRIX T1/E1 PROTECTION CARD T1/E1 LINE CARD T1/E1 LINE CARD T1/E1 LINE CARD
T1/E1 Protection T1/E1 Primary
LINE TRANSITION MODULE
System In/Out
With this architecture, there primary T1/E1/J1 running across backplane. primary carries analog TIP/RING signals from each line cards. protection matrix connects these signals normally high impedance, non-intrusive state. There connecting protection switching matrix protection board. Whenever line cards deemed faulty supervisory card, output drivers switched high impedance state. this point, protection matrix replaces missing signal primary E1/J1 with signal from protection card. common line transition module contains isolation transformers, line side protection receive side termination. core this system architecture protection matrix implementation. have seen previous section, this matrix traditionally implemented using electromechanical relays. proposed architecture however, tri-state drivers high impedance receivers combined within protection matrix achieve same objective. following section looks protection matrix implementation further detail.
Protection Matrix
protection matrix Figure must able replace T1/E1/J1 pair from primary line cards with T1/E1/J1 pair from protection card. receive direction (input system) matrix must corresponding signal primary reproduce
Protection Without Relays
input protection card. transmit direction (output from system) matrix must replace missing T1/E1/J1 signal with signal coming from protection card. possible implementation that meets these requirements shown Figure Figure Protection Matrix
Control PROTECTION MATRIX
T1/E1 Protection T1/E1 Primary
building block this protection matrix Intel PIU, simplified T1/E1/J1 multiplexing element (see Figure Each contains multiple tri-state drivers high impedance receivers. analog side, these devices interface primary T1/E1/J1 either drive stay non-intrusive, high impedance state. digital side, provides recovered clock data also accepts transmit input clock data. receive output clock data signals tri-stated. Therefore, multiple elements connected parallel shown Figure additional interfaces protection card through T1/E1/J1 protection bus. Figure Figure illustrate backup data paths case failure line cards (card this example). transmit path, receives signal from protection board. recovered clock data distributed other PIUs. Since PIUs' drivers with exception will tri-stated, transmit signal from protection board effectively routed T1/E1/J1 primary (see Figure receive path, recovers input signal from primary delivers connecting protection card. remaining PIUs tri-stated digital output side there contention. Figure
Protection Without Relays
Figure Protection Switching, Transmit Path
Control PROTECTION MATRIX
T1/E1 Protection T1/E1 Primary
Figure Protection Switching, Receive Path
Control PROTECTION MATRIX
T1/E1 Protection T1/E1 Primary
Protection Without Relays
Intel® Protection Interface Unit (Intel® PIU)
Figure
RNEG
RPOS
TNEG
TPOS
RCLK
TCLK
LEN0 CLOCK DATA RECOVERY PULSE SHAPER LEN1 LEN2
REFCLK RXTRST
TXTRST
Intel available port, 15x15 PBGA package. Intel PIUs controlled hardware serial host mode. reference clock (1.544 2.048 required clock recovery. single reference clock feed PIUs protection matrix. Both output analog drivers receive clock data digital buffers tri-stated. PIUs also include three line build-out inputs (LEN0-2) applications.
RRING
TRING
RTIP
TTIP
Protection Without Relays
Implementation Details
following sub-sections address specific implementation details from technical perspective. start describing electrical interface from line cards protection matrix from matrix protection card. Design topics regarding protection matrix implementation also covered this section. following discussion targeted short-haul applications using Intel LXT38x family T1/E1/J1 LIUs conjunction with Intel PIU.
Line Card/Protection Matrix Interface
Application note 249464, "LXT380/1/4/6/8 Redundancy Applications, T1/E1/J1 Intel® Hitless Protection Switching (Intel® HPS) Without Relays" discusses implementation details redundancy. Since Intel transmit receive circuitry identical LXT38x family transceivers, same interface proposed this application note used connecting line cards protection matrix redundancy applications. Figure Figure show interface proposed above referenced application note. Only channel represented simplicity. reader referred above referenced application note further implementation details such component values performance test results.
Figure Line Card Protection Matrix Interface, Receive Direction
PRIMARY BOARD LINE CARD
RTIP RRING LXT384_Rx 0.47uF 0.47uF 0.22uF
LINE INTERFACE CARD
LINE TRANSITION MODULE
LXT384
BACKPLANE
BACKPLANE
RTIP
RRING
BACKUP BOARD MATRIX
RTIP RRING LXT384_Rx 0.22uF
0.47uF
0.47uF
LXT3008 LXT384 TE-REX
Protection Without Relays
Figure Line card Protection Matrix Interface, Transmit Direction
PRIMARY BOARD LINE CARD
TVCC
LINE INTERFACE CARD LINE TRANSITION
MODULE
TTIP
LXT384
TRING LXT384_Tx 0.47uF 0.47uF
BACKPLANE BACKPLANE
TTIP
TRING
BACKUP BOARD
MATRIX
TVCC TTIP
0.47uF
0.47uF
LXT3008 TE-REX LXT384
TRING LXT384_Tx
Because protection matrix adds total data throughput delay, configuration cannot guarantee hitless switching. However, switching time still much faster than that using mechanical relays, significantly reducing data loss.
Protection Matrix/Protection Card Interface
connection between protection matrix protection card Figure internal connection. These signals T1/E1/J1 lines outside this system. Therefore, stringent pulse template return loss specifications apply this internal connection.When protection switching activated, line driver protection card line driver Intel interfacing protection card will launch pulses that travel very short distances through backplane. However, driving these pulses requires power. Fortunately, reduce power significantly increasing terminating impedances line interface. interface proposed Figure tested labs reliable transmission resulted significant power savings. Please refer data sheet additional details power consumption performance. circuit Figure designed interface same capacitive coupled interface used line cards. Therefore, protection card design exactly same line card design.
Protection Without Relays
Figure Power Interface Protection Card
TVCC TTIP 0.47µF PROTECTION CARD 560pF
TVCC TRING
LXT3008
(ONE CHANNEL) RTIP
0.22µF
FROM PROTECTION CARD
RRING
Matrix Control
supervisory card responsible controlling protection switching within matrix. illustrated Figure Figure Intel® corresponding faulty line card must activated while other PIUs tri-stated both digital analog (line) side. input pins control whether analog digital interfaces tri-stated not. Table
Table LXT3008 Tri-State Control
State Active Inactive TXTRST High RXTRST/REFCLK 1.544 2.048 Clock
interfacing protection card (upper right corner Figure Figure should activated whenever there faulty line card. Figure represents possible control circuitry implementation protection matrix. Eight PDWN (Power-Down) inputs determine whether corresponding PIUs active not. 1.544 2.048 reference clock routed series gates. gates ensure that RXTRST/REFCLK inputs when corresponding PDWN Low. When PDWN High, reference clock applied PIU. Since seven PIUs bottom Figure only will active time, PDWN[1,7] control signals also generated from three word decoder. This minimizes number control signals from backplane. Application Note
Protection Without Relays
addition power-down signal, control should also provide line build-out inputs transmitters (LEN[0,2]). Since only will active time, only three lines required. Note: With this hardware mode only implementation, ports within will share same setting. This issue only applications where there line build-out. However, port line build-out required, should with serial HOST mode control. Intel interfacing protection board only required drive short distance between protection matrix protection board. Therefore, only LEN0 LEN1 connected line build-out inputs. LEN[0,1] applications. only applications, should inputs Low. line build-out control required this case. Figure Protection Matrix Control
1.544 2.048
LEN0 LEN1 LEN2 TXTRST REFCLK RXTRST
[0,2]
Control
PDWN [1,8]
Matrix Power Supply
Since reliability protection matrix fundamental architecture, should special attention power supply design. Here guidelines:
Power Supply Protection
power supply should adequately protected against lightning surges EFTs (Electrical Fast Transients). Sidactors devices (Transient Voltage Suppressors) should placed right power supply input, close disturbance source. Telecom systems required survive standardized surge testing performed according international standards such 61000-4-5.
Fuse Protection
should also consider including protection fuse power supply input. there severe malfunction matrix such latch-up, fuse will power-down matrix preventing from interfering with other circuits. Note that powered down matrix board will interfere with flow traffic provided tri-state pins asserted.
LEN0 LEN1 LEN2
LEN0 LEN0 LEN1 LEN1 LEN2 LEN2
LEN0 LEN0 LEN1 LEN1 LEN2 LEN2
TXTRST
TXTRST TXTRST
TXTRST TXTRST
REFCLK RXTRST
REFCLK RXTRST REFCLK RXTRST
REFCLK RXTRST
REFCLK RXTRST
Protection Without Relays
Noise Filtering
should follow common power supply noise reduction techniques matrix design. Power inputs should filtered through combination ferrite beads decoupling capacitors. will find additional information that applies design including layout guidelines recommended part numbers LXT384 Design Assistant http://developer.intel.com.
Summary
demonstrated previous sections, possible implement T1/E1/J1, redundancy protection without relays. based architectures, offer significant advantages over relay implementation summarized Table
Table Relays
Features
Relay
Power Consumption Size Isolation Switching Speed Switching Noise
High Good Milliseconds High
Small Fair Microseconds
Protection Without Relays
Figure illustrates space savings achieved through implementation. This figure assumes protection matrix with relays. Each line card supports T1/E1/J1 ports. typical Eurocard format board shown. Figure Space Comparison
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