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N+1 Protection Without Relays Using Intel® Protection Interface Units Intel® PIUs - Intel® LXT3008 for T1 / E1 / J1

Order Number: 249532-002

N+1 Protection Without Relays Using Intel® Protection Interface Units (Intel® PIUs) - Intel® LXT3008 for T1 / E1 / J1
Application Note
April 2001
Order Number: 249532-002
Application Note
N+1 Protection without Relays
Contents
1.0 2.0 3.0 Abstract............................................................... 5 Introduction ........................................................... 5 System Architecture ....................................................7 3.1 3.2 4.0 4.1 4.2 4.3 4.4 5.0 Protection Matrix .................................................. 7 The Intel® Protection Interface Unit (Intel® PIU).........................10 Line Card / Protection Matrix Interface.................................11 Protection Matrix / Protection Card Interface ............................12 Matrix Control ...................................................13 Matrix Power Supply ..............................................14
Implementation Details .................................................11
Summary .............................................................15
Figures
1 2 3 4 5 6 7 8 9 10 11 12 Relay Based N+1 Protection- Transmit Path ............................ 5 Relay Based N+1 Protection- Receive Path ............................. 6 System Architecture ............................................... 7 Protection Matrix .................................................. 8 Protection Switching, Transmit Path ................................... 9 Protection Switching, Receive Path ................................... 9 The PIU ........................................................10 Line Card to Protection Matrix Interface, Receive Direction................11 Line card to Protection Matrix Interface, Transmit Direction ................12 Low Power Interface To The Protection Card ...........................13 Protection Matrix Control...........................................14 Space Comparison...............................................16
Tables
1 2 LXT3008 Tri-State Control .........................................13 Relays vs. PIU...................................................15
Application Note
N+1 Protection without Relays
Revision History
Revision -002 Date 4 / 5 / 2001 Description Title change and graphics improvements
Application Note
N+1 Protection Without Relays
Abstract
This application note shows how to implement an N+1 protection architecture without relays for T1 / E1 / J1 applications. It starts by presenting the traditional, relay based implementation and discussing its disadvantages. In section 3, a "relay-less" N+1 system architecture based on Intel® Protection Interface Unit (Intel® PIU) ICs is introduced. The following section explains the implementation details from a technical perspective. Finally, section 5 summarizes the information presented in the previous sections and lists the advantages and disadvantages of the proposed solution over the traditional relay-based implementation.
Introduction
Figure 1. Relay Based N+1 Protection- Transmit Path
PROTECTION MATRIX
Application Note
N+1 Protection Without Relays
Figure 2. Relay Based N+1 Protection- Receive Path
PROTECTION MATRIX
The relay implementation is very simple from an architectural standpoint but unfortunately, there are many disadvantages to it:
· Parts count
· Space
Typical size for a miniature DPDT low signal relay is 15 x 7.5 mm. With a total of 112 relays, you will not have much space left for additional circuitry in the protection matrix.
· Power Consumption
· Switching Speed
Typical set time for relays is in the 2 to 4 ms range plus a bounce time of approximately 0.5ms. With a T1 link running at 1.544 Mbps, that set time corresponds to over 3000 bits of lost information. This is more than enough to trigger a red alarm (it only takes 175 contiguous bit periods of lost signal according to ANSI T1.231). This problem is accentuated with higher speed E1 links running at 2.048 Mbps. As it can be concluded from the discussion above, there are a number of issues with relay based N+1 protection schemes. In the following paragraphs we will introduce a solution based on Intel® PIU ICs that will address these problems.
Application Note
N+1 Protection Without Relays
System Architecture
Figure 3 is a detailed view of a possible system architecture with N+1 protection.
Figure 3. System Architecture
Control Bus TDM Bus
SUPERVISORY CARD 1:N PROTECTION MATRIX T1 / E1 PROTECTION CARD T1 / E1 LINE CARD #1 T1 / E1 LINE CARD #2 T1 / E1 LINE CARD #N
T1 / E1 Protection Bus T1 / E1 Primary Bus
LINE TRANSITION MODULE
System In / Out
With this architecture, there is a primary T1 / E1 / J1 bus running across the backplane. The primary bus carries all the analog TIP / RING signals from each of the N line cards. The protection matrix connects to all these signals and is normally set to a high impedance, non-intrusive state. There is a bus connecting the protection switching matrix to the protection board. Whenever one of the line cards is deemed to be faulty by the supervisory card, its output drivers are switched to a high impedance state. At this point, the protection matrix replaces the missing signal in the primary T1 / E1 / J1 bus with the signal from the protection card. A common line transition module contains all the isolation transformers, line side protection and receive side termination. At the core of this system architecture is the protection matrix implementation. As we have seen in the previous section, this matrix is traditionally implemented using electromechanical relays. In the proposed architecture however, tri-state drivers and high impedance receivers are combined within the protection matrix to achieve the same objective. The following section looks at the protection matrix implementation in further detail.
Protection Matrix
The protection matrix in Figure 3 must be able to replace a T1 / E1 / J1 pair from any of the primary line cards with the T1 / E1 / J1 pair from the protection card. In the receive direction (input to the system) the matrix must tap on the corresponding signal in the primary bus and reproduce it at the
Application Note
N+1 Protection Without Relays
input to the protection card. In the transmit direction (output from the system) the matrix must replace the missing T1 / E1 / J1 signal with the signal coming from the protection card. A possible implementation that meets these requirements is shown in Figure 4. Figure 4. Protection Matrix
Control Bus PROTECTION MATRIX
T1 / E1 Protection Bus T1 / E1 Primary Bus
Application Note
N+1 Protection Without Relays
Figure 5. Protection Switching, Transmit Path
Control Bus PROTECTION MATRIX
T1 / E1 Protection Bus T1 / E1 Primary Bus
Figure 6. Protection Switching, Receive Path
Control Bus PROTECTION MATRIX
T1 / E1 Protection Bus T1 / E1 Primary Bus
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N+1 Protection Without Relays
The Intel® Protection Interface Unit (Intel® PIU)
Figure 7. The PIU
LEN0 CLOCK AND DATA RECOVERY PULSE SHAPER LEN1 LEN2
REFCLK RXTRST
TXTRST
The Intel PIU is available as an 8 port, 15x15 mm, 160 pin PBGA package. Intel PIUs are controlled by hardware or serial host mode. A 1x reference clock (1.544 MHz for T1 and 2.048 MHz for E1) is required for clock recovery. A single reference clock can feed all the PIUs in a protection matrix. Both the output analog drivers and the receive clock and data digital buffers can be tri-stated. PIUs also include three line build-out inputs (LEN0-2) for T1 DSX applications.
RRING
TRING
Application Note
N+1 Protection Without Relays
Implementation Details
The following sub-sections address specific implementation details from a technical perspective. We start by describing the electrical interface from the line cards to the protection matrix and from the matrix to the protection card. Design topics regarding the protection matrix implementation are also covered in this section. The following discussion is targeted to short-haul applications using the Intel LXT38x family of T1 / E1 / J1 LIUs in conjunction with the Intel PIU.
Line Card / Protection Matrix Interface
Application note 249464, "LXT380 / 1 / 4 / 6 / 8 Redundancy Applications, T1 / E1 / J1 Intel® Hitless Protection Switching (Intel® HPS) Without Relays" discusses the implementation details for 1:1 redundancy. Since the Intel PIU transmit and receive circuitry is identical to the LXT38x family of transceivers, the same interface as proposed in this application note can be used for connecting the line cards to the protection matrix in N+1 redundancy applications. Figure 8 and Figure 9 show the interface proposed in the above referenced application note. Only one channel is represented for simplicity. The reader is referred to the above referenced application note for further implementation details such as component values and performance test results.
Figure 8. Line Card to Protection Matrix Interface, Receive Direction
PRIMARY BOARD LINE CARD
LINE INTERFACE CARD
LINE TRANSITION MODULE
LXT384
BACKPLANE
R7 1:2
RTIP TV2
RRING
BACKUP BOARD MATRIX
C5 0.47uF
C6 0.47uF
LXT3008 LXT384 TE-REX
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N+1 Protection Without Relays
Figure 9. Line card to Protection Matrix Interface, Transmit Direction
PRIMARY BOARD LINE CARD
TVCC D2 R10
LINE INTERFACE CARD LINE TRANSITION
MODULE
LXT384
BACKPLANE BACKPLANE
C4 560 pF 1:2
TTIP TV2
TRING
BACKUP BOARD
MATRIX
TVCC D5 45 9.1 D6 R12 TTIP
C5 0.47uF
C6 0.47uF
LXT3008 TE-REX MUX LXT384
Because the protection matrix adds to the total data throughput delay, the N+1 configuration cannot guarantee hitless switching. However, the switching time is still much faster than that of using mechanical relays, significantly reducing data loss.
Protection Matrix / Protection Card Interface
The connection between the protection matrix and the protection card in Figure 3 is an internal connection. These signals do not go to any T1 / E1 / J1 lines outside this system. Therefore, the stringent pulse template and return loss specifications do not apply to this internal connection.When protection switching is activated, the line driver in the protection card and the line driver in the Intel PIU interfacing to the protection card will launch pulses that travel very short distances through the backplane. However, driving these pulses requires power. Fortunately, you can reduce power significantly by increasing the terminating impedances at the PIU line interface. The interface proposed in Figure 10 was tested in our labs for reliable transmission and it resulted in significant power savings. Please refer to the PIU data sheet for additional details on power consumption performance. The circuit in Figure 10 was designed to interface to the same capacitive coupled interface used in the line cards. Therefore, the protection card design can be exactly the same as the line card design.
Application Note
N+1 Protection Without Relays
Figure 10. Low Power Interface To The Protection Card
TVCC D4 TTIP D3 0.47µF TO PROTECTION CARD 560pF 400 1:2
TVCC D2 TRING
LXT3008
(ONE CHANNEL) RTIP
1k 125 0.22µF
1:2 FROM PROTECTION CARD
125 RRING 1k
Matrix Control
The supervisory card is responsible for controlling protection switching within the matrix. As illustrated in Figure 5 and Figure 6, the Intel® PIU corresponding to a faulty line card must be activated while all the other PIUs are tri-stated on both the digital and the analog (line) side. Two input pins to the PIU control whether the analog and the digital interfaces are tri-stated or not. See Table 1.
Table 1. LXT3008 Tri-State Control
PIU State Active Inactive TXTRST High Low RXTRST / REFCLK 1.544 or 2.048 MHz Clock Low
The PIU interfacing to the protection card (upper right corner in Figure 5 and Figure 6) should be activated whenever there is a faulty line card. Figure 11 represents a possible control circuitry implementation for a 7+1 protection matrix. Eight PDWN (Power-Down) inputs determine whether the corresponding PIUs are active or not. A 1.544 MHz or 2.048 MHz reference clock is routed to a series of AND gates. The AND gates ensure that the RXTRST / REFCLK inputs are set Low when the corresponding PDWN pin is Low. When the PDWN pin is High, the reference clock is applied to the PIU. Since of the seven PIUs in the bottom of Figure 11 only one will be active at any time, the PDWN1, 7 control signals can also be generated from a three bit word and a decoder. This minimizes the number of control signals from the backplane. Application Note 13
N+1 Protection Without Relays
In addition to the power-down signal, the control bus should also provide line build-out inputs for the PIU transmitters (LEN0, 2). Since only one PIU will be active at any time, only three lines are required. Note: With this hardware mode only implementation, all the ports within one PIU will share the same LEN setting. This is not an issue for E1 only applications where there is no line build-out. However, if per port line build-out is required, you should use a PIU with a serial HOST mode control. The Intel PIU interfacing to the protection board is only required to drive the short distance between the protection matrix and the protection board. Therefore, only LEN0 and LEN1 are connected to the line build-out inputs. Set LEN0, 1 to 11 for T1 applications. In E1 only applications, you should set all the LEN inputs Low. No line build-out control is required in this case. Figure 11. Protection Matrix Control
1.544 / 2.048 MHz
LEN0 LEN1 LEN2 TXTRST REFCLK / RXTRST
Control Bus
PDWN 1, 8
Matrix Power Supply
Since the reliability of the protection matrix is fundamental in a N+1 architecture, you should pay special attention to its power supply design. Here are a few guidelines:
· Power Supply Protection
The power supply should be adequately protected against lightning surges and EFTs (Electrical Fast Transients). Sidactors or TVS devices (Transient Voltage Suppressors) should be placed right at the power supply input, close to the disturbance source. Telecom systems are required to survive standardized surge testing performed according to international standards such a IEC 61000-4-5.
· Fuse Protection
You should also consider including a protection fuse at the power supply input. If there is a severe malfunction in the matrix such as a latch-up, the fuse will power-down the matrix preventing it from interfering with other circuits. Note that a powered down matrix board will not interfere with the flow of traffic provided the tri-state pins are asserted.
Application Note
LEN0 LEN1 LEN2
LEN0 LEN0 LEN1 LEN1 LEN2 LEN2
TXTRST
TXTRST TXTRST
REFCLK / RXTRST
REFCLK / RXTRST REFCLK / RXTRST
REFCLK / RXTRST
N+1 Protection Without Relays
· Noise Filtering
You should follow common power supply noise reduction techniques in the matrix design. Power inputs should be filtered through a combination of ferrite beads and decoupling capacitors. You will find additional information that applies to a PIU design including layout guidelines and recommended part numbers in the LXT384 Design Assistant at http://developer.intel.com.
Summary
As demonstrated in the previous sections, it is possible to implement T1 / E1 / J1, N+1 redundancy protection without relays. PIU based architectures, offer significant advantages over a relay implementation as summarized in Table 2.
Table 2. Relays vs. PIU
Features Set
Relay
Power Consumption Size Isolation Switching Speed Switching Noise
High Big Good Milliseconds High
Low Small Fair Microseconds Low
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N+1 Protection Without Relays
Figure 12 illustrates the space savings achieved through a PIU implementation. This figure assumes a 7+1 protection matrix with 112 relays. Each line card supports 8 T1 / E1 / J1 ports. A typical 6U Eurocard format board is shown. Figure 12. Space Comparison
RELAY
RELAY RELAY RELAY RELAY RELAY RELAY RELAY RELAY
RELAY
RELAY RELAY RELAY RELAY RELAY RELAY RELAY RELAY
RELAY
RELAY RELAY RELAY RELAY RELAY RELAY RELAY RELAY
RELAY
233 mm
RELAY
RELAY RELAY RELAY RELAY RELAY RELAY RELAY RELAY
160 mm
Application Note