Application Note (AP-388) Revision July 1998 Document Number

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Alert LAN** Design Guide
Application Note (AP-388)
Revision July 1998
Document Number: 703222-002
Revision Date Feb. 1998
Revision
Description First release Replaced Figure "Overview BIOS Support Alert LAN" with updated version Corrected address 0101AAA added paragraph Section 6.0, "System Management (SMB)"
July 1998
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Alert LAN** ASIC contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation P.O. 7641 Prospect 60056-7641 call 1-800-879-4683. Many documents available download from Intel's website http://www.intel.com.
Copyright Intel Corporation, 1997 *Third-party brands names property their respective owners.
Alert result Intel-IBM Advanced Manageability Alliance trademark IBM.
Application Note (AP-388)
Contents
INTRODUCTION HARDWARE REQUIREMENTS.1 82558 B-step (82558B) Fast Ethernet Controller 2.1.1 82558 B-step EEPROM 2.1.2 82558 B-step Clock Output 64x16 EEPROM.2 Environmental Integrated Circuit PIIX4 Equivalent.3 Sticky Latch (optional)
BIOS REQUIREMENTS Hardware Preparation Boot.6 System Programming Watchdog Setup Hang Boot Alert POST Error Reporting Support
COMPONENT PLACEMENT ALERT ASIC EVENT INTERFACE Cover Tamper Environmental System Management Interrupt Board Temperature Interrupt Leash.8 Processor Missing
SYSTEM MANAGEMENT (SMB) SMOOTH CLOCK SWITCHING LOGIC ALERT ASIC SIGNALS.9 Reset Main Power Good System Management Interrupt (SMI) Auxiliary Power Good Main Power Good
10.0 11.0
COMPLIANCE.10 ACPI POWER STATES.11 APPENDIX REFERENCE SCHEMATICS
Application Note (AP-388)
Application Note (AP-388)
Introduction
This application note provides information design specific considerations relevant system designers interested implementing design using Alert LAN** ASIC. Alert ASIC specially designed operate through Intel's 82558's Total Cost Ownership (TCO) Interface. stand alone device requires additional components create functional management solution. following list documents related Alert ASIC obtained through your local Intel sales representative:
Alert ASIC Datasheet Alert ASIC Software Developer's Manual 82558 Total Cost Ownership (TCO) Management Interface Application Note (AP-385) 82558 Fast Ethernet Controller with Integrated Datasheet 82557 C-step 82558 Based Products EEPROM Address Programming Information Application Note (AP-382)
Alert Stepping Information
Hardware Requirements
Alert ASIC stand alone device. requires additional components create functional management solution. possible supporting hardware identified this section.
Note:
82558 B-step Fast Ethernet Controller 64x16 EEPROM Environmental Integrated Circuit (IC) PCI-to-ISA/IDE Xcelerator (PIIX4) Sticky Latch (optional)
Supporting hardware sets will differ from implementation implementation.
82558 B-step (82558B) Fast Ethernet Controller
82558 Fast Ethernet Controller required complete solution. Alert ASIC designed communicate with proprietary interface 82558B. 82558B provides functionality transmit data network calculates adds checksum data from Alert ASIC.
Application Note (AP-388)
Alert LAN** ASIC Design Guide
2.1.1
82558 B-step EEPROM
82558's EEPROM word illustrated Figure
Word
ISOL
ADDR
Figure 82558 B-step EEPROM Word following fields 82558's EEPROM word should enable interface when Alert ASIC present. (Details found 82557C 82558 EEPROM Programming Information Application Note, AP-382.)
2.1.2
Clock Isolation Disable Enable Wake LAN* (WOL) External Clock Enable
82558 B-step Clock Output 2.1.2.1 82558 Clock Signal Quality
output clock full swing with strong driver behind reduce ringing emissions, series resistor should used this line. resistor value should effectively match trace impedance less driver impedance. Another reason series resistor eliminate large undershoots. Large undershoots cause 3126 gate turn momentarily difference between ground voltage undershoot greater than (gate-to-source) threshold voltage 3126.
2.1.2.2
82558 Clock Errata
82558B Clock output signal (CLKOUT) configured output clock signal. This helps reduce design cost when used clock Alert ASIC instead using oscillator. However, there erratum 82558B. CLKOUT clock start from applied power (cold boot) there clocks PCI_CLK input. Alert ASIC works around this relying PIIX4's "power-up cold boot" feature. This ensures that PCI_CLK will enabled. Therefore, ASIC defaults PCI_CLK (expecting power-up) therefore provides 82558B with necessary clocks prevent start CLKOUT condition.
64x16 EEPROM
Alert ASIC designed 64x16 EEPROM configure default settings upon reset hard transitions. EEPROM present contains invalid checksum, Alert ASIC will default component default settings defined Alert ASIC Datasheet. Note: 82558 requires EEPROM configuration settings; this separate EEPROM from 82558B's EEPROM.
Application Note (AP-388)
Alert LAN** ASIC Design Guide
Environmental Integrated Circuit
environmental that capable monitoring voltage, temperature, cover tamper used part system management solution. However, only input exists Alert ASIC.
PIIX4 Equivalent
PIIX4 device provides master interface that enables system BIOS communicate with Alert ASIC. PIIX4 also provides PWR_GOOD PCI_RST# signals that propagate Alert ASIC. Note: PIIX4 ability force system into power state without prior indication software. Thus, Alert ASIC monitors PWR_GOOD hard transition. PIIX4 power-up feature disabled external hardware, cause initialization problem with Alert ASIC since expects PCI_CLK power-up. responsibility designer ensure that Alert ASIC 82558B least four clocks during hardware reset least four clocks after hardware reset overcome this problem. Contact your local Intel representative more suggestions work around this problem.
Sticky Latch (optional)
Sticky latches useful detecting events that occur when system state (completely off), such Cover Tamper input. latch battery-backed that Alert ASIC will become aware that event occurred when powered-up. sticky latch also provides ability reset driving opposite polarity latch bidirectional pin, EVENT_1, Alert ASIC. EVENT_1 Alert ASIC ability clear sticky latch. this feature enabled, executed clearing STA_EV1 Event Status register. result least output pulse opposite polarity EVENT_1 pin. example sticky latch circuit illustrated Figure
SAMPLE/CLEAR
5VSB
Figure Sticky Latch Example Note: This solution also prohibits ASIC cover tamper clear mechanism (the ASIC configured output clear pulse). environmental should clear sticky latch.
Application Note (AP-388)
Alert LAN** ASIC Design Guide
BIOS Requirements
Alert ASIC support POST failure reporting requires changes client system's BIOS. BIOS software performs four important tasks within Alert Client while client preboot state. BIOS software disables (masks) generation hardware alert messages heartbeat messages Alert ASIC. This task important because ensures that Alert ASIC's transmission activity will interfere with later BIOS initialization activities. BIOS software programs guards against corruption System field Alert ASIC's EEPROM. BIOS software configures Alert ASIC generate watchdog alert message client system hangs during POST boot. client BIOS software provides Alert ASIC POST error capability. When BIOS discovers fatal error during POST, BIOS generates software event message Alert Proxy Service (APS).
Application Note (AP-388)
Alert LAN** ASIC Design Guide
figure below shows high level flow steps Alert enabled BIOS follows during preboot state.
Start Pre-POST
System Valid
exists
Update System Global Disable
Init registers
exists
Disable Watchdog
Disable transmits
Enabled
EEPROM read after reset
Enable Transmit
EEPROM Checksum
Send System Awake
User Setup Enables
Send Heartbeat Start
Exit Pre-POST
Figure Overview BIOS Support Alert More detailed information regarding BIOS requirements described Alert ASIC Software Developer's Manual.
Application Note (AP-388)
Alert LAN** ASIC Design Guide
Hardware Preparation Boot
Prior Boot, Alert enabled BIOS must disable generation heartbeat messages hardware alert messages. BIOS should disable heartbeat message generation disabling Alert ASIC Heartbeat Timer. BIOS should disable generation hardware alert messages well masking hardware events.
System Programming
Alert enabled BIOS responsible programming maintaining System Alert EEPROM. Alert EEPROM described detail Alert ASIC EEPROM Application Note, AP-387. System given system constant value programmed into BIOS code. powerup, BIOS should compare current System value contained offset Alert EEPROM against expected value BIOS code. System value EEPROM differs from expected value, BIOS should write expected System value into Alert EEPROM Global Disable Bit.
Watchdog Setup Hang Boot Alert
Alert enabled BIOS should configure Alert ASIC generate watchdog event BIOS hangs during POST hangs during boot. accomplish this, BIOS must perform tasks. BIOS must unmask generation watchdog events writing value into Alert Event Mask register. BIOS must program Alert Watchdog Status Byte register Alert Watchdog Timer. value programmed into Watchdog Timer should allow enough time BIOS POST complete boot. BIOS optionally support POST check-pointing feature. This feature enables identify where system boot sequence hang occurred. BIOS enables this feature updating Alert Watchdog Status Byte beginning individual POST test again just prior boot. following table describes defined Watchdog Status Byte register values. Table Defined Watchdog Status Values
Value Watchdog Message Power HANG POST Checkpoints Boot
Application Note (AP-388)
Alert LAN** ASIC Design Guide
POST Error Reporting Support
Alert enabled BIOS should generate Alert software event message fatal POST Error. First, BIOS should write POST failure code into Alert Software Status Byte registers big-endian byte ordering with byte Software Status Byte high byte Software Status Byte Next, BIOS should software event Alert Event Status register. software event message will inform POST failure provide POST Error Code system administrator.
Component Placement
Alert ASIC should placed close possible 82558B, clock switching logic, EEPROM. recommended distance between each these components less than inch.
Alert ASIC Event Interface
Alert ASIC designed provide capability generating alerts fully operational power states five hardware events occur. Alert ASIC implements following alerts:
Cover Tamper Environmental System Management Interrupt (SMI) Board Temperature Interrupt (BTI) Thermal Leash Processor Missing
Cover Tamper
Cover Tamper used indicate that cover been opened typically wired batterybacked sticky latch. process limitations Alert ASIC, impedance path exists between inputs when ASIC powered. Since sticky latch battery-backed, this result battery drainage when system unplugged power). Details described Alert Stepping Information document. This normally active high input signal Alert ASIC.
Environmental System Management Interrupt
line environmental integrated circuit (IC) should connected ASIC. environmental typically used monitor motherboard voltages fans. current implementation Alert ASIC does have capability integrate
Application Note (AP-388)
Alert LAN** ASIC Design Guide
environmental Therefore, designs based only event interest (such voltage sense) determine cause Environmental SMI. This normally level active input signal Alert ASIC.
Board Temperature Interrupt
input ASIC delivered from thermal sensor close system's microprocessor(s). This normally active high input signal Alert ASIC.
Leash
Leash input ASIC simply link indication. should connected 82558 number 162, LILED#. This normally active high input signal Alert ASIC.
Processor Missing
This input ASIC intended indicate when more system processors missing depends processor used. example Slot Occupied (SLOTOCC#) signal Pentium processor. This normally active high input signal Alert ASIC.
System Management (SMB)
Alert ASIC provides slave interface used configuring ASIC. Pull-up resistors required both signals. resistor values dictated described System Management (SMB) Specification. ASIC address 0101XXXb, where defined pull-up pull-down resistors SMB_A[2:0] (also used Data Bus[2:0] signals) pins. minimum value pull-up resistor required overcome internal pull-down resistance 82558 B-step device. Pulldown resistor values larger (for example, address lines that required read should pulled-up externally with relatively strong pull-up resistors (for example, This necessary because pull-down resistors same lines 82558 B-step active, depending reset sequence between PCI_RST# AUX_GOOD, cancel effect internal Alert pull-up resistors. Note: interface ASIC supports Transistor-to-Transistor Logic (TTL) level inputs. Thus, bus, conversion required. Since open drain (the pull-up resistors provide logic high level), ASIC drive
Application Note (AP-388)
Alert LAN** ASIC Design Guide
Smooth Clock Switching Logic
82558B requires smooth clock switching logic operate with flexible filters mode. This logic required avoid glitches that potentially alter operational sequence micromachine such that will execute operations destructive flexible filter when switching between clock 82558 external clock output. smooth clock switching logic ASIC operates with clock domains, Clock signal (PCI_CLK) 82558 external clock output signal (CLKOUT). Each domain several memory cells. switch from domain other, clocks from both domains required. Attention should given signals from PIIX4 clock generation which might stop PCI_CLK before power transition (for example, PCI_STOP#). Note: Alert ASIC defaults PCI_CLK assumes that PIIX4 will force power-up main supply, thus supplying PCI_CLK. This implemented overcome CLKOUT start-up anomaly 82558B. More information CLKOUT anomaly found 82558 Stepping Information document. routing this logic should receive high priority since very time sensitive. Traces should kept minimum length. 3126 part should used since circuit modeled 3126. Additionally, will also work with 3126.
Alert ASIC Signals
Reset Main Power Good
Alert ASIC blocks Reset (PCI_RST#) signal from 82558B when Main Power Good (PWR_GOOD) signal low. This required prevent 82558B from resetting during normal power-down situations. Otherwise, 82558B will lose device state (return lose programmed flexible filters. PCI_RST# typically asserted PIIX4 during power-down. PIIX4 looks Power (PWROK) signal that transitioning then asserts PCI_RST#. PWOK PWR_GOOD should same signal derived from same source with identical timing). This allows ASIC PWR_GOOD same time PIIX4 does block PCI_RST# that PIIX4 about drive low.
System Management Interrupt (SMI)
ASIC provides SMI# signal indication events local CPU. Since these interrupts happen during power states, this interrupt should connected used) input PIIX4 PIIX6) which provides SMI, SCI, Resume capabilities. However, current software stack does interrupts.
Application Note (AP-388)
Alert LAN** ASIC Design Guide
Auxiliary Power Good Main Power Good
Typically, Auxiliary Power Good (AUX_GOOD) signal expected transition from high before Main Power Good (PWR_GOOD) signal transitions from high. However, this restriction Alert ASIC. Note: AUX_GOOD signal works hardware reset signal (active low) ASIC. This signal must quick transition signal driven sound logic. PWR_GOOD signal Schmitt-triggered input ASIC. does require quick transition signal; however, recommended since rise fall time signals susceptible offsets from crosstalk other signals.
Compliance
nature Alert solution with 82558B, special clocking required PCI_CLK signal. loading characteristics PCI_CLK follows:
PCI_CLK Connection Alert ASIC 82558 B-step 3126 Analog Switch Stray 3126/82558B Traces 12.0 Units
maximum minimum calculation exceeds maximum allowed specification pF). Several methods implemented compensate this:
Reduce overall capacitance reducing trace length PCI_CLK signal
3126/82558B, which reduces trace capacitance
separate PCI_CLK trace Alert ASIC reduce total capacitance
3126/82558B trace Note: loading Alert ASIC does meet minimum capacitance However, Alert ASIC does have access does require close timing reference PCI_CLK. minimum, following PCI_CLK characteristics should met:
Verify that clock skew between PCI_CLK traces maximum nanoseconds. worst case timing (11ns) met, Alert ASIC must have zero
negative skew PCI_CLK relation PCI_CLK seen 82558B. other words, PCI_CLK should arrive Alert ASIC 82558B same time slightly faster Alert ASIC (but slower). This unlikely concern since this only necessary worst case timing required, Alert ASIC worst case process, temperature, voltage. However, mentioned this document completeness.
Application Note (AP-388)
Alert LAN** ASIC Design Guide
10.0
ACPI Power States
Alert ASIC uses PWR_GOOD signal indication whether switch between PCI_CLK CLKOUT 82558B clock source. 82558B requires clock source function mode that ASIC uses. also requires clock support flexible filtering. However, state (which implies device state) implements stopped clock with power still applied bus. This indicates that 82558B would have clock perform flexible filtering since ASIC will still select PCI_CLK (PWR_GOOD still valid). This scenario that covered implementation since Alert solution targeted managed desktops. state little desktop model unlikely implemented.
11.0
Appendix Reference Schematics
following pages contain reference schematics 82558B/Alert ASIC design.
Application Note (AP-388)
Alert LAN* Reference Schematics
SHEET 82558
82555.SCH
SHEET LM79 Interface
LM79.SCH
SHEET Asic related logic
AP_LOGIC.SCH
NOTES: These generic schematics intended used reference only. references should interpreted standby supply unless otherwise noted. references should interpreted digital ground. This design assumes PIIX4 used Master. This design assumes that PIIX4 forces full power-on power-on. This design assumes that Cover Tamper sticky latch cleared LMxx. these reference schematics along with Alert LAN* datasheet.
SHEET Power Detect Reset
PHY_WOL.SCH
SHEET Bypass Caps Testpoints
CAP.SCH
Title Size Date: File:
Alert LAN* Reference Schematics
Number
Alert LAN*
Sheet Drawn
Revision
23-Jan-1998 A:\AP_EVAL.PRJ
AD[31:0] AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# REQ# GNT# PCLK INTA# RST# FRAME# TRDY# IRDY# STOP# IDSEL DEVSEL# PERR# SERR# ALTRST# PME# TEST EXT_CLK TPE_DATA
82558B
202285-042 202285-042 641184-001 641184-001 202285-042 SLVTRI RSTOUT ZREF LISTAT ISOLATE# LILED ACTLED SPEEDLED FD3/PHY_SA FD2/EEDI FD1/EEDO FD0/EESK FCS# FOE# FWE# EECS VREF RBIAS10 RBIAS100 201645-073 ZREF LISTAT ISOLATE# LILED ACTLED SPEEDLED FA[7.0] FD2/EEDI FD1/EEDO FD0/EESK FCS# FOE# FWE# EECS U2VREF BIAS10 BIAS100 202286-174 202286-182 202285-033 EECS EESK EEDI EEDO values RBIAS resistors require tuning your board implementation. these values starting point. 641184-001
From Interface C/BE#[3:0]
ISOLATE# LILED FA[7:0]
From ASIC, Page
82558RST#
82558RST# PCI_CTRL From Interface
C/BE0# C/BE1# C/BE2# C/BE3# REQ# GNT# INTA# 82558RST# FRAME# TRDY# IRDY# STOP# IDSEL DEVSEL# PERR# SERR# AUX_GOOD PME# TEST 25M_CLK
202285-033
This pull-down LISTAT indicates that 82558 powered auxiliary power source. ASIC Page FD[7:0]
From Page
AUX_GOOD
equivalent already exist Mother board. Page 27pF 108425-006 PME#
201645-073
FL_CTRL
CRYSTAL_25MHZ 201760-011
27pF 108425-006
201645-049 R101 201645-073
109862-201
Main clock source ASIC
A_CLK
A_CLK
202285-015 PCLK
Select lines from ASIC B25_SEL PCI_SEL B25_SEL PCI_SEL
93C46
Title
82558B.SCH
Number
Size QS3126 100625-184 Date: File:
Alert LAN*
Sheet Drawn
Revision
23-Jan-1998 A:\82555.SCH
3.3V
+3.3V
+3.3V
equivalent Environmental shown below example only. Actual connections voltage/temperature/fan monitoring specific each board implementation.
+1.5V +2.5V +3.3V
+12V 4.75K
27.4K
-12V 202286-331
+3.3V
+3.3V
202286-258
HEC-12V +12V +3.3V +2.5V +1.5V FAN1 FAN2 COVER AUX_GOOD
INT# VID4 VID3 VID2 VID1 VID0 NTEST_IN/AOUT LM_SMIA VID4 VID3 VID2 VID1 VID0
201645-073
+2.5V_Sense/+Vccp2 +12VIN +5VIN +3.3VIN +2.5VIN +Vccp1 FAN1 FAN2 CHS_SEC RESET#
LM_SMIA
ASIC, Page
FAN1_TACHOMETER FAN2_TACHOMETER COVER AUX_GOOD
VID[4:0] FAN_CTRL FAN_CTRL
voltage lines Analog output control speed
NTEST_OUT/A0 GNDD
SMB_ADR=58 (HEX) 680050-101
201645-073
201645-073
LM75 Temperture Sensor LM75
Title Size Date: File: 23-Jan-1998 A:\HH2.SCH
HH2.SCH
Number
Alert LAN*
Sheet Drawn
Revision
This Resistor required duplicated Mother Board. 201645-049 R102 201645-049 R103 201645-049
687974-002
AP_ASIC
A_CLK PCI_CTRL PCI_GOOD AUX_GOOD ASIC_COVER LM_SMIA LIDED LIDED TFORCE LM_SMIA ASIC_COVER Cover LM_SMI LANLEASH PROC_MISS EVENT TRDREQ TMARKER TACTIVE EE_CS EE_SK EE_DI EE_DO TSTATUS# TREADY# 201645-049 201645-049 RST# 82558RST# ISOLATE# EE_CS EE_SK EE_DI EE_DO SMB_SCL SMB_SDA SMB_ADR=5C default address (HEX). resistors TDATA2, TDATA1, TDATA0 bits [3:1] this address. SMI_OUT# PCI_RST# 82558_RST# ISOLATE# FWE# FOE# AUX_GOOD AUX_GOOD PCI_GOOD PWR_GOOD PCI_CLK PCI_CLK A_CLK B25_CK B25_SEL PCI_SEL B25_SEL PCI_SEL B25_SEL PCI_SEL Clock stearing logic Page
A_CLK source from Page
PCI_CLK from
Example PWR_GOOD signal from Page
Example AUX_GOOD signal from Page
LM79 equivalent.
82558
TDATA0 TDATA1 TDATA2 TDATA3 TDATA4 TDATA5 TDATA6 TDATA7 FA[7.0]
FA[7.0] 82558 interface page FD[7.0] FL_CRTL
EECS EESK EEDI EEDO
93C46
109862-201
PCI_CTRL 82558RST# ISOLATE#
Signals LM79, Page
SMI_OUT# PROC_M COVER N.O. SW_NO 202285-128 2N7002 603400-001 202285-128 74LV14 676292-101 201645-073 676292-101 74LV14 PME# PME# 74HCT14 108251-181 BATTERY .1uF 108427-050 volts Page WAKE_UP COVER
SIM_OUT# PROC_M
signals will come from PIX4 equavailent.
Interupt Line ASIC (active low) This open drain interrupt shared with other interrupts Thermal sensor near Processor Missing
reason sticky latch being powered battery store fact cover tampered even with power plug removed from
Switch Closes when cover removed. photo detector with active output used place mechanical switch.
Every part that requires these schematics should connected Power Plane, volt Plane, unless otherwise noted.
Connected TACK output FAN. LM79 equivalent device specification.
R106 201645-049
should stuffed they some where else Mother Board.
WAKE_UP
Wake Signal this siganl required, connect PME# signal 82558B interface. Title Size Date: File:
201645-049
ASIC_COVER Cover Tamper Input ASIC isolated N-channel 201645-049 with current through because ASIC sink rails when power completely battery backed-up sticky latch driving positive potential.
AP_LOGIC.SCH
Number Alert LAN* 26-Jan-1998 A:\AP_LOGIC.SCH Sheet Drawn Revision
Analog Differential Signals from 82558B
TPE_DATA
12pF 108425-002 49.9 202286-068 .1uF 108427-050 .1uF 108427-050
49.9 202286-068
TDRD+ RDRDC 10/100 MAGNETICS 677262-001 RXRXC RXMAGRXC MAGCMT
RJ45 623377-001
49.9 202286-068 MAGTERM
49.9 202286-068
.1uF 108427-050 1000pF 108425-063
RP2A 202474-022
RP2B 202474-022
RP2C 202474-022 TERMPLANE
RP2D 202474-022 1500pF 108425-027
CGND
.1uF 108427-050
.1uF 108427-050
108506-002 PCI_GOODX PCI_GOOD PCI_GOOD
This example circuit generate PWR_GOOD signal. NOTE that output edges driven real digital logic ensuring quick transitions. BAV99LT1 305901-001 Four Diode drops used here ensure that PWR_GOOD goes soon power falling. This necessary 74HCT14 part. 74HCT14 2.7K 108251-181 201645-059 74HCT14 108251-181 BAV99LT1 305901-001
This example circuit generation AUX_GOOD. supervisor used generate clean transition also monitor voltage. 74LS14 SPRVSR 658184-001 AUX_GOOD AUX_GOOD
PCI_PWR
PCI_PWR
Title Size Date: File:
PHY_WOL.SCH
Number
Alert LAN*
23-Jan-1998 A:\PHY_WOL.SCH Sheet Drawn
Revision
+3.3V +3.3V DECOUPLING
AUX_PWR AUX_PWR DECOUPLING
.1uF 108427-050
.1uF 108427-050
PCI_PWR
PCI_PWR
4.7uF 202170-004
4.7uF 202170-004
.1uF 108427-050
.1uF 108427-050
DECOUPLING
.1uF 108427-050
.1uF 108427-050
.1uF 108427-050
.1uF 108427-050 LM79 bypass Caps .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050
AP_ASIC Bypass
.1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050 .1uF 108427-050
.1uF 108427-050
.1uF 108427-050
4.7uF 202170-004
4.7uF 202170-004
4.7uF 202170-004
4.7uF 202170-004
4.7uF 202170-004
4.7uF 202170-004
Title Size Date: File: 23-Jan-1998 A:\CAP.SCH
CAP.SCH
Number
Alert LAN*
Sheet Drawn
Revision

Application Note (AP-388) Revision July 1998 Document Number

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