Introducing Intel's Family Embedded Intel386Microprocessors PRANA

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AP-499 APPLICATION
Introducing Intel's Family Embedded Intel386Microprocessors
PRANAV MEHTA APPLICATIONS ENGINEERING
February 1994
Order Number: 272425-002
Intel Corporation makes warranty products assumes responsibility errors which appear this document does make commitment update information contained herein. Intel retains right make changes these specifications time, without notice. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. ordering code only used product name trademark Intel Corporation. Intel Corporation Intel's FASTPATH affiliated with Kinetics, division Excelan, Inc. FASTPATH trademark products. *Other brands names property their respective owners. Additional copies this document other Intel literature obtained from: Intel Corporation Literature Sales P.O. 7641 Prospect, 60056-7641 call 1-800-879-4683
INTEL CORPORATION 1994 CG-041493
CONTENTS
PAGE INTRODUCTION.1 OVERVIEW 2.1. Intel386EX Microprocessor Core 2.1.1. MODULAR 2.1.2. EXTERNAL INTERFACE 2.2. PC/DOS Compatible Features.5 2.2.1. TIMER/COUNTER UNIT.6 2.2.2. INTERRUPT CONTROL UNIT 2.2.3. ASYNCHRONOUS SERIAL (SIO) UNIT.6 2.2.4. DIRECT MEMORY ACCESS (DMA) CONTROLLER ARBITER 2.2.5. PORT 2.3. Embedded Control-Specific Features 2.3.1. CLOCK GENERATION POWER MANAGEMENT UNIT 2.3.2. CHIP SELECT UNIT 2.3.3. SYNCHRONOUS SERIAL (SSIO) UNIT 2.3.4. DRAM REFRESH CONTROL UNIT 2.3.5. WATCHDOG TIMER UNIT 2.3.6. PARALLEL PORTS 2.3.7. PACKAGING 2.4. JTAG Unit Testability ADDRESS SPACE 3.1. Structure 3.2. Expanded Space 3.3. Configuration Port 3.3.1. OPENING CLOSING EXPANDED SPACE CONFIGURING Intel386EX MICROPROCESSOR OPERATING MODES Intel386EX MICROPROCESSOR 5.1. DOS-Compatible Mode 5.2. Non-Intrusive Mode.15 5.3. Enhanced Mode 5.4. Non-DOS Mode.16 TABLES Table Expanded Address FIGURES Traditional Embedded-Application Design.1 DOS-Based Embedded Application Using Intel386EX Microprocessor.1 Real-Time Embedded-Application Design Using Intel386EX Microprocessor.2 Integration Value-Added Functions into Small Form-Factor Package Intel386EX Microprocessor Interface Unit Intel386EX Microprocessor Interface 16-Bit Wide SRAM.5 Intel386EX Microprocessor Interface 8-Bit Boot-Block EPROM.5 Intel386EX Microprocessor Interrupt Structure Intel386EX Microprocessor Clock Generation Unit.8 Interaction with Idle Powerdown Modes Simple Scheme Interfacing Intel386EX Microprocessor DRAM Space EISA Space.12 Configuration Port Intel386EX Microprocessor, Address Remap Configuration Register (REMAPCFG) Opening Intel386EX Microprocessor's Expanded Space.14 DOS-Compatible Mode.15 Non-Intrusive DOS-Compatible Mode Enhanced Mode.16 Non-DOS Mode PAGE CONCLUSION REFERENCES.17
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INTRODUCTION
Application
Intel386microprocessor family gained widespread acceptance world embedded applications. understand reasons driving this phenomenon, worth looking market segments that embracing this product family. There applications that seek achieve quick time-tomarket using personal computer-based development environment. Interestingly, applications this segment very similar traditional embedded markets (telecommunications, networking, factory automation, imaging). product development cycle drastically reduced embedding popular operating systems like Microsoft Windows* embedded target, obviating need software developers develop proprietary operating systems. Figures illustrate difference between embedded design using proprietary operating system embedded design with stored ROM. latter approach significantly reduces required amount applicationspecific development provides consistent sophisticated user interface embedded applications. Many home entertainment office automation products provide standard, PC-like user interface ease use. Applications like remote bar-code scanners, data loggers, digital cameras only require PC/DOS compatibility also demand enhanced power management features.
Customized BIOS
Intel386EX Microprocessor-Based Hardware Platform
A2215-0A
Application
Figure DOS-Based Embedded Application Using Intel386EX Microprocessor There also vast base applications that 80C186 product family. When these applications require higher performance address space, Intel386 architecture provides natural migration protect their code investment Intel architecture. such nonDOS applications, various real-time, multitasking operating systems kernels available, easing transition 32-bit Intel386 architecture. Figure shows application that uses Intel's iRMX® operating system. This Intel's real-time multitasking kernel. kernel isolates designer from details Intel386 microprocessor architecture.
Embedded Processor Support Hardware
A2214-0A
Figure Traditional Embedded-Application Design
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Application
such Power Management Unit, Chip Select Unit, DRAM Refresh Control Unit, Watchdog Timer Unit, Synchronous Asynchronous Serial Units, JTAG Boundary Scan Unit. Intel386 microprocessor PC-on-a-chip (integrated solution. differs from other integrated solutions some significant areas: Intel386 microprocessor designed DOS-compatible platform optimized embedded applications. This translates into integration additional peripherals geared toward standard embedded functions (e.g., chip-select logic, watchdog timer, ports, synchronous serial control unit). address space configuration limited Kbyte already assigned standard peripherals. obtain more register space additional peripherals, Intel386 micro-processor incorporates special address space ex-tension mechanism. There some departure from exact configuration. Embedded applications require higher performance superior functionality than those offered 8237A (the module architecture). Intel386 microprocessor provides enhanced controller module that superset 8237A. Also, cost-effective, reduces number channels (from seven architecture). Intel386 microprocessor does supply signals directly. Most embedded applications designed single-board systems require bus. However, original Intel386 microprocessor's maintained, easily recreated. Embedded applications adhere standard user interface. Hence, Intel386 microprocessor does have video controller keyboard controller. However, addresses these peripherals reserved that they added externally PC-compatible user interface desired. short, only those features architecture that also useful embedded arena retained Intel386 microprocessor. This makes Intel386 microprocessor cost effective across wide range applications.
Real-Time Multitasking Operating System/Kernel
Intel386 Microprocessor-Based Hardware Platform
A2216-0A
Figure Real-Time Embedded-Application Design Using Intel386EX Microprocessor Against this background, Intel introducing family embedded Intel386 microprocessors meet requirements various embedded market segments. initial offerings this family fully static, 32-bit microprocessors following: Intel386 microprocessor PC/DOScompatible processor that been optimized embedded applications Intel386 microprocessor adds additional address lines, low-power operation, Intel's System Management Mode (SMM) features Intel386 microprocessor Static Intel386 microprocessor pin-compatible with dynamic Intel386 microprocessor features Intel386 microprocessor well documented. This application note describes Intel386 microprocessor. Intel386 microprocessor covered detail because addressability same those Intel386 microprocessor. Figure illustrates basic functions offered Intel386 microprocessor. Although some peripherals compatible with architecture, Intel386 microprocessor provides additional features,
Smart, Value-Added Integration i386EX Microprocessor
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PQFP
A2228-0A
Figure Integration Value-Added Functions into Small Form-Factor Package
OVERVIEW
mentioned above, Intel386 microprocessor brings PC/DOS compatibility embedded applications, while offering many features useful embedded systems. following discussion describes Intel386 microprocessor core, peripherals that provide compatibility, peripherals features that optimized embedded applications.
Intel386 microprocessor core design modular, allowing easier implementation future proliferations embedded Intel386 micro-processor product family. Intel386 microprocessor process-shifted from micron process micron process, giving more performance headroom. This vital, performance requirements typically grow over long life span embedded processor. Intel386 microprocessor offered dual operating voltage part. This means that operates supply voltage specifications, 10%. Embedded applications more likely exposed wider temperature extremes than standard desktop portable applications. Components embedded design must able withstand this environment. Intel386 microprocessor offered with extended temperature range -40°C +85°C.
2.1. Intel386EX Microprocessor Core
Intel386 microprocessor uses same 32-bit core that standard Intel386 microprocessor, with some enhancements make suitable needs embedded market. Intel386 microprocessor core fully static, which means that processor will retain state even when incoming clock signal removed.
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Another feature added Intel386 microprocessor Intel System Management Mode (SMM). added fourth operating mode Intel architecture, along with real, protected, virtual-86 modes. implementation Intel386 microprocessor compatible with SL-enhanced Intel486and Pentiumprocessors. Although originally introduced power management features portable computers, used embedded environment other purposes, such debugging, having alternate operating system, virtualizing devices. More information this topic will available during first quarter 1994. 2.1.1. MODULAR
Memory Control Module Memory Control Module Core Address i386EX Core Data Microprocessor Core Control Core EM-Address Internal Unit EM-Data EM-Control EM-Bus External Address Module
EI-Address EI-Control
External Interface
External Data External Control
EI-Data
Intel386 microprocessor incorporates modular design approach. internal buses defined: EMbus EI-bus. shown Figure internal unit interfaces with address, data, control signals from core then splits them into EIbus. EM-bus full 26-bit address connecting Intel386 core modules that need full address range operation (e.g., DMA). 16-bit address EI-bus isolates core from majority devices integrated chip. This prevents overloading with signals coming from core peripherals added EI-bus. This modular approach significantly reduces development time future proliferations embedded Intel386 microprocessor product family. 2.1.2. EXTERNAL INTERFAC
Module
A2217-0A
Figure Intel386EX Microprocessor Interface Unit While Intel386 microprocessor retains original Intel386 microprocessor compatibility with existing ASICs chip sets, adds following enhancements suit embedded applications. standard Intel386 microprocessor 24-bit external address bus. This allows operating system application programs address Mbytes physical memory directly. Conventional embedded applications require much less memory. However, mentioned before, trend embedded applications requires more sophisticated, graphical user interfaces, which demands larger data code storage space. Keeping mind characteristically long life cycles embedded applications, Intel386 microprocessor provides 26-bit addressing that will support Mbytes memory space. coincidentally, this range fits very well with emerging PCMCIA standard. This will become important PCMCIA cards find their into embedded applications.
Intel386 microprocessor's external superset Intel386 microprocessor's bus. example, maintains non-multiplexed 16-bit data bus, like that Intel386 microprocessor, higher performance. When data multiplexed with address bus, must latch address first clock cycle then treat data remainder cycle. non-multiplexed obviates need address latching, requiring fewer clock cycles complete cycle.
EI-Bus
i386EX Microprocessor
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Many embedded designs still 8-bit devices cost efficiency. Intel386 microprocessor provides BS8# signal dynamically change default 16-bit cycle 8-bit cycle. BS8# within specified time period, current cycle word sized, then microprocessor will issue another cycle byte address. Figure shows this feature combined with microprocessor's chip-select logic implement glue-less interface 8-bit boot-block EPROM.
external Intel386 microprocessor contains multiplexed W/R# signal designate current cycles write operation (logic read operation (logic Most static RAMs (SRAMs) EPROMs available market require separate read write control signals interfacing. This means that Intel386 microprocessor-based system, glue logic required demultiplex W/R# signal before routing memory. facilitate simplified interface SRAMs EPROMs, Intel386 microprocessor offers separate signals. Figure shows example interfacing Intel386 microprocessor 16-bit wide SRAM. multiplexed W/R# signal retained compatibility with existing companion chips.
8-bit Boot-Block EPROM
A2:1
An:1 D7:0
SRAM Upper Byte
i386 Microprocessor
BLE# D7:0 UCS# BS8#
BHE# D15:8 An:A1 D15:0 CSn# SRAM Lower Byte
An:A1
A2230-0A
Figure Intel386EX Microprocessor Interface 8-Bit Boot-Block EPROM Intel386 microprocessor contains on-chip wait state Ready generation logic part Chip Select Unit. Whenever internal Ready generator used either accesses internal peripherals through Chip Select Unit signal called Local Access (LBA#) asserted signal cycle external state machines that tracking activity.
BLE# BS8# D7:0 An:A1
A2231-0A
Figure Intel386EX Microprocessor Interface 16-Bit Wide SRAM
2.2. PC/DOS Compatible Features
central idea behind Intel386 microprocessor bring compatibility embedded environment. idea provide minimal functions keep cost attractive cross-section users) compatibility then designers externally specific hardware required externally. Intel386 microprocessor contains following PC/DOS-compatible peripheral functions board.
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2.2.1. TIMER/COUNTER UNIT
tion registers associated with interrupt control unit determines interrupt sources, described later. 2.2.3. ASYNCHRONOUS SERIAL (SIO) UNIT
Timer/Counter Unit Intel386 microprocessor same functionality industry standard 82C54 counter/timer. provides three independent 16bit counters, each capable handling clock inputs MHz. source timer clocks selected either internal processor clock external clocking circuit. timer/counter module programmed operate different modes. Various modes allow timer unit used event counter, elapsed time indicator, programmable one-shot, etc. 2.2.2. INTERRUPT CONTROL UNIT
Intel386 microprocessor's asynchronous serial port Universal Asynchronous Receiver/Transmitter (UART). Functionally, equivalent National Semiconductor NS16450 INS8250A. Intel386 microprocessor such serial ports. UART performs serial-to-parallel conversion characters received from external device parallelto-serial conversion characters received from before transmitting them external world. read status UART time during functional operation. Status information reported includes type condition transfer operations being performed UART error conditions (parity, overrun, framing, break interrupt). Some other features unit following: UART includes programmable baud-rate generator capable dividing baud-clock input divisors (216 multiplying clock drive internal transmitter receiver logic. baud-clock input selected either derivative internal processor clock external clocking circuit. "sticky" feature UART allows ninebit serial transfer mode used multidrop configurations which master communicates with several slave processors. DOS-compatible applications, serial transfer (baud) rates typically exceed 19.2 Kbaud. However, many non-DOS applications demand higher baud rates. maximum baud rate achievable Intel386 microprocessor's unit 530K. achieve approximately 500K baud rate with processing serial interrupts requires almost 100% processor's bandwidth. This typical overhead involved saving current processor information before jumping interrupt service routine. Thus such high transfer rates cannot other useful work. circumvent this problem, serial interrupts Intel386 microprocessor selectively connected module. this case, instead generating interrupt whenever transmit buffer empty receive buffer full, appropriate request line (DREQ) activated. Arbiter unit (explained next section) turn
Intel386 microprocessor incorporates 8259A Programmable Interrupt Control (PIC) units, same peripherals used architecture. addition using same functional modules, these PICs connected same master/slave configuration system. example, output timer/counter channel connected IRQ0 input master 8259A. Figure illustrates various connections.
Timer External Serial Port (COM2) Serial Port (COM1) External External External
INTR
8259A Master
CAS[2:0]
External External Serial Timer Timer External External Watchdog
8259A Slave
CAS[2:0]
A2223-0A
Figure Intel386EX Microprocessor Interrupt Structure Intel386 microprocessor offers total eight external interrupt lines. Four these, which come from master 8259A, cascaded externally with additional 8259As. Thus total number external interrupt lines expanded configura-
2.2.4.
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8237A operating modes supported except special two-cycle mode. Instead, true two-cycle mode provided that does require channels memory-to-memory transfers. Similar 8237A, controller programmed through 8-bit registers. Arbiter works much like priority resolving circuitry DMA. receives requests from channels, external master, DRAM Refresh Controller. Arbiter requests ownership asserting internal HOLD signal processor resolves priority issues among active requests when ownership granted. 2.2.5. PORT
generates internal HOLD request core. Unless processor executing LOCKed cycles, relinquishes external rather quickly. Once Arbiter gives control appropriate channel, data transmitted (from) memory from (to) appropriate UART buffer within cycles. Circumventing interrupt latency processor this fashion results only bandwidth same 500K baud rate!
UART programmed work either polled interrupt-driven environment. DIRECT MEMORY ACCESS (DMA) CONTROLLER ARBITER
Intel386 microprocessor's Controller 2-channel with feature that enhancements beyond 8237A controller used (ISA) architecture. incorporates full 26-bit addressing, 2cycle mode memory-to-memory transfers using only channel, buffer chaining mode, etc. However, module configured 8237A-like mode. circuitry designed that additional channels added future embedded Intel386 microprocessor products. Intel386 microprocessor's controller capable transferring data between combination memory I/O, with combination bits) data path widths. bandwidth optimized through internal temporary register that disassemble assemble data from either aligned nonaligned destination source. Intel386 microprocessor's channels, each which operates independently. Each channel many different operating modes data transfer (single, block demand transfer with either "fly-by" two-cycle mode). Many operating modes combined provide very versatile controller. design unit backward-compatible with 8237A, follows: Even though Intel386 microprocessor's capable generating 26-bit addresses directly, emulate page register feature architecture, option provided prevent overflow from lower bits higher bits.
overcome limitations 80286 processor, early PC-AT systems incorporated special features: A20GATE FastCPUReset, described below. These features were implemented somewhat random fashion beginning, over time almost OEMs settled providing these features register bits location 92H. Intel386 architecture does have similar limitations, these features implemented Intel386 microprocessor because need backward-compatible with enormous amount software written 80286-based systems. 2.2.5.1. A20GAT
A20GATE allows systems emulate wraparound characteristic 8086 processor across Mbyte address boundary. When disabled, however, allows programs access Kbytes extra memory above Mbyte boundary. 2.2.5.2. FastCPUReset
Whenever this Port set, resets only Intel386 microprocessor. This provides backward compatibility with programs written 80286 that reset processor switch from protected mode real mode.
2.3. Embedded Control-Specific Features
following complementary features Intel386 microprocessor that make DOS-compatible engine optimized embedded applications.
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2.3.1. CLOCK GENERATION POWER MANAGEMENT UNIT 2.3.1.1. Idle Mode
clock generation unit provides uniform, non-overlapping clock signals associated peripherals. Figure shows clock signals generated within clock unit. power management features control clock signals provide different power management functions. clock generation circuit includes divideby-two counter, programmable divider generating prescaled clock (PSCLK), divide-by-two counter generating baud clock inputs serial control units (SERCLK), reset circuit. Intel386 microprocessor does incorporate on-chip oscillator circuit. Given wide operating voltage specification Intel386 microprocessor, difficult characterize oscillator given frequency that provides accurate time reference entire voltage range. Thus, absence CLKOUT signal from on-chip oscillator, CLK2 input (twice operating frequency processor) provides fundamental timing reference Intel386 microprocessor.
RESET (from 8259A) SMI#
Intel386 microprocessor consumes about half total device power. When processor waiting external event occur, Idle mode used stop clocks during waiting period. This reduces power consumption significantly. When external event occurs, processor exits Idle mode resumes operation. While idle, however, peripheral clocks still active (for example, serial channel transfer data DMA, that process continues without interruption). Idle mode entered manipulating bits Power Control register then executing HALT instruction. Upon receiving unmasked interrupt, NMI, SMI, processor exits Idle mode. 2.3.1.2. Powerdown Mode
There instances low-power applications when processor operation required until certain external event occurs. Powerdown mode allows clocks going well peripherals disabled. Processor current consumption reduced leakage current (microamps). Powerdown mode entered manipulating bits Power Control register then executing HALT instruction. Upon receiving unmasked interrupt, NMI, SMI, processor exits Powerdown mode. PWRDOWN output signal provided control other external devices, desired.
Power Manager
Powerdown
Core Clock Buffers
PH1C PH2C
Core Clocks
CLK2 Peripheral Clock Buffers SERCLK Programmable Divider PSCLK (Prescaled clock)
A2224-0B
PH1P PH2P
Peripheral Clocks
UART1 UART2 Synchronous Serial I/O(SSIO) Timer Module SSIO Module
Figure Intel386EX Microprocessor Clock Generation Unit application requirements Intel386 microprocessor power consumption. power management modes provided Intel386 microprocessor: Idle Powerdown.
2.3.1.3. 2.3.2.
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address location (where 0-15, depending upon mask register). size region dependent upon mask used. chip-select region active when meets following criteria: chip-select enable lower mask register enabled. status matches programmed type (memory I/O). cycle address equal nonmasked portion chip-select address. memory address applies memory read, memory write, instruction fetch cycles. address applies read write cycles. Interrupt acknowledge HALT cycles will activate chip-select regions. After power-on reset, only chip-select region active, selecting UCS# chip-select pin. following summarizes features Chip Select Unit: Eight chip-selects with Kbyte granularity memory accesses word granularity accesses. Support memory addressing.
Powerdown flag Halt instruction Unmasked Interrupt IDLE flag Halt instruction
Interaction with Idle Powerdown Modes
Upon receiving interrupt, Intel386 microprocessor exits Idle Powerdown mode then enters Intel System Management Mode (SMM). Once appropriate actions have been taken SMM, before exiting SMM, possible check entered while processor Halt state. this point, desired, SM-code flag that returns processor HALT state upon exiting SMM. Assuming that Power Control Register bits were changed SMM, processor then re-enters Idle Powerdown mode. Figure describes these state transitions. CHIP SELECT UNIT
Chip Select Unit (CSU) decodes cycle address status information activates chip-select signals that enabled. individual chip-selects become valid same state address lines follow same timings address lines.
Normal Operation
Programmable start address with mask register indicate chip-select region, allowing overlap. Memory cycle decoder.
Idle Mode
Powerdown Mode
Programmable wait state generator wait states). On-chip 8-bit size generator. Provision disable chip-select. Provision override ready. 2.3.3. SYNCHRONOUS SERIAL (SSIO) UNIT
SMI# Powerdown flag set; Halt restart slot instruction Reset Halt restart slot instruction IDLE flag set; Halt restart slot instruction
System Management Mode
A2229-0A
Figure Interaction with Idle Powerdown Modes divided into eight separate chip-select regions; each enable eight chip-select signals. Each chip-select region mapped into memory space. memory-mapped chip-select region start 2(n+1) Kbyte address location (where 0-15, depending upon mask register). I/Omapped chip-select region start 2(n+1) word
Synchronous Serial (SSIO) unit Intel386 microprocessor allows simultaneous bidirectional communications. consists transmit channel, receive channel, dedicated baud rate generator. transmit receive channels operated independently (using different clocks) provide non-lockstep, full-duplex communications. Each channel capable originating clocking signal (Master Mode) receiving externally generated clocking signal (Slave Mode).
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following summarizes features SSIO unit: 6.25 Mbaud maximum shift clock speed MHz) Double-buffered 16-bit data register each channel Shared baud rate generator Gated interrupt outputs Independently enabled transmit receive functions Programmable connection SSIO interrupts on-chip DMA, similar that UARTs
D15:0 RAS# CAS# Lower Byte i386EX Microprocessor Multiplexer An:1 ROW/COL# DRAM An:1
DRAM An:1 D7:0 RAS# CAS# D15:8 Upper Byte ADS# PH2P BLE# BHE# REFRESH# M/IO#,D/C#,W/R# GCSx CLK2 CLK2 System Reset EPLD RAS# CASL# CAS#H
2.3.4.
DRAM REFRESH CONTROL UNIT
Several vendors offer fully integrated DRAM controllers, either single-chip solution part chip-set. These devices useful, there several factors that lead designers design their DRAM interface: Off-the-shelf DRAM controllers expensive. They typically have high counts power requirements. They offer many special features such nibble, page, static-column modes that commonly used embedded applications. This represents non-value added functionality user. simple DRAM interface implemented using couple multiplexers inexpensive Programmable Logic Device (PLD). Figure shows basic conceptual elements such design. resulting logic would most cost-effective solution specific application. Intel386 microprocessor incorporates simple DRAM refresh control logic that provides three basic functions complete DRAM interface: Programmable refresh interval arbitration logic whenever refresh cycle needs generated address generation refresh DRAM cells REFRESH# provided that used external logic generate appropriate "RAS only," "CAS before RAS," simple dummy read cycles refresh DRAM.
A2290-0A
Figure Simple Scheme Interfacing Intel386EX Microprocessor DRAM 2.3.5. WATCHDOG TIMER UNIT
variety sources cause system failures; example, runaway software work into endless loop waiting event that never occurs. sources system failures anticipated guarded against. Watchdog Timer (WDT) unit provides method graceful recovery from unexpected hardware software upsets. contains 32-bit programmable counter that generates pulse WDTOUT PH2P cycles CLK2 cycles, under normal operation). This signal directly back RESET, NMI, other interrupt. unit Intel386 microprocessor configured three possible states. 2.3.5.1. Software Watchdog Mode
Runaway software cause system hang. programmed software watchdog, then executing software needs reload timer before timer expires. special instruction sequence, that errant code would very unlikely produce, used reload timer.
2.3.5.2. 2.3.5.3.
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package. This will followed 144-pin EIAJ TQFP. Figure page shows value-added integration peripherals other embedded features into small form-factor package.
Monitor Mode
some cases, hardware upset errant code cause access peripheral location that does exist hardware system. "normally ready" system, this would cause hang-up because processor would waiting Ready terminate cycle. Monitor mode protects against this scenario. When Monitor mode, timer loaded every falling edge ADS# (beginning cycle) counting stopped when READY# goes low. READY# signal asserted within programmed interval, WDTOUT signal activated. Free-Running Counter Mode
2.4. JTAG Unit Testability
With shrinking package size (and pitch), increasing system complexity, advent surface-mount technology, circuit board testing become major issue. emerging standards industry simplify board testing JTAG boundary scan technique. Intel386 microprocessor employs IEEE 1149.1 compliant JTAG boundary scan standard facilitate manufacturability testability products.
neither Software Watchdog function Monitor function required, Watchdog Timer used general-purpose, 32-bit, free-running counter. instances, only action takes expiration timer activating WDTOUT signal. system designer route this signal Reset pin, NMI, other nonmaskable interrupts satisfy system requirements. Intel386 microprocessor also allows designer route WDTOUT signal internally internal slave 8259A interrupt controller. 2.3.6. PARALLEL PORTS Many applications require on-chip peripheral functions available Intel386 microprocessor. example, relatively small system would require only eight chip-select lines provided. other applications, modem control signals required. cost-sensitive embedded world, maximum utilization real estate desired. Input/Output ports allow system designers flexibility replace function unused peripheral pins with general-purpose ports. Many on-chip peripheral functions multiplexed with port. Intel386 microprocessor's ports bitprogrammable input-only, output-only, opendrain bidirectional. Ports share input/output buffer cell that drive capability. Port drive capability interface directly with heavierload devices such LEDs. These drive capabilities offered volts. 2.3.7. PACKAGING
ADDRESS SPAC
appropriate this juncture discuss Intel386 microprocessor's address space. architecture, defined standard, peculiar scheme address decoding. addresses most common peripherals found architecture fixed. While addressing scheme Intel386 microprocessor needs compatible with scheme, needs beyond that accommodate extra peripherals designed embedded applications.
3.1. Structure
Intel386 microprocessor's address space Kbytes. platforms, assumes that only total address space used. first bytes (addresses 0000H 00FFH) this space reserved platform (motherboard) resources, such interrupt controllers. remaining bytes (addresses 0100H 03FFH) available "general" peripheral card resources. Since only address space supported, add-in peripheral cards decode only lower address lines; consequently, upper address lines (A10-A15) ignored. Because upper address lines decoded, platform address locations address locations repeated times boundaries), covering entire address space. (See Figure 12.) Add-in peripheral cards addresses reserved platform resources. Software running platform copies address locations reserved platform resources.
Initially, Intel386 microprocessor will offered 132-pin JEDEC Plastic Quad Flat Pack (PQFP)
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FFFFH (64K) General Slot FD00H
General Slot Slot General Slot
FFFFH (64K) FC00H (63K) F800H (62K) F400H (61K) F000H (60K)
Platform (Reserved) FC00H (63K)
Slot General Slot Slot General Slot Slot
0C00H (3K) General Slot 0900H Platform (Reserved) 0800H (2K) General Slot 0500H Platform (Reserved) 0400H (1K) General Slot 0100H (256) Platform (Reserved) 0000H
A2225-0A
General Slot Slot General Slot Slot General Slot Slot General Slot Slot General Slot Slot General Slot Slot General Slot Slot General Slot Slot
A2226-0A
1FFFH (8K) 1C00H (7K) 1800H (6K) 1400H (5K) 1000H (4K) 0C00H (3K) 0800H (2K) 0400H (1K) 0000H (0K)
Figure Space
3.2. Expanded Space
Intel386 microprocessor's address scheme (similar that EISA(32) systems) exploits above facts assigning repetitions first address locations specific slots1. partitioning such that groups address locations assigned each slot, total 1024 specific address locations slot. (See Figure 13.) Since add-in cards decode only lower address lines, they respond "general" bytes (repeated times). Thus, each slot addresses four 256-byte segments) that potentially contain extended peripheral registers.
Figure EISA Space Slot refers platform. (Again, many peripherals found standard platform (motherboard) integrated Intel386 microprocessor). Thus, total unique addresses assigned platform addition bytes which repeated). first address locations same platform resources defined across platforms. remaining three groups address locations used specific platform such EISA. Intel386 microprocessor, slot used extra registers needed integrated non-DOS peripherals. This safe method because, although EISA method allows slots defined, traditionally only slots available platform. other words, slot typically used2.
slot socket used connect add-on boards standard buses expanding functionality system. embedded processors like Intel386 microprocessor, term slot more concept than physical reality. slot could viewed part total address space.
addition slot Intel reserves slot future expansion embedded Intel386 microprocessor product family.
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register (often referred Configuration Port), defined Figure Remap bits this register control whether onchip peripherals mapped into regular address space (i.e., first bytes slot mapped expanded address space (i.e., slot 15). associated with particular peripheral then mapped into space. individually bits various peripherals them out. important note, however, that contents this register modified only after expanded address space enabled specified below. Reset, this register cleared, which maps on-chip peripherals into space.
3.3. Configuration Port
address locations slot (within area) offer special case. These address locations used peripheral registers main platform. Intel386 microprocessor other integrated solutions them enable extra address space required configuration registers specific these products. These same address locations used enabling extra address space Intel386 microprocessor. Also, 16-bit register location used control mapping various on-chip peripherals address space. This register, designated REMAPCFG
Register Name Register Mnemonic Register Function
Address Configuration Register (Configuration Port) REMAPCFG Enables disables expanded space allows address remapping some on-chip peripherals.
Mnemonic
Reset State
Function Enables expanded space. Remaps Serial Channel (COM2) address. Remaps Serial Channel (COM1) address. Remaps Slave 8259A Interrupt Controller address. Remaps Master 8259A Interrupt Controller address. Remaps address. Remaps Timer address.
Figure Configuration Port Intel386EX Microprocessor, Address Remap Configuration Register (REMAPCFG) 3.3.1. OPENING CLOSING EXPANDED SPACE on-chip peripherals like timers, DMA, interrupt controllers serial communication channels mapped regular space into expanded space (using REMAPCFG register). Registers associated with other on-chip peripherals (Chip Select
Intel386 microprocessor's expanded space enabled specific write sequence addresses 23H. Once expanded space enabled,
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Unit, Power Management module, Watchdog Timer, etc.) accessed. address this expanded mode illustrated Table Table Expanded Address Register Description Controller Master Interrupt Controller Programmable Interval Timer Page Registers Slave Interrupt Controller Math Coprocessor Chip Select Unit Synchronous Serial Unit DRAM Refresh Control Unit Watchdog Timer Unit Asynchronous Serial Channel (COM1) Clock Generation Power Management Unit External/Internal Interface Unit Chip Configuration Registers Parallel Ports Asynchronous Serial Channel (COM2) Address Range F000H F020H F040H F080H F0A0H F0F0H F400H F480H F4A0H F4C0H F4F8H F800H F810H F820H F860H F8F8H F01FH F03FH F05FH F09FH F0BFH F0FFH F47FH F49FH F4BFH F4CFH F4FFH F80FH F81FH F83FH
Space Remap Register 3FFH
compatibility. special address-decoding technique required accomplish this. address-decoding scheme based values Expanded Space Enabled (ESE) individual Address Remap bits REMAPCFG register. Various combinations these values define four basic operating modes Intel386 microprocessor, discussed Section
Intel386EX Microprocessor Expanded Space
F87FH F8FFH
A2218-0A
Figure Opening Intel386EX Microprocessor's Expanded Space
REMAPCFG register write-protected until expanded space unlocked (see Figure 15). When unlocking write sequence executed, sets Expanded Space Enabled (ESE) bit, which REMAPCFG register (Figure 14). program check this whether access expanded space registers. Clearing Expanded Space Enabled (ESE) disables expanded space. This again locks REMAPCFG register makes read-only. indicated address map, registers associated with Intel386 microprocessor's peripherals controls (except REMAPCFG) physically located unique address space Slot (i.e., address ranges F000H-F0FFH, F400H-F4FFH, F800H-F8FFH). However, some these registers need mapped into lower address range (slot
CONFIGURING Intel386EX MICROPROCESSOR
During chip initialization (and other times needed), Intel386 microprocessor configured different ways. Configuration choices available interconnect various on-chip peripheral modules certain ways. Functions many device pins also programmed. Intel386 microprocessor incorporates module configuration registers configuration registers (located between F820H F83FH Expanded space) these purposes. example, output timer channel internally connected IRQ2 line slave 8259A then, level, shared programmed PORT3.1 instead timer output TMROUT1. idea allow much flexibility end-user possible,
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given wide array features available Intel386 microprocessor.
5.2. Non-Intrusive Mode
This mode characterized following values:
OPERATING MODES Intel386EX MICROPROCESSOR
individual peripheral's Remap Peripherals whose corresponding Remap bits will mapped expanded space. Still, only A9-A0 address lines decoded internally. Mapped peripherals non-DOS peripherals inaccessible (see Figure 17). This mode useful when on-chip DOS-compatible peripheral used DOS-compatible function but, instead, stand-alone peripheral connected externally. example, designer might connect external 8237A 100% compatibility rather than using Intel386 microprocessor's enhanced module. this case, Remap integrated block will (1). external 8237A accessed slot space, while integrated accessed only after expanded space enabled.
discussed earlier, Intel386 microprocessor programmed operate four different operating modes depending application.
5.1. DOS-Compatible Mode
This mode characterized following values: peripherals' Remap bits peripherals mapped into space. Only address lines A9-A0 decoded on-chip peripherals. other words, accesses peripherals valid, whereas non-DOS peripherals inaccessible (see Figure 16). This mode useful accessing on-chip timer, interrupt controller, UARTs, controller DOScompatible environment.
3FFH
On-chip UART-0
3FFH
On-chip UART-0
On-chip UART-1
On-chip UART-1
On-chip 8259A-2 Expanded Space
On-chip Timer
On-chip 8259A-2 Expanded Space
On-chip
NOTE: Shaded area depicts space that accessible.
On-chip Timer
On-chip 8259A-1
Remap Register
NOTE: Shaded area depicts space that accessible.
On-chip 8259A-1
External Space
On-chip Space
A2220-0A
Figure Non-Intrusive DOS-Compatible Mode
A2219-0A
Figure DOS-Compatible Mode
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5.3. Enhanced Mode
This mode characterized following values: peripherals' Remap bits Internally, address lines A15-A0 decoded. same time, on-chip peripherals mapped into slot space (00H-3FFH). access peripheral accesses physical register slot space, same time reflected slot space (see Figure 18). application frequently requires additional peripherals available Intel386 microprocessor same time wants maintain some level compatibility ease development, this most useful mode. External decoding logic must decode address lines A15-A0 this mode.
Internally, address lines A15-A0 decoded. Corresponding on-chip peripherals accessed only slot space. designer place other peripherals slot with conflict (see Figure 19). Again, external logic must decode A15-A0. This mode those systems that don't require compatibility have other custom peripherals slot space. complete non-DOS mode accomplished when remap bits (1). peripherals, lower bits space expanded space identical (except UARTs, whose lower bits identical). This makes remapping easier. Also, UARTs have fixed addresses. This differs from standard configurations, which these address ranges programmable. However, some other device located same location, then customized BIOS Intel386 microprocessor detect them, remap corresponding channel space, then write address (F4F8H-F4FFH, example, channel into BIOS data table describing map. course, this case, would enter Enhanced mode access channel
3FFH
On-chip UART-2
On-chip UART-1 3FFH
On-chip 8259A-2 Expanded Space (Other peripherals) Expanded Space
On-chip Timer
Other Peripherals UART-0 UART-1 On-chip 8259A-1 Timer 8259A-2 On-chip Space On-chip 8259A-1
A2221-0A
Figure Enhanced Mode
5.4. Non-DOS Mode
This mode characterized following values: individual peripheral's Remap
A2222-0A
Figure Non-DOS Mode
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CONCLUSION
There growing need many embedded market segments processor solutions that enable fast development cycle low-power, high-performance applications requiring minimum board space. Intel plans meet needs these market segments with embedded Intel386 microprocessor product family. three initial product offerings, Intel386 Intel386 microprocessors offer high-performance computing power without integration. third member family, integrated Intel386 microprocessor, reviewed. Intel386 microprocessor Intel386 architecture-based, PC/DOS-compatible processor that been optimized embedded applications.
REFERENCES
Solari, Edward, Design, Annabooks, Diego, 1991.

Introducing Intel's Family Embedded Intel386Microprocessors PRANA

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