C167CR Interrupt Structure Controller Area Network (CAN) module w

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Microcontrollers ApNote AP1621
C167CR Interrupt Structure
Controller Area Network (CAN) module which been implemented Siemens C167CR microcontrollers allows communication between several stations (CAN nodes) BASIC-CAN functionality FULL-CAN functionality according specification V2.0B active. This document describes functionality interrupt structure gives implementation example standard interrupt subroutine. Author Jens Barrenscheen Microcontroller Product Definition
12.96,
C167CR Interrupt Structure
Contents
Page
Interrupt Sources Status Interrupts Error Interrupts Message Specific Interrupts
Interrupt Identification INTID Code General Interrupt Handling Bus-Off Re-Initialisation Message Interrupt Summary
AP1621 ApNote Revision History Actual Revision 12.96 Page Page actual Rev. prev.Rel. Previous Revision none (Original Version) Subjects (changes since last release)
AP1621 12.96
C167CR Interrupt Structure
Interrupt Sources
many different interrupt sources generate only global interrupt request, their internal structure must taken into account interrupt service procedure. INTID code Interrupt Register (EF02H) indicates which source activated request. Control/Status Register (EF00H) globally enables (IE=1) disables interrupt sources module.
C167CR controller provides three different types interrupts: Status Interrupts
They generated after status change module, which indicated flags status part (high byte) Control/Status Register. reason status interrupt successful transmission (TXOK set) reception (RXOK set) message, occurrence error (LEC bitfield) during message transfer. These interrupt sources enabled setting Control/Status Register. Error Interrupts
These interrupts, which enabled Control/Status Register, generated after each change flags EWRN BOFF. These flags indicate level internal error counters (transmit error counter receive error counter). these counter reaches value error warning flag EWRN set. exceeds value 255, flag BOFF set. Furthermore, INIT automatically device stops action bus, goes bus-off. resynchronisation achieved resetting INIT software. Message Specific Interrupts
Interrupts this type generated each message object after successful transmission reception. This function individually enabled setting bits TXIE and/or RXIE corresponding Message Control Register (MCR_Mn) located address EFn0H, with (1.15) being number corresponding message object.
Interrupt Identification INTID Code
INTID code indicates that requested interrupts have been correctly serviced more interrupts pending. This should condition leave interrupt service routine. INTID value indicates status interrupt enabled SIE) error interrupt enabled EIE), which cause interrupt with highest priority. case status change successful message transfer, flags TXOK RXOK Status Register set. erroneous message transfer indicated field. case error interrupt, least error flags EWRN BOFF changed. INTID code indicates reception message message object This special case will discussed later.
AP1621 12.96
C167CR Interrupt Structure
INTID code 3.16 indicates message specific transmit TXIE set) receive RXIE set) interrupt concerning message objects (INTID-2). addition, global flags TXOK RXOK checked decide interrupt received transmitted message. successful message transfer sets INTPND corresponding Message Control Register MCR_Mn, which must cleared software reset this interrupt request.
General Interrupt Handling
status part (high byte) Control/Status Register must read interrupt service procedure order identify interrupt source reset pending interrupt request. Flags TXOK RXOK this part register have then cleared software. priority internal interrupt sources decreases with increasing INTID code. This structure must also taken into account identification interrupt source. example, successful transmission only message object cause independent interrupt requests corresponding TXIE have been set. While status interrupt (highest priority) serviced INTPND this message object cleared, message specific interrupt remains pending. order ensure that interrupts correctly serviced, standard interrupt procedure C167CR should respect following items. Each read operation status part (SR) Control/Status Register (high byte, located EF01H) have influence INTID value. avoid errors this functionality, this register should read only beginning interrupt routine then stored variable (here: status). following actions, such flag tests, only refer this variable. same structure used variable intid, which yields value Interrupt Register (IR). Furthermore, INTPND concerned Message Control Register (MCR_Mn) reset order release interrupt request been activated message specific bits TXIE RXIE.
interrupt void int_can (void) interrupt CANI {unsigned char status, intid; while (intid {status read reset status switch (intid) case status error interrupt (status 0x0004) status interrupts (status 0x0800) transmit interrupt (status 0x1000) receive interrupt (status 0x0700) erroneous transfer (status 0x0008) error interrupts (status 0x4000) EWRN changed (status 0x8000) BUSOFF changed break; case message interrupt special chapter break; case message interrupt MCR_M1 0xFFFD; reset INTPND (status 0x0800) transmit interrupt (status 0x1000) receive interrupt break;
AP1621 12.96
C167CR Interrupt Structure
case MCR_M2 0xFFFD; (status 0x0800) (status 0x1000) break; case MCR_M3 0xFFFD; (status 0x0800) (status 0x1000) break; case MCR_M14 0xFFFD; (status 0x0800) (status 0x1000) break;
message interrupt reset INTPND transmit interrupt receive interrupt message interrupt reset INTPND transmit interrupt receive interrupt message interrupt reset INTPND transmit interrupt receive interrupt
Bus-Off Re-Initialisation
Each transfer error causes incrementation error counters (receive error counter transmit error counter) module. these counters reaches value EWRN set. enabled bits this action generates error interrupt. receive error counter stops up-counting when device goes into error passive state, even more receive errors occur. transmit error counter incremented each error transmitted messages. this counter exceeds value 255, BOFF error interrupt generated, too. Furthermore, device then goes into bus-off state, sets INIT stops actions bus. re-initialisation module started after resetting INIT software. device then goes into bus-off recovery checks logic level input line CAN_RxD. value written bitfield after monitoring sequence recessive bits. After these sequences, device resynchronised bus. During this procedure, code should interpreted error (same code Bit0Error). indicates that device successfully trying synchronise that continuously disturbed. bits set, status interrupt generated after each sequence. user does want this feature, possible disable status interrupts during bus-off recovery resetting control part (CR) Control/Status Register (low byte, located EF00H). This done following instructions interrupt routine:
case (status 0x0008) (status 0x4000) (status 0x8000) 0x0A; else 0x0E; break; status error interrupt error interrupts EWRN other instructions BUSOFF bus-off recovery reset SIE, other instructions SIE, other instructions
AP1621 12.96
C167CR Interrupt Structure
Message Interrupt
internal structure message object been adapted provide BASIC-CAN feature. this mode, incoming messages with identifiers, which matching other message objects, stored object other objects have been activated, messages treated message object check whether incoming message addresses controller (acceptance filtering) should ignored. consequence, required time deal with incoming data increases, messages (data remote frames, standard extended identifiers) handled. special double buffer system been implemented order avoid data losses case messages arriving just after other. While working these buffers, next incoming message stored second one, figure This double buffer structure concerns data bytes well bits Message Control Register (MCR_M15) This structure must taken into account message specific receive interrupt should generated. Therefore, RXIE Message Control Register set. Note: this object only used receive object, TXIE influence functionality. needs work buffer containing latest incoming message, buffer which been accessed before must released. This done resetting bits NEWDAT RMTPND writing value 55DFH into Message Control Register next access this message object will address buffer containing latest incoming message following message will stored second buffer. INTPND buffer currently used must then reset order able correctly quit interrupt service routine. corresponding part interrupt service routine written following way:
case {MCR_M15 0x55DFH MCR_M15 0xFFFDH break; message interrupt release buffer (old) reset INTPND (new) other instructions
Summary
Siemens C167CR microcontroller with on-chip module provides features FULLCAN controller combined with BASIC-CAN option message object Thanks multitude different interrupt sources, information which necessary normal data transfer error handling directly available. these reasons, C167CR easily used data transfer treatment systems. program sequences given this paper examples, which showing efficient powerful interrupt structure this module.
AP1621 12.96
C167CR Interrupt Structure
Reset releases Buffer Buffer released Buffer released access Buffer releases Buffer
allocates Buffer
Store received Message into Buffer
Buffer released Buffer allocated access Buffer
Buffer allocated Buffer released access Buffer
Store received Message into Buffer
Store received Message into Buffer
Buffer allocated Buffer allocated access Buffer
Buffer allocated Buffer allocated access Buffer
Store received message into Buffer MSGLST Allocated Released
releases Buffer
releases Buffer
Store received message into Buffer MSGLST
NEWDAT NEWDAT
RMTPND RMTPND
Figure Handling Last Message Object's Alternating Buffer
AP1621 12.96

C167CR Interrupt Structure Controller Area Network (CAN) module w

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