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Additional file AP082001.EXE available 8-Bit C500 Family Controll


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Microcontrollers ApNote AP0820
Additional file AP082001.EXE available
8-Bit C500 Family Controller C515C
Controller Area Network (CAN) module which been implemented Siemens C515C microcontroller allows communication between several stations (CAN nodes). This document describes functionality, initialisation module. Furthermore, examples concerning interrupt generation error handling will given. Author Jens Barrenscheen Microcontroller Product Definition
Semiconductor Group
12.96,
8-Bit C500 Family Controller C515C
Contents
Page
Principle this application Initialisation Definition Message Object Interrupt Handling Sending Message Error Handling Busoff State Re-Initialisation Appendix CANREG.H INTC515C.H REGC515C.H
AP0820 ApNote Revision History Actual Revision 12.96 Page Page actual Rev. prev.Rel. Previous Revision none (Original Version) Subjects (changes since last release)
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
Principle this application
on-chip CAN-controller provides features FULL-CAN controllers, such message management acceptance filtering input masks) order minimise load. BASICCAN functionality with only message object (nr. available, too. This device supports standard protocol (specification identifier), well extended protocol (specification active, identifier). nodes connected parallel two-wire CAN-bus (CAN_H CAN_L). C515C connected external CAN-bus transceiver signal TxDC RxDC, principle shown figure
C515C with on-chip controller
P4.6 TxDC P4.7 RxDC
node
transceiver
CAN_H CAN_L
node
node
Figure Connection Siemens C515C microcontroller Fifteen different message objects used independently Siemens C515C microcontroller. Each specific identifier; message objects with identical identifiers allowed different types objects defined, transmit objects receive objects. Transmit objects contain data with data length programmable from bytes. They transmitted soon idle after setting corresponding transmit request flag. Receive objects used store data incoming transmit objects with matching identifier. transmission request concerning receive objects causes transmission remote frame order request data transfer from another node with identical identifier.
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
Initialisation
initialisation module made follows: registers located onchip XRAM memory, from address F700H F7FFH. access this special memory space requires modification register XPAGE value F7H. Furthermore, bits XMAP0 XMAP1 register SYSCON must forced "0". initialisation controller begins with setting bits INIT Control Register (F700H) "1". This instruction (CCE=1) enables modification Timing Registers BTR0, located F704H, BTR1 F705H order program desired timing baudrate. should reset after access these registers avoid erroneous modification internal timing. following values have been tested: Table Programming Timing Registers Baudrate BTR0 BTR1 kBaud kBaud kBaud MBaud
This description only focuses application complete message identifiers where masking done. Therefore, Global Mask Registers GMS0, GMS1, UGML0, UGML1, LGML0 LGML1 (F709H F70BH) contain value FFH. controller provides three different types interrupt sources: status interrupts error interrupts message specific interrupts first type generated status change module, which indicated Status Register (F701H). This successful transmission (TXOK set) reception (RXOK set) message object, occurrence error (see bitfield). These interrupt sources enabled setting Control Register which located address F700H. second type error interrupts, which enabled EIE. They generated after change flags EWRN BOFF Status Register. Interrupts third type generated each message object after successful transmission reception. This function enabled setting ,,1" bits TXIE and/or RXIE lowbyte corresponding Message Control Register MCR0_n (F7n0h), with being number corresponding message object (1.15). Control Register globally enables (IE=1) disables interrupt sources module. internal structure C515C requires setting bits ECAN (register IEN2) (register IEN0) ,,1" order service interrupt request. Before initialisation sequence where INIT reset ,,0", message objects must completely initialised declared valid (MSGVAL="0" corresponding Message Control Register) order avoid erroneous data transfers.
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
This structure leads following initialisation procedure
unsigned char interrupts enabled unsigned char status interrupts disabled unsigned char error interrupts disabled void can_init (void) {SYSCON 0xFC; XMAP0=0, XMAP1=0 XPAGE 0xF7; memory space XRAM GMS0 UGML0 LGML0 UMLM0 LMLM0 BTR0 0xFF; 0xFF; 0xFF; 0xFF; 0xFF; GMS1 UGML1 LGML1 UMLM1 LMLM1 0xFF; 0xFF; 0xFF; 0xFF; 0xFF; global mask short global mask long last message mask INIT=1 CCE=1 (enable access baudrate) access timing registers: MHz,250 kBaud CCE=0 (disable access baudrate) clear TXOK RXOK
0x41; 0xC1; 0x01; 0xE7;
BTR1 0x6B;
MCR0_1 0x55; MCR0_15 0x55; IEN2 0x02; (SIE) 0x04; (EIE) 0x08;
message valid message valid enable INIT=0 enable enable enable interrupt (ECAN=1) global can_int can_status_int can_error_int
Definition Message Object
complete definition message object includes determination identifier corresponding Arbitration Registers UAR0_n, UAR1_n, LAR0_n LAR1_n (F7n2H.F7n5H). case transmit objects, desired data bytes have written addresses from F7n7H (DB0_n) F7nEH (DB7_n) message object. interrupt enable bits TXIE RXIE application specific corresponding Message Control Register. They enable interrupt generation successful message transfer. Furthermore, remaining flags INTPND RMTPND ,,0" defined starting conditions. order avoid action message object which currently accessed CPU, CPUUPD before works data this message object. Message Configuration Register MCFG_n located address F7n6. used define character message object, such direction data transfer DIR, data length field DLC. Receive objects (DIR "0") contain direct data, their data length data length transmit objects (DIR "1") defined from bytes. Furthermore, determines whether extended identifier bits (XTD="1"), standard identifier bits (XTD="0") used (see table After last access, CPUUPD cleared, well NEWDAT. This after action these data. Then message object declared valid setting MSGVAL, because module only works valid message objects.
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
Table Programming Message Configuration Register Object Direction transmit receive transmit receive Data length Protocol standard standard extended extended Address F716H F726H F776H F7B6H Value
Table Impact Transmission this message object generates ="0" Receive Object (receives data frames, transmits remote frames) remote frame. corresponding data frame stored this reception. data frame with remote frame with matching identifier matching identifier received received data frame stored. remote frame answered.
="1" data frame. Transmit Object (transmits data frames, receives remote frames)
data frame stored.
remote frame answered corresponding data frame
message object initialisation procedure (objects given example) programmed follows:
definition message standard transmission frame void def_1 (void) {MCR1_1 0xFB; CPUUPD=1 UAR0_1 0x11; UAR1_1 0x20;// identifier 00010001 MCFG_1 0x18; frame definition DB0_1 0x5A; data byte MCR0_1 0xA5; MSGVAL=1, TXIE=1, RXIE=0, INTPND=0 MCR1_1 0x55; RMTPND=0, TXRQ=0, CPUUPD=0, NEWDAT=0 definition message standard remote frame void def_2 (void) {MCR1_2 0xFB; CPUUPD=1 UAR0_2 0x22; UAR1_2 0x20;// identifier 00100010 MCFG_2 0x00; frame definition MCR0_2 0xA9; MSGVAL=1, TXIE=1, RXIE=1, INTPND=0 MCR1_2 0x55; RMTPND=0, TXRQ=0, CPUUPD=0, NEWDAT=0
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
Interrupt Handling
many different interrupt sources generate only global interrupt request, their internal structure must taken into account interrupt service procedure. INTID code Interrupt Register (F702H) indicates which source activated request. status interrupt enabled SIE) error interrupt enabled EIE) cause interrupt with highest priority, which indicated INTID value "1". case status change successful message transfer, flags TXOK RXOK Status Register "1". erroneous message transfer indicated field. case error interrupt, least error flags EWRN BOFF changed. Status Register must read interrupt service procedure order identify interrupt source reset pending interrupt request! flags this register must then cleared software. INTID code "2.16" indicates message specific transmit TXIE="1") receive RXIE="1") interrupt. successful message transfer sets corresponding INTPND "1", which must cleared software reset this interrupt request. priority internal interrupt sources decreases with increasing INTID code. This structure must also taken into account identification interrupt source. example, successful transmission only message object cause independent interrupt requests corresponding TXIE have been "1". While status interrupt (highest priority) serviced INTPND this message object cleared, message interrupt stays still pending. This will generate second interrupt request (message specific) same action. Only INTID code indicates that requested interrupts have been correctly serviced. standard interrupt procedure programmed follows:
interrupt void int_can (void) interrupt CANI {unsigned char status, intreg; while (intreg {status read reset status switch (intreg) {case status error interrupt (SIE) status interrupts (status 0x08) {.}// transmit interrupt (status 0x10) {.}// receive interrupt (status 0x07) {.}// erroneous transfer (EIE) error interrupts (status 0x40) {.}// EWRN changed (status 0x80) {.}// BUSOFF changed break; case message interrupt MCR0_1 0xFD; reset INTPND (status 0x08) transmit interrupt (status 0x10) receive interrupt break; case message interrupt MCR0_2 0xFD; reset INTPND (status 0x08) {.}// transmit interrupt (status 0x10) {.}// receive interrupt break;
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
Sending Message
valid message object sent controller setting TXRQ corresponding Message Control Register. This done following way:
void send_1 (void) transmit message object MCR1_1 0xEF; void send_2 (void) MCR1_2 0xEF; transmit message object
each transferred message (transmit remote frame), receiving nodes answer with dominant ("0") acknowledge signal (Ack) indicate successful message transfer. After transmission remote frame from node node (transmission object with matching identifier) answers sending requested data frame. These actions generate status interrupts concerning flags TXOK RXOK, shown figure node
Figure Successful transmission remote frame (50µs/div)
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
several TXRQ bits activated same time, controller starts sending object with highest priority (lowest number). transmission request only serviced corresponding message object valid (MSGVAL="1") currently accessed (CPUUPD="0"). case TXRQ being ,,1" while CPUUPD still ,,1", transmission request taken into account after CPUUPD been cleared therefore need repeated CPU. Error Handling
After detection transfer error, sending node immediately (one time) stops transmission current message object sends error frame consisting dominant bits. They detected other nodes, which then answer emission another dominant bits. After this sequence, remains logic level bits, before controller automatically restarts transmission disturbed message object. example short disturbance with only erroneous shown fig. this case, error counter sending node incremented decremented after each successful message transfer. interrupt generated each transfer error been "1". code bitfield contains information about error type. given example (see figure status interrupt generated Bit1Error. status interrupt which shown figure generated after successful message transfer TxOK been tested.
Figure Status interrupt generation Bit1Error (50µs/div)
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
Busoff State Re-Initialisation
Each transfer error causes incrementation error counters (transmit error counter receive error counter). case longer disturbances, they also incremented each time sequence erroneous bits occurs. When counter reaches value EWRN "1". more errors occur error counter reaches 255, controller stops actions goes into busoff state. This indicated BOFF flag changing "1", which shown figure
EWRN
BOFF status interrupts
Figure EWRN, BOFF Re-Initialisation (5ms/div)
error interrupt generated either EWRN BOFF change status. re-initialisation module ensure normal functionality achieved clearing INIT, which automatically when entering busoff state. During busoff recovery bitfield contains code representing Bit0Error each time sequence recessive bits been monitored. this code generate status interrupt, should cleared busoff state order avoid higher load. busoff state detected using error interrupts (EIE="1") then desired interrupt mode.
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
Figure Message transfer just before busoff state (200µs/div)
controller stops actions goes busoff, disturbed message repeated immediately, fig. After successful busoff recovery (started resetting INIT), automatically repeated without involving corresponding TxRQ remains set, figure This functionality avoids loss messages temporary transfer errors. automatic repetition last erroneous message after busoff recovery desired, disabled resetting corresponding TxRQ software.
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
Figure Automatic message repetition after busoff state (200µs/div)
Siemens C515C microcontroller with on-chip module provides features FULL-CAN controller. This includes independent message objects with standard extended identifiers, which transferred with maximal baudrate MBaud. Thanks multitude different interrupt sources, information which necessary normal data transfer error handling directly available. these reasons, C515C easily used data transfer treatment systems.
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
Appendix CANREG.H
extern unsigned char pdata canreg[256]; /****************************/ Register Declaration Control Registers #define #define #define #define BTR0 #define BTR1 #define GMS0 #define GMS1 #define UGML0 #define UGML1 #define LGML0 #define LGML1 #define UMLM0 #define UMLM1 #define LMLM0 #define LMLM1 canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[
Message Registers #define MCR0_M1 canreg[ #define MCR1_M1 canreg[ #define UAR0_M1 canreg[ #define UAR1_M1 canreg[ #define LAR0_M1 canreg[ #define LAR1_M1 canreg[ #define MCFG_M1 canreg[ #define DB0_M1 canreg[ #define DB1_M1 canreg[ #define DB2_M1 canreg[ #define DB3_M1 canreg[ #define DB4_M1 canreg[ #define DB5_M1 canreg[ #define DB6_M1 canreg[ #define DB7_M1 canreg[ Message Registers #define MCR0_M2 canreg[ #define MCR1_M2 canreg[ #define UAR0_M2 canreg[ #define UAR1_M2 canreg[ #define LAR0_M2 canreg[ #define LAR1_M2 canreg[ #define MCFG_M2 canreg[ #define DB0_M2 canreg[ #define DB1_M2 canreg[ #define DB2_M2 canreg[ #define DB3_M2 canreg[ #define DB4_M2 canreg[ #define DB5_M2 canreg[ #define DB6_M2 canreg[ #define DB7_M2 canreg[ Message Registers #define MCR0_M3 canreg[ #define MCR1_M3 canreg[ #define UAR0_M3 canreg[ #define UAR1_M3 canreg[ #define LAR0_M3 canreg[ #define LAR1_M3 canreg[
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
#define #define #define #define #define #define #define #define #define
MCFG_M3 DB0_M3 DB1_M3 DB2_M3 DB3_M3 DB4_M3 DB5_M3 DB6_M3 DB7_M3
canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[
Message Registers #define MCR0_M4 canreg[ #define MCR1_M4 canreg[ #define UAR0_M4 canreg[ #define UAR1_M4 canreg[ #define LAR0_M4 canreg[ #define LAR1_M4 canreg[ #define MCFG_M4 canreg[ #define DB0_M4 canreg[ #define DB1_M4 canreg[ #define DB2_M4 canreg[ #define DB3_M4 canreg[ #define DB4_M4 canreg[ #define DB5_M4 canreg[ #define DB6_M4 canreg[ #define DB7_M4 canreg[ Message Registers #define MCR0_M5 canreg[ #define MCR1_M5 canreg[ #define UAR0_M5 canreg[ #define UAR1_M5 canreg[ #define LAR0_M5 canreg[ #define LAR1_M5 canreg[ #define MCFG_M5 canreg[ #define DB0_M5 canreg[ #define DB1_M5 canreg[ #define DB2_M5 canreg[ #define DB3_M5 canreg[ #define DB4_M5 canreg[ #define DB5_M5 canreg[ #define DB6_M5 canreg[ #define DB7_M5 canreg[
Message Registers #define MCR0_M6 canreg[ #define MCR1_M6 canreg[ #define UAR0_M6 canreg[ #define UAR1_M6 canreg[ #define LAR0_M6 canreg[100] #define LAR1_M6 canreg[101] #define MCFG_M6 canreg[102] #define DB0_M6 canreg[103] #define DB1_M6 canreg[104] #define DB2_M6 canreg[105] #define DB3_M6 canreg[106] #define DB4_M6 canreg[107] #define DB5_M6 canreg[108] #define DB6_M6 canreg[109] #define DB7_M6 canreg[110] Message Registers #define MCR0_M7 canreg[112] #define MCR1_M7 canreg[113] #define UAR0_M7 canreg[114] #define UAR1_M7 canreg[115] #define LAR0_M7 canreg[116]
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
#define #define #define #define #define #define #define #define #define #define
LAR1_M7 MCFG_M7 DB0_M7 DB1_M7 DB2_M7 DB3_M7 DB4_M7 DB5_M7 DB6_M7 DB7_M7
canreg[117] canreg[118] canreg[119] canreg[120] canreg[121] canreg[122] canreg[123] canreg[124] canreg[125] canreg[126]
Message Registers #define MCR0_M8 canreg[128] #define MCR1_M8 canreg[129] #define UAR0_M8 canreg[130] #define UAR1_M8 canreg[131] #define LAR0_M8 canreg[132] #define LAR1_M8 canreg[133] #define MCFG_M8 canreg[134] #define DB0_M8 canreg[135] #define DB1_M8 canreg[136] #define DB2_M8 canreg[137] #define DB3_M8 canreg[138] #define DB4_M8 canreg[139] #define DB5_M8 canreg[130] #define DB6_M8 canreg[131] #define DB7_M8 canreg[132] Message Registers #define MCR0_M9 canreg[144] #define MCR1_M9 canreg[145] #define UAR0_M9 canreg[146] #define UAR1_M9 canreg[147] #define LAR0_M9 canreg[148] #define LAR1_M9 canreg[149] #define MCFG_M9 canreg[150] #define DB0_M9 canreg[151] #define DB1_M9 canreg[152] #define DB2_M9 canreg[153] #define DB3_M9 canreg[154] #define DB4_M9 canreg[155] #define DB5_M9 canreg[156] #define DB6_M9 canreg[157] #define DB7_M9 canreg[158] Message Registers #define MCR0_M10 canreg[160] #define MCR1_M10 canreg[161] #define UAR0_M10 canreg[162] #define UAR1_M10 canreg[163] #define LAR0_M10 canreg[164] #define LAR1_M10 canreg[165] #define MCFG_M10 canreg[166] #define DB0_M10 canreg[167] #define DB1_M10 canreg[168] #define DB2_M10 canreg[169] #define DB3_M10 canreg[170] #define DB4_M10 canreg[171] #define DB5_M10 canreg[172] #define DB6_M10 canreg[173] #define DB7_M10 canreg[174] Message Registers #define MCR0_M11 canreg[176] #define MCR1_M11 canreg[177] #define UAR0_M11 canreg[178] #define UAR1_M11 canreg[179]
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
#define #define #define #define #define #define #define #define #define #define #define
LAR0_M11 LAR1_M11 MCFG_M11 DB0_M11 DB1_M11 DB2_M11 DB3_M11 DB4_M11 DB5_M11 DB6_M11 DB7_M11
canreg[180] canreg[181] canreg[182] canreg[183] canreg[184] canreg[185] canreg[186] canreg[187] canreg[188] canreg[189] canreg[190]
Message Registers #define MCR0_M12 canreg[192] #define MCR1_M12 canreg[193] #define UAR0_M12 canreg[194] #define UAR1_M12 canreg[195] #define LAR0_M12 canreg[196] #define LAR1_M12 canreg[197] #define MCFG_M12 canreg[198] #define DB0_M12 canreg[199] #define DB1_M12 canreg[200] #define DB2_M12 canreg[201] #define DB3_M12 canreg[202] #define DB4_M12 canreg[203] #define DB5_M12 canreg[204] #define DB6_M12 canreg[205] #define DB7_M12 canreg[206] Message Registers #define MCR0_M13 canreg[208] #define MCR1_M13 canreg[209] #define UAR0_M13 canreg[210] #define UAR1_M13 canreg[211] #define LAR0_M13 canreg[212] #define LAR1_M13 canreg[213] #define MCFG_M13 canreg[214] #define DB0_M13 canreg[215] #define DB1_M13 canreg[216] #define DB2_M13 canreg[217] #define DB3_M13 canreg[218] #define DB4_M13 canreg[219] #define DB5_M13 canreg[220] #define DB6_M13 canreg[221] #define DB7_M13 canreg[222] Message Registers #define MCR0_M14 canreg[224] #define MCR1_M14 canreg[225] #define UAR0_M14 canreg[226] #define UAR1_M14 canreg[227] #define LAR0_M14 canreg[228] #define LAR1_M14 canreg[229] #define MCFG_M14 canreg[230] #define DB0_M14 canreg[231] #define DB1_M14 canreg[232] #define DB2_M14 canreg[233] #define DB3_M14 canreg[234] #define DB4_M14 canreg[235] #define DB5_M14 canreg[236] #define DB6_M14 canreg[237] #define DB7_M14 canreg[238] Message Registers #define MCR0_M15 canreg[240] #define MCR1_M15 canreg[241] #define UAR0_M15 canreg[242]
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
#define #define #define #define #define #define #define #define #define #define #define #define
UAR1_M15 LAR0_M15 LAR1_M15 MCFG_M15 DB0_M15 DB1_M15 DB2_M15 DB3_M15 DB4_M15 DB5_M15 DB6_M15 DB7_M15
canreg[243] canreg[244] canreg[245] canreg[246] canreg[247] canreg[248] canreg[249] canreg[250] canreg[251] canreg[252] canreg[253] canreg[254]
INTC515C.H
,,INTC515C.H" symbolic interruptnumbers C151C-interrupt routines #define EXTI0 (03H) external interrupt #define TIMER0 (0BH) Timer Overflow #define EXTI1 (13H) external interrupt #define TIMER1 (1BH) Timer Overflow #define SINT (23H) serial interrupt #define TIMER2 (2BH) Timer Overflow #define ADCI (43H) A/D-Converter interrupt #define EXTI2 (4BH) external interrupt #define EXTI3 (53H) external interrupt #define EXTI4 (5BH) external interrupt #define EXTI5 (63H) external interrupt #define EXTI6 (6BH) external interrupt #define (7BH) Power Down interrupt #define CANI (8BH) interrupt #define SSCI (93H) interrupt #define EXTI7 (A3H) external interrupt #define EXTI8 (ABH) external interrupt
REGC515C.H
Copyright SIEMENS 1996 rights reserved. Register Declarations C515C Processor /**********************/ BYTE Register 0x80; 0x81; 0x82; 0x83; WDTREL 0x86; PCON 0x87; TCON 0x88; TMOD 0x89; 0x8A; 0x8B; 0x8C; 0x8D; XPAGE DPSEL SSCCON 0x90; 0x91; 0x92; 0x93; 0x94;
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
SSCMOD SCON SBUF IEN2 IEN0 SRELL SCIEN SYSCON IEN1 SRELH IRCON CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 T2CON CRCL CRCH ADCON0 ADDATH ADDATL ADCON1 CCPL CCPH DIR5
0x95; 0x96; 0x98; 0x99; 0x9A; 0xA0; 0xA8; 0xA9; 0xAA; 0xAB; 0xAC; 0xB0; 0xB1; 0xB8; 0xB9; 0xBA; 0xC0; 0xC1; 0xC2; 0xC3; 0xC4; 0xC5; 0xC6; 0xC7; 0xC8; 0xCA; 0xCB; 0xCC; 0xCD; 0xD0; 0xD8; 0xD9; 0xDA; 0xDB; 0xDC; 0xDD; 0xDE; 0xDF;
0xE0; 0xE8; 0xF0; 0xF8; 0xF8;
/*********************/ Register TCON sbit sbit sbit sbit sbit sbit sbit sbit SCON sbit sbit sbit sbit 0x8F; 0x8E; 0x8D; 0x8C; 0x8B; 0x8A; 0x89; 0x88; 0x9F; 0x9E; 0x9D; 0x9C;
Semiconductor Group
AP0820 12.96
8-Bit C500 Family Controller C515C
sbit sbit sbit sbit IEN0 sbit sbit sbit sbit sbit sbit sbit sbit IEN1 sbit EXEN2 sbit SWDT sbit EX6M sbit sbit sbit sbit sbit EADC sbit sbit sbit sbit sbit INT1 sbit INT0 sbit sbit T2CON sbit T2PS sbit I3FR sbit I2FR sbit T2R1 sbit T2R0 sbit T2CM sbit T2L1 sbit T2I0 IRCON sbit EXF2 sbit sbit IEX6 sbit IEX5 sbit IEX4 sbit IEX3 sbit IEX2 sbit IADC ADCON0 sbit sbit sbit ADEX sbit sbit sbit sbit sbit sbit sbit sbit sbit sbit sbit sbit sbit
0x9B; 0x9A; 0x99; 0x98; 0xAF; 0xAE; 0xAD; 0xAC; 0xAB; 0xAA; 0xA9; 0xA8; 0xBF; 0xBE; 0xBD; 0xBC; 0xBB; 0xBA; 0xB9; 0xB8; 0xB7; 0xB6; 0xB5; 0xB4; 0xB3; 0xB2; 0xB1; 0xB0; 0xCF; 0xCE; 0xCD; 0xCC; 0xCB; 0xCA; 0xC9; 0xC8; 0xC7; 0xC6; 0xC5; 0xC4; 0xC3; 0xC2; 0xC1; 0xC0; 0xDF; 0xDE; 0xDD; 0xDC; 0xDB; 0xDA; 0xD9; 0xD8; 0xD7; 0xD6; 0xD5; 0xD4; 0xD3; 0xD2; 0xD1; 0xD0;
Semiconductor Group
AP0820 12.96

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