PBLK ADCIN Signal Processor Electronic Cameras AD9802 FUNCTI

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PBLK ADCIN Signal Processor Electronic Cameras AD9802 FUNCTI

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FEATURES 10-Bit, MSPS Converter MSPS Full Speed Correlated Double Sampler (CDS) Noise, Wideband Internal Voltage Reference Missing Codes Guaranteed Single Supply Operation Power CMOS: 48-Terminal TQFP Package
PBLK ADCIN
Signal Processor Electronic Cameras AD9802
FUNCTIONAL BLOCK DIAGRAM
CLPDM PGACONT1 PGACONT2 ADCCLK TIMING GENERATOR DOUT DRVDD
CLAMP
CLAMP REFERENCE
AD9802
DVDD
CMLEVEL STBY CLPOB ADCMODE ACVDD ADVDD
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
AD9802 complete signal processor developed electronic cameras. suitable both camcorder consumer-level still camera applications. signal processing chain comprised high speed CDS, variable gain 10-bit ADC. Required clamping circuitry onboard voltage reference provided well direct input. AD9802 operates from single supply with typical power consumption AD9802 packaged space saving 48-terminal thin quad flatpack (TQFP) specified over operating temperature range +70°C.
On-Chip Input Clamp Clamp circuitry high speed correlated double sampler allow simple ac-coupling interface sensor full MSPS conversion rate. On-Chip AD9802 includes low-noise, wideband amplifier with analog variable gain from 31.5 (linear dB). Direct Input direct input 10-bit converter provided digitizing video signals. 10-Bit, High Speed Converter linear 10-bit capable digitizing signals full MSPS conversion rate. Typical missing code performance guaranteed. Power power-down, AD9802 consumes fraction power presently available multichip solutions. Digital Functionality AD9802 offers three-state digital output control. Small Package Packaged 48-terminal, surface-mount thin quad flatpack, AD9802 well suited very compact, headroom designs.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1997
AD9802-SPECIFICATIONS unless otherwise noted)
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE (For Functional Operation) ACVDD ADVDD DVDD DRVDD POWER SUPPLY CURRENT ACVDD ADVDD DVDD DRVDD POWER CONSUMPTION Normal Operation Power-Down Mode MAXIMUM SHP, SHD, ADCCLK RATE Resolution Differential Nonlinearity Missing Codes ADCCLK Rate Reference Voltage Reference Bottom Voltage Input Range Maximum Input Signal Pixel Rate PGA1 Maximum Gain High Gain Medium Gain Minimum Gain CLAMP (During CLPOB. Only Stable over Range Average Black Level Pixel-to-Pixel Offset (See Black Level Clamping Description)
(TMIN TMAX with ACVDD 3.15 ADVDD 3.15 DVDD 3.15 DRVDD 3.15
3.00 3.00 3.00 3.00 3.15 3.15 3.15 3.15 39.5 14.6 0.07 3.50 3.50 3.50 3.50 Units Bits LSBs 1.75 1.25 31.5 LSBs LSBs
GUARANTEED
14.5 -4.0
23.5
NOTES test conditions: maximum gain PGACONT1 PGACONT2 high gain PGACONT1 PGACONT2 medium gain PGACONT1 PGACONT2 minimum gain PGACONT1 PGACONT2 Specifications subject change without notice.
DIGITAL SPECIFICATIONS noted)
Parameter LOGIC INPUTS High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Level Output Voltage
(TMIN TMAX with ACVDD 3.15 ADVDD 3.15 DVDD 3.15 DRVDD 3.15 unless otherwise
Symbol Units REV.
AD9802 TIMING SPECIFICATIONS noted)
Parameter ADCCLK Clock Period ADCCLK Hi-Level Period ADCCLK Lo-Level Period SHP, Clock Period SHP, Minimum Pulse Width Rising Edge Rising Edge Digital Output Delay
(TMIN TMAX with ACVDD 3.15 ADVDD 3.15 DVDD 3.15 DRVDD 3.15 unless otherwise
55.6 24.8 24.8 55.6 12.5 27.8 27.8 Units
Digital Output Data Control
PBLK
MODE1
MODE2
Digital Output Data (D9-D0) Normal Operation High Impedance
ABSOLUTE MAXIMUM RATINGS*
Parameter ADVDD ACVDD DVDD DRVDD SHP, ADCCLK, CLPOB, CLPDM PGACONT1, PGACONT2 PIN, DOUT VRT, CLAMP_BIAS CCDBYP1, CCDBYP2 STBY MODE1, MODE2 DRVSS, DVSS, ACVSS, ADVSS Junction Temperature Storage Temperature Lead Temperature sec)
With Respect ADVSS, SUBST ACVSS, SUBST DVSS, DSUBT DRVSS, DSUBST DSUBST DSUBST SUBST SUBST DSUBST SUBST SUBST SUBST DSUBST SUBST SUBST, DSUBST
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
DVDD DVDD ACVDD ACVDD DRVDD ADVDD ACVDD ACVDD DVDD ADVDD +0.3 +150 +150 +300
Units
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum ratings extended periods affect device reliability.
ORDERING GUIDE
Model AD9802JST
Temperature Range +70°C
Package Description 48-Terminal Plastic Thin Quad Flatpack
Package Option ST-48
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD9802 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD9802
CONFIGURATION
ADCMODE ADVSS SHABYP CMLEVEL
ADCIN TEST2 TEST1 ACVDD CLAMP_BIAS ACVSS PGACONT2 PGACONT1 CCDBYP1 CCDBYP2
ADVDD
ADVSS
ADVSS (LSB) (MSB) DRVDD CONNECT
IDENTIFIER
AD9802
VIEW (Not Scale)
ADCCLK
DSUBST
CLPDM
DRVSS
DVSS
DVDD
STBY PBLK
MODE1 MODE2
SUBST
FUNCTION DESCRIPTIONS
2-11
Name ADVSS D0-D9 DRVDD DRVSS DSUBST DVSS ADCCLK DVDD STBY PBLK CLPOB CLPDM DVSS CCDBYP2 CCDBYP1 PGACONT1 PGACONT2 ACVSS CLAMP_BIAS ACVDD TEST1, TEST2 ADCIN CMLEVEL SHABYP MODE2 MODE1 ADCMODE ADVDD ADVSS SUBST
Type
Description Analog Ground Digital Data Outputs: LSB, Digital Driver Supply Digital Driver Ground Digital Substrate Digital Ground Sample Clock Input Digital Supply Power-Down (Active High) Pixel Blanking (Active Low) Black Level Restore Clamp (Active Low) Reference Sample Clock Input Data Sample Clock Input Input Clamp (Active Low) Digital Ground Bypass. Decouple analog ground through Input. AC-Couple output through Input. above. Bypass. Decouple analog ground through Coarse Gain Control (0.3 V-2.7 Decoupled analog ground through Fine Gain Control Analog Ground Clamp Bias Level. Decouple analog ground through Analog Supply Reserved Test Pins. Should left pulled high ACVDD. Direct Analog Input (See Driving Direct Input) Common-Mode Level. Decouple analog ground through Internal Bias Level. Decouple analog ground through Test Mode Control (See Digital Output Data Control.) Test Mode Control (See Digital Output Data Control.) Input Control. Logic CDS/PGA, high direct input. Connect Analog Supply Analog Ground Substrate. Connect analog ground. Bottom Reference Bypass. Decouple analog ground through Reference Bypass
NOTE Type: Analog Input, Analog Output, Digital Input, Digital Output, Power.
CLPOB
DVSS
REV.
AD9802
EQUIVALENT INPUT CIRCUITS
DVDD DRVDD
ACVDD
10pF
SUBST ACVSS
Figure (DIN) (PIN)
ACVDD DVSS DRVSS PGACONT1
Figure Pins 2-11 (DB0-DB9)
DVDD
SUBST PGACONT2 ACVDD
Figure (PGACONT1) (PGACONT2)
ACVDD
DSUBST
DVSS
Figure (SHP) (SHD)
DVDD
SUBST
ACVSS
Figure (CLAMP BIAS)
DSUBST DVSS
ADVDD 1.1k
Figure (ADCCLK)
ADVDD
SUBST
ADVSS
9.3k ADVSS
Figure (VRT) (VRB)
ACVDD
Figure (CMLEVEL)
ACVDD
SUBST
SUBST
ACVSS
Figure (ADCIN) (SHABYP)
Figure (CCDBYP2) (CCDBYP1)
REV.
AD9802
EFFECTIVE PIXEL INTERVAL BLACK LEVEL INTERVAL BLANKING INTERVAL DUMMY BLACK INTERVAL EFFECTIVE PIXEL INTERVAL
CLPOB
PBLK
CLPDM
ADCCLK
DATA
NOTES: CLPDM CLPOB OVERWRITE PBLK CLAMP TIMING NEEDS ADJUSTED RELATIVE CCD'S BLACK PIXELS RECOMMENDED PULSE WIDTH CLPDM
Figure Typical Horizontal Interval Timing
REV.
AD9802
SIGNAL (DELAYED MATCH ACTUAL SAMPLING EDGE)
ACTUAL SAMPLING EDGE 35ns ADCCLK 35ns
DIGITAL
DATA DATA
OUTPUT LOAD 20pF
OUTPUT DELAY 15ns HOLD TIME INTERNAL CLOCK DELAY LATENCY CYCLES
Figure Timing Diagram
PRE-ADC OUTPUT LATCH
10ns
PRE-ADC OUTPUT LATCH DATA TRANSITION ADCCLK 20ns INHIBITED PERIOD ADCCLK RISING EDGE RISING EDGE ANYWHERE THIS PERIOD
Figure ADCCLK Timing Edge
REV.
AD9802
THEORY OPERATION Introduction
AD9802 10-bit analog-to-digital interface cameras. block level diagram system shown Figure device includes correlated double sampler (CDS), dB-31 variable gain amplifier (PGA), black level correction loop, input clamp voltage reference. only external analog circuitry required system level emitter follower buffer between output AD9802 inputs.
CLAMP BLACK LEVEL 10-BIT
Programmable Gain Amplifier (PGA) on-chip provides (linear gain range 31.5 typical gain characteristic plot shown Figure Only range from intended actual use.
GAIN
GAIN
PGACONT1 Volts
Figure
Correlated Double Sampling (CDS)
important high performance systems method removing several types noise. Basically, samples output taken: with signal present (data) without (reference). Subtracting these samples removes noise that common to-or correlates with-both. Figure shows block diagram AD9802's CDS. blocks directly driven input sampling function performed passively, without amplifiers. This implementation relies off-chip emitter follower buffer drive sampling capacitors. Only capacitor time seen input pin. AD9802 actually uses circuits "ping-pong" fashion allow system more acquisition time. this way, output from blocks will valid entire clock cycle. Thus, bandwidth requirement subsequent gain stage reduced compared that single channel system. This lower bandwidth translates lower power noise.
FROM
Figure
shown Figure control provided through PGACONT1 PGACONT2 inputs. PGACONT1 provides coarse, PGACONT2 fine (1/16), gain control.
PGACONT1 PGACONT2
PGACONT1 COARSE CONTROL PGACONT2 FINE (1/16) CONTROL
Figure
Black Level Clamping
correct processing, signal must referenced well established "black level" AD9802. edge CCD, there collection pixels covered with metal prevent light penetration. read out, these "black pixels" provide calibration signal that used establish black level. feedback loop shown Figure closed around during calibration interval (CLPOB LOW) black level. black pixels being processed, integrator block measures difference between input level desired reference level. This difference, error, signal amplified passed block where added incoming pixel data. result this process, black pixels digitized range, taking maximum advantage available linear range system.
10pF
Figure
CLPOB
INTEGRATOR
Figure
REV.
AD9802
actual implementation this loop slightly more complicated shown Figure Because there separate blocks, black level feedback loops required offset voltages developed. Figure also shows additional block feedback loop labeled "RPGA." RPGA uses same control inputs PGA, inverse gain. RPGA functions attenuate same factor amplifies, keeping gain bandwidth loop constant. There exists unavoidable mismatch offset voltages used correct both blocks. This mismatch causes slight difference offset level even pixels, called "pixel-to-pixel offset" (see Specifications). pixel-to-pixel offset output referred specification, because black level correction done using output PGA.
CDS1 CDS2 CLPOB RPGA2 RPGA1 INT2 INT1
avoid problems associated with processing these transients, AD9802 includes input blanking function. When active (PBLK LOW) this function stops operation allows user disconnect inputs from buffer. input voltage exceeds supply rail more than then protection diodes will turned increasing current flow into AD9802 (see Equivalent Input Circuits). Such voltage levels should externally clamped prevent device damage reliability degradation.
10-Bit Analog-to-Digital Converter (ADC)
employs multibit pipelined architecture that well suited high throughput rates while being both area power efficient. multistep pipeline presents input capacitance resulting lower on-chip drive requirements. fully differential implementation used overcome headroom constraints single power supply.
Direct Input
CONTROL
analog processing circuitry bypassed AD9802. When ADCMODE (Pin taken high, ADCIN provides direct input SHA. This feature allows digitization signals that require gain adjustment. output disconnected from when ADCMODE taken high.
Differential Reference
Figure
Input Bias Level Clamping
buffered output connected AD9802 through external coupling capacitor. bias point this coupling capacitor established during clamping (CLPDM LOW) period using "dummy clamp" loop shown Figure When closed around CDS, this loop establishes desired bias point coupling capacitor.
CLPDM
AD9802 includes reference based differential, continuous-time bandgap cell. external bypass capacitor reduces reference drive requirements, thus lowering power dissipation. differential architecture chosen ability reject supply substrate noise. Recommended decoupling shown Figure
INPUT CLAMP
Figure
BLACK LEVEL
Internal Timing
Figure
Input Blanking
some applications, AD9802's input exposed large signals from CCD. These signals very large, relative AD9802's input range, could thus saturate on-chip circuit blocks. Recovery time from such saturation conditions could substantial.
AD9802's on-chip timing circuitry generates clocks necessary operation blocks. user needs only synchronize clocks with waveform, other timing handled internally. ADCCLK signal used strobe output data, adjusted accommodate desired timing.
REV.
AD9802
APPLICATIONS INFORMATION Generating Clock Signals
RBIAS RBIAS ADCIN SHABYP 1.5V
best performance, AD9802 should driven logic levels. shown Equivalent Input Circuits, logic ADCCLK will turn protection diode DVDD, increasing current flow into this pin. result, noise power dissipation will increase. clock inputs, SHD, have additional protection withstand direct levels. External clamping diodes resistor dividers used translate levels levels, lowest power dissipation achieved with logic transceiver chip. National Semiconductor's 74LVX4245 provides level shift eight clock signals, three-state option, features power consumption. Philips Semiconductor Quality also manufacture similar devices. Driving Direct Input AD9802 used "direct input" mode, which input signal bypasses input clamp, PGA, sent directly sample hold amplifier (SHA) ADC. There several methods that used drive direct input. enable direct input mode operation, ADCMODE (Pin taken logic high. This will internally disconnect output from input, connect ADCIN (Pin input. differential input, consisting ADCIN (Pin positive input, SHABYP (Pin negative input. Both pins must properly biased. Figures through show four circuits driving direct input. Decoupling capacitors shown CML, VRT, SHABYP pins.
ADCIN SHABYP 1.5V
AD9802
ADCMODE
Figure AC-Coupled Input
Figure shows alternative ac-coupled configuration. connecting SHABYP CML, bias (ADCIN) will internally track same voltage, automatically setting input bias level. With given input capacitor value, CIN, time constant this configuration will dependent sampling frequency Specifically: (CIN /FS)
ADCIN SHABYP 1.5V
AD9802
ADCMODE
Figure "Auto Bias" AC-Coupled Input
Figure shows true differential drive circuit. Each input would p-p, achieve full-scale input ADC. common-mode input range this configuration extends from about This circuit could also implemented with coupling, similar Figure
500mV ADCIN 500mV
AD9802
ADCMODE
SHABYP
AD9802
ADCMODE
Figure DC-Coupled Input
Figure single-ended, dc-coupled circuit. SHABYP connected (1.5 establish midpoint bias. input signal should centered around CML. Figure shows ac-coupled configuration, where both inputs biased CML. input capacitor bias resistors should sized appropriate high pass cutoff frequency application. minimize differential offset voltage input bias currents, both resistors should equal.
Figure Differential Input
Figure shows video clamp circuit which used with direct mode AD9802 (supplies decoupling shown). circuit will clamp reference black level incoming video signal 1.25 With SHABYP connected 1.75 (VRT), ADCIN range spans from 1.25 2.25 accomplish this, CLAMP pulse should asserted during horizontal sync interval, when video reference black level. logic high applied gate SD210 will turn device, input capacitor will charge provide 1.25 ADCIN AD9802. Other appropriate NMOS devices substituted SD210. AD8047 requires supplies; appropriate single supply amps substituted. size capacitor should meet acquisition time REV.
-10-
AD9802
droop specifications needed. capacitor value 0.01 will result droop less than across video line, requires only CLAMP pulse charge larger capacitor used reduce droop, then longer CLAMP pulse necessary.
AMPLITUDE
ADCIN
CLAMP
SHABYP SD210
AD8047
ADCMODE
AD9802
-100
FREQUENCY
Figure Direct Mode Typical FFT; 3.58 MHz,
Figure Video Clamp Circuit
Figures 27-29 show typical linearity distortion performance AD9802 direct mode.
Digitally Programmable Gain Control
AD9802's controlled analog input voltage some applications, digital gain control preferable. Figure shows circuit using Analog Devices' AD8402 Digital Potentiometer generate control voltage. AD8402 functions individual potentiometers, with serial digital interface program position each wiper over positions. device will operate with supplies, features power-down mode reset function. keep external components minimum, ends "potentiometers" tied ground used coarse gain adjust, PGACONT1, with steps about dB/LSB. other used fine gain control, PGACONT2, capable around 0.01 steps eight bits used. outputs should filtered with larger capacitors minimize noise into PGACONT pins AD9802.
1023
Figure Direct ADC-Mode Typical
PGACONT1
PGACONT2
AD8402-10
SHDN
1023
Figure Digital Control
Figure Direct ADC-Mode Typical
REV.
-11-
AD9802
disadvantage this circuit that control voltage will supply dependent. additional precision required, external used amplify VREFT (1.75 VREFB (1.25 pins AD9802 desired voltage level. These reference voltages stable over operating supply range AD9802. power, cost, rail-to-rail output amplifiers like AD820, OP150 OP196 specified operation. Alternatively, precision voltage reference used. REF193 from Analog Devices features power, dropout performance, maintaining output with minimum supply when lightly loaded.
Power Grounding Recommendations AD9801/AD9802 EVALUATION BOARD DESCRIPTION Power Supply Connectors
VDD: supply AD9801/AD9802. Data sheet specifications given +3.15 Operational range from +3.5 AVCC: supply AD8047 buffer, PGACONT potentiometers. buffer amplifier needed, AVCC connected supply. AVSS: supply AD8047 buffer. buffer amplifier needed, AVSS connected AGND: This analog ground plane AD9801/AD9802 buffer amplifier. ground planes already connected together place evaluation board. DGND: This digital ground plane LVXC3245 transceivers. ground planes already connected together place evaluation board. +3D: digital supply LVXC3245 transceivers. +3/5D: digital supply LVXC3245 transceivers. This voltage determines logic compatibility evaluation board. clock levels digital output levels used, connect clock levels digital output levels used, connect DIN: Unbuffered input AD9801/AD9802. This input terminated which removed termination required. Input Configurations more information. VIN: Input AD8047 buffer amplifier. This input terminated which removed termination required. This used buffer drive AD9801/AD9802, buffer driving direct input AD9802. Input Configurations AD9802 data sheet more information. CLPDM CLPOB PBLK ADCCLK
AD9802 should treated analog component when used system. same power supply ground plane should used pins. two-ground system, this requires that digital supply pins decoupled analog ground plane digital ground pins connected analog ground best noise performance. pins AD9802 connected system digital ground, then noise capacitively couple inside AD9802 (through package parasitics) from digital circuitry analog circuitry. Separate digital supplies used, particularly slightly different driver supplies needed, digital power pins should still decoupled same point digital ground pins (analog ground plane). AD9802 digital outputs need drive substantial load, buffer should used AD9802's outputs, with buffer referenced system digital ground. some cases, when system digital noise substantial, acceptable split ground pins AD9802 separate analog digital ground planes. this done, sure connect ground pins together AD9802. further improve performance, isolating driver supply DRVDD from DVDD with ferrite bead help reduce kickback effects during major code transitions. Alternatively, damping resistors digital outputs will reduce output rise times, reducing kickback effect.
Evaluation Board
Input Connectors
evaluation board AD9802 available. board includes circuitry manual gain adjustment, input signal buffering, logic level translation digital signals. Documentation AD9802-EB included, consisting board description, schematic layout information.
Clock Connectors
clock inputs terminated buffered LVXC3245 transceiver. supply level determines input clock level compatibility. outputs LVXC3245 always send clock levels AD9801/AD9802.
-12-
REV.
AD9802
Jumper Descriptions Test Point Descriptions
JP10
Connect bypass input coupling capacitor C18. Connect short (Pins AD9801) together. Connects level wiper Connect short input coupling capacitor ground, test purposes. Connects output buffer amplifier AD9801/AD9802 input. Connects AD9801/AD9802's DRVDD supply through ferrite bead FB6. Connects AD9801/AD9802's DRVDD supply. Connects output AD8047 direct input AD9802. This jumper should never connected AD9801-EB. Selects regular camera mode operation AD9802. This jumper should always place AD9801-EB. Selects direct input mode AD9802. This jumper should never connected AD9801-EB.
TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18
Input signal Input signal PIN/DIN AD9801/AD9802. PGACONT1 voltage. PGACONT2 voltage. STANDBY pin, pull high enable power-down mode. CLPDM AD9801/AD9802. AD9801/AD9802. AD9801/AD9802. CLPOB AD9801/AD9802. PBLK AD9801/AD9802. ADCCLK AD9801/AD9802. AVCC AVSS AGND DGND +3/5D
Prototype
left hole prototyping area connected AGND. bottom right hole connected AVCC.
Input Configurations
Standard Input Grounded Input Test Buffered Input* Direct Input (9802 only)
Input none
open short open open short open open short open don't care.
open short open
open open short
open open open short
short short short open
JP10 open open open short
*When using buffer amplifier, must connected AVCC AVSS, should removed.
REV.
-13-
AD9802
JP10 0.01
MODE1
0.01
ADVSS (LSB)
ADCMODE
MODE2 SHABYP CMLEVEL
ADVSS ADVSS
SUBST
ADVDD ADVDD
ADCIN TEST2
TEST1 ACVDD
AD9802
CLAMP_BIAS ACVSS PGACONT2 PGACONT1 CCDBYP1 CCDBYP2 CLPDM DVSS
PGACONT2 PGACONT1
DVSS ADCCLK DVDD
(MSB) DRVDD DRVSS DSUBST
0.01
CLPOB
PBLK
STBY
TP10 TP11 CLPOB ADCCLK CLPDM PBLK
AVCC
AMP_OUT
Figure Evaluation Board
-14-
REV.
AD9802
TP12
AVCC
PGACONT1
TP13 AVCC AVCC
TP14 AVSS TP15
PGACONT2
DGND
AVCC TP16 TP17 TP18 +3/5D AVSS 0.01 AMP_OUT
AD8047
0.01
+3/5D
Figure Evaluation Board
REV.
-15-
AD9802
+3/5D +3/5D 0.01 74LVXC3245 T/RB VCCB 0.01 0.01 74LVXC3245 T/RB VCCB 0.01 CLPOB PBLK ADCCLK +3/5D 40-PIN HEADER 0.01 74LVXC3245 VCCB T/RB 0.01 CLKOUT CLKOUT CLPDM
CLPDM CLPOB PBLK ADCCLK
(MSB) (LSB)
ADCCLK
Figure Evaluation Board
-16-
REV.
AD9802
Figure Primary Side (Layer
Figure Ground Plane (Layer
REV.
-17-
AD9802
Figure Power Plane (Layer
Figure Secondary Layer (Layer
-18-
REV.
AD9802
Figure Primary Side Assembly
Figure Secondary Side Assembly
REV.
-19-
AD9802
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
48-Terminal Plastic Thin Quad Flatpack (TQFP) (ST-48)
0.063 (1.60) 0.030 (0.75) 0.018 (0.45) 0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35)
0.354 (9.00) 0.276 (7.0)
SEATING PLANE VIEW
(PINS DOWN)
0.076 0.007 (0.18) 0.004 (0.09)
0.019 (0.5)
0.011 (0.27) 0.006 (0.17)
0.354 (9.00)
0.276 (7.0)
-20-
REV.
PRINTED U.S.A.
C3102-3-10/97

PBLK ADCIN Signal Processor Electronic Cameras AD9802 FUNCTI

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