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DESCRIPTIO Software-Selectable Transceiver Supports: RS232, RS449


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LTC1343 Software-Selectable Multiprotocol Transceiver
DESCRIPTIO
Software-Selectable Transceiver Supports: RS232, RS449, EIA-530, EIA-530-A, V.35, V.36, X.21 NET1 NET2 Compliant Software-Selectable Cable Termination Using LTC1344 4-Driver/4-Receiver Configuration Provides Complete 2-Chip Port Operates from Single Supply Internal Echoed Clock Loop-Back Logic
APPLICATIO
Data Networking Data Router, registered trademarks Linear Technology Corporation.
LTC1343 4-driver/4-receiver multiprotocol transceiver that operates from single supply. LTC1343s form core complete software-selectable interface port that supports RS232, RS449, EIA-530, EIA-530-A, V.35, V.36 X.21 protocols. Cable termination implemented using LTC1344 software-selectable cable termination chip using existing discrete designs. LTC1343 runs from single supply using internal charge pump that requires only five space saving surface mount capacitors. mode pins latched internally allow sharing select lines between multiple interface ports. Software-selectable echoed clock loop-back modes help eliminate need external glue logic between serial controller line transceiver. part features flowthrough architecture simplify shielding available 44-lead SSOP surface mount package.
TYPICAL APPLICATIO
Multiprotocol Serial Interface with DB-25 Connector
SCTE
LTC1343
LTC1343
DB-25 CONNECTOR
LTC1344
(107)
(140)
(106)
(108)
(105)
SHIELD (101)
SGND (102)
(142)
(104)
(115)
(109)
SCTE
SCTE (113)
(103)
(141)
(114)
1343 TA01
LTC1343
ABSOLUTE MAXIMUM RATINGS
(Note
PACKAGE/ORDER INFORMATION
VIEW PWRVCC CHARGE PUMP PGND PACKAGE 44-LEAD PLASTIC SSOP
Supply Voltage 6.5V Input Voltage Transmitters 0.3V (VCC 0.3V) Receivers Logic Pins 0.3V (VCC 0.3V) Output Voltage Transmitters (VEE 0.3V) (VDD 0.3V) Receivers 0.3V (VCC 0.3V) Logic Pins 0.3V (VCC 0.3V) 0.3V 0.3V Short-Circuit Duration Transmitter Output Indefinite Receiver Output Indefinite Operating Temperature Range LTC1343C 70°C LTC1343I 40°C 85°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LTC1343CGW LTC1343IGW
D4EN INVERT R1EN CTRL/CLK DCE/DTE LATCH
TJMAX 150°C, 65°C/
Consult factory Military grade parts.
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Notes
SYMBOL Supplies Supply Current (DCE Mode, Digital Pins VCC) V.10 Mode, Load V.10 Mode, Full Load RS530, RS530-A, X.21 Modes, Load RS530, RS530-A, X.21 Modes, Full Load V.35 Mode, Load V.35 Mode, Full Load V.28 Mode, Load V.28 Mode, Full Load No-Cable Mode V.10 Mode, Full Load RS530, RS530-A, X.21 Modes, Full Load V.35 Mode, Full Load V.28 Mode, Full Load Mode, Load V.28 Mode, with Load V.28 Mode, Full Load V.35 Mode, Full Load 40°C 85°C V.10, RS530, RS530A, X.21 Modes, Full Load 40°C 85°C
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
0.05
UNITS
Internal Power Dissipation (DCE Mode, Digital Pins VCC)
Positive Charge Pump Output Voltage Negative Charge Pump Output Voltage
LTC1343
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Notes
SYMBOL IOSR IOZR V.11 Driver SKEW Differential Output Voltage Open Circuit, 1.95k (Figure 1.95k (Figure (Figure (Figure 0.25V 0.25V, Power No-Cable Mode Driver Disabled 0.25V 0.25V, Power No-Cable Mode Driver Disabled (Figures (Figures 70°C (Figures 40°C 85°C (Figures 70°C (Figures 40°C 85°C (Figures 70°C (Figures 40°C 85°C (Figures 70°C 40°C 85°C 70°C 40°C 85°C (Figures (Figures CTRL GND, 70°C CTRL VCC, 70°C (Figures CTRL GND, 40°C 85°C CTRL VCC, 40°C 85°C
ELECTRICAL CHARACTERISTICS
PARAMETER Supply Rise Time Logic Input High Voltage Logic Input Voltage Logic Input Current Output High Voltage Output Voltage Output Short-Circuit Current Three-State Output Current
CONDITIONS No-Cable Mode Power-Up Turn
UNITS
Logic Inputs Outputs ±0.50
VCC, 70°C VCC, 40°C 85°C VCC,
Change Magnitude Differential Output Voltage Common Mode Output Voltage Change Magnitude Common Mode Output Voltage Short-Circuit Current Output Leakage Current Rise Fall Time Input Output Input Output Input Output Difference, tPLH tPHL Output Output Skew Input Threshold Voltage Input Hysteresis Input Current Input Impedance Rise Fall Time Input Output
±150 ±0.01 ±100
V.11 Receiver
LTC1343
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Notes
SYMBOL PARAMETER Input Output CONDITIONS (Figures CTRL GND, 70°C CTRL VCC, 70°C (Figures CTRL GND, -40°C 85°C CTRL VCC, -40°C 85°C V.35 Driver SKEW tPLH tPHL V.10 Driver Output Voltage Open Circuit, 3.9k (Figure 3.9k Driver Only GND; EIA-530, X.21, EIA-530-A Modes 0.25V 0.25V, Power No-Cable Mode Driver Disabled (Figures 450, 100pF R423SET 100k (Figures 450, 100pF R423SET 100k (Figures 450, 100pF R423SET 100k
ELECTRICAL CHARACTERISTICS
±0.66 12.6 ±100
UNITS
Input Output Difference, tPLH tPHL
(Figures 70°C (Figures -40°C 85°C Open Circuit With Load, 4.0V 4.0V (Figure 0.25V 0.25V (Figures (Figures 70°C (Figures -40°C 85°C (Figures 70°C (Figures -40°C 85°C (Figures 70°C (Figures -40°C 85°C (Figures VB)/2 (Figure VB)/2 (Figure (Figures (Figures 70°C (Figures -40°C 85°C (Figures 70°C (Figures -40°C 85°C (Figures 70°C (Figures -40°C 85°C
Differential Output Voltage Transmitter Output High Current Transmitter Output Current Transmitter Output Leakage Current Rise Fall Time Input Output Input Output Input Output Difference, tPLH tPHL Output Output Skew Differential Receiver Input Threshold Voltage Receiver Input Hysteresis Receiver Input Current Receiver Input Impedance Rise Fall Time Input Output Input Output Input Output Difference, tPLH tPHL
±0.44 12.6
±0.55 ±0.01
V.35 Receiver
±4.0 ±3.6
±0.50
±6.0
Short-Circuit Current Output Leakage Current Rise Fall Time Input Output Input Output
±150 ±0.1 ±100
LTC1343
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Notes
SYMBOL V.28 Driver VTHL VTLH tPLH tPHL Output Voltage Short-Circuit Current Output Leakage Current Slew Rate Input Output Input Output Input Threshold Voltage Input High Threshold Voltage Receiver Input Hysteresis Receiver Input Impedance Rise Fall Time Input Output Input Output (Figures (Figures CTRL CTRL (Figures CTRL CTRL
ELECTRICAL CHARACTERISTICS
PARAMETER Receiver Input Threshold Voltage Receiver Input Hysteresis Receiver Input Current Receiver Input Impedance Rise Fall Time Input Output Input Output
CONDITIONS 70°C 40°C 85°C (Figures (Figures (Figures Open Circuit (Figure 0.25V 0.25V, Power No-Cable Mode Driver Disabled (Figures 2500pF (Figures 2500pF (Figures 2500pF
UNITS
V.10 Receiver
±0.50
±150 ±0.01 ±100 30.0
V/µs
V.28 Receiver
Note Absolute Maximum Ratings those beyond which safety device impaired. Note currents into device pins positive; currents device negative. voltages referenced device ground unless otherwise specified.
Note typicals given CVCC CVDD 1µF, CVEE 3.3µF tantalum capacitors 25°C.
FUNCTIONS
(Pin Generated Positive Supply Voltage RS232. Connect capacitor ground. (Pin Capacitor Positive Terminal. Connect capacitor between PWRVCC (Pin Positive Supply Charge Pump. 4.75V PWRVCC 5.25V. (Pin bypass with capacitor ground. (Pin Capacitor Negative Terminal. (Pin Level Driver Input. (Pin Level Driver Input. (Pin Level Driver Input. Becomes CMOS level output when chip echoed clock mode 0V).
LTC1343
FUNCTIONS
(Pin Positive Supply Transceivers. 4.75V 5.25V. PWRVCC (Pin (Pin Level Driver Input. D4EN (Pin 10): Level Enable Input Driver When high, driver outputs enabled. When low, driver outputs forced into high impedance state. D4EN affected LATCH pin. INVERT (Pin 11): Level Signal Invert Input. When high, extra inverter will added driver receiver signal path. data stream will change polarity, i.e., becomes becomes When data flows through with polarity change. INVERT affected LATCH pin. R1EN (Pin 12): Logic Level Enable Input Receiver When low, receiver output enabled. When high, receiver output forced into high impedance state. (Pin 13): CMOS Level Receiver Output. (Pin 14): CMOS Level Receiver Output. (Pin 15): CMOS Level Receiver Output. (Pin 16): CMOS Level Receiver Output. (Pin 17): Level Mode Select Input data latched when LATCH high. (Pin 18): Level Mode Select Input data latched when LATCH high. (Pin 19): Level Mode Select Input data latched when LATCH high. CTRL/CLK (Pin 20): Level Mode Select Input. When chip will configured clock data signals. When high chip will configured control signals. data CTRL/CLK latched when LATCH high. DCE/DTE (Pin 21): Level Mode Select Input. When high, mode selected. When mode selected. data DCE/DTE latched when LATCH high. LATCH (Pin 22): Level Logic Signal Latch Input. When input buffers CTRL/CLK, DCE/ DTE, transparent. When LATCH pulled high data logic pins latched into their respective input buffers. data latch allows logic lines shared between multiple ports. (Pin 23): Level Loop-Back Select Input. When chip enters loop-back configuration configured normal operation when high. data latched when LATCH high. (Pin 24): Level Echoed Clock Select Input. When part enters echoed clock configuration configured normal operation when high. data latched when LATCH high. (Pin 25): Analog Input RS423 Driver Output Rise Fall Time Resistor. Connect resistor from ground. (Pin 26): Receiver Inverting Input. (Pin 27): Receiver Noninverting Input. (Pin 28): Receiver Inverting Input. (Pin 29): Receiver Noninverting Input. (Pin 30): Receiver Inverting Input. (Pin 31): Receiver Noninverting Input. (Pin 32): Receiver Inverting Input. (Pin 33): Driver Noninverting Output. (Pin 34): Driver Inverting Output. (Pin 35): Driver Noninverting Output. (Pin 36): Driver Inverting Output. (Pin 37): Driver Noninverting Output. (Pin 38): Driver Inverting Output. (Pin 39): Driver Inverting Output. (Pin 40): Signal Ground. Connect PGND (Pin 41). PGND (Pin 41): Charge Pump Power Ground. Connect (Pin 40). (Pin 42): Generated Negative Supply Voltage. Connect 3.3µF capacitor ground. (Pin 43): Capacitor Negative Terminal. Connect capacitor between (Pin 44): Capacitor Positive Terminal. Connect capacitor between
LTC1343
TEST CIRCUITS
100pF 100pF
15pF
1343
1343
Figure RS422 Driver Test Circuit
Figure RS422 Driver/Receiver Test Circuit
15pF
1343
Figure V.35 Driver/Receiver Test Circuit
15pF
1343
1343
Figure V.10/V.28 Driver Test Circuit
Figure V.10/V.28 Receiver Test Circuit
SELECTIO
LTC1343 MODE NAME V.10, RS423 EIA-530-A Clock Data EIA-530-A Control Reserved X.21 V.35 Clock Data V.35 Control EIA-530, RS449, V.36 V.28, RS232 Cable
CTRL/CLK V.10 V.10 V.10 V.10 V.10 V.28 V.28 V.10 V.28 V.10 V.11 V.11 V.11 V.11 V.35 V.28 V.11 V.28 V.10 V.11 V.10 V.11 V.11 V.35 V.28 V.11 V.28 V.10 V.11 V.11 V.11 V.11 V.35 V.28 V.11 V.28 V.10 V.11 V.11 V.11 V.11 V.35 V.28 V.11 V.28 V.10 V.11 V.10 V.11 V.11 V.35 V.28 V.11 V.28 V.10 V.11 V.11 V.11 V.11 V.35 V.28 V.11 V.28 V.10 V.10 V.10 V.10 V.10 V.28 V.28 V.10 V.28
LTC1343
SWITCHI WAVEFOR
SKEW SKEW
1343
1.5V
1MHz 10ns
Figure V.11, V.35 Driver Propagation Delay
VOD2 -VOD2
1.5V
Figure V.11, V.35 Receiver Propagation Delay
1.5V 1.5V
1343
Figure V.10, V.28 Driver Propagation Delay
1.3V 1.7V 2.4V 0.8V
1343
Figure V.10, V.28 Receiver Propagation Delay
1.5V
VDIFF V(A) V(B)
1MHz 10ns
INPUT
OUTPUT
1.5V
1343
LTC1343
APPLICATIONS INFORMATION
Overview LTC1343 4-driver/4-receiver multiprotocol transceiver that operates from single supply. LTC1343s form core complete software-selectable interface port that supports RS232, RS449, EIA-530, EIA-530-A, V.35, V.36 X.21 protocols. Cable termination implemented using LTC1344
SERIAL CONTROLLER LTC1343 LTC1344 LTC1344
SCTE
LTC1343
Figure Complete Multiprotocol Interface EIA-530 Mode
software-selectable cable termination chip using existing discrete designs. complete DCE-to-DTE interface operating EIA-530 mode shown Figure first LTC1343 each port used generate clock data signals along with (Local Loop-back) (Test Mode). second LTC1343 used generate control signals along with
LTC1343 SERIAL CONTROLLER
SCTE
SCTE
LTC1343
1343
LTC1343
APPLICATIONS INFORMATION
(Remote Loop-back) (Ring Indicate). LTC1344 cable termination chip used only clock data signals because they must support V.35 cable termination. control signals need external resistors. Mode Selection interface protocol selected using mode select pins CTRL/CLK (see Mode Selection table). CTRL/CLK should pulled high LTC1343 being used generate control signals pulled used generate clock data signals. example, port configured V.35 interface, mode selection pins should control signals, CTRL/CLK drivers receivers will operate RS232 (V.28) electrical mode. clock data signals, CTRL/CLK drivers receivers will operate V.35 electrical mode, except single-ended driver receiver which will operate RS232 (V.28) electrical mode. DCE/DTE
LATCH LTC1344 DCE/ (DATA) LTC1343 DCE/DTE CTRL/CLK LATCH CABLE LTC1343 DCE/DTE CTRL/CLK LATCH (DATA)
1343
(DATA) CONNECTOR
Figure Single Port DCE/V.35 Mode Selection Cable
will configure port mode when high, when low. interface protocol selected simply plugging appropriate interface cable into connector. mode pins routed connector left unconnected wired ground cable shown Figure pull-up resistors through will ensure binary when left unconnected that LTC1343s LTC1344 enter no-cable mode when cable removed. no-cable mode LTC1343 supply current drops less than 200µA LTC1343 driver outputs LTC1344 resistive terminations forced into high impedance state. Note that data latch pin, LATCH, shorted ground chips. interface protocol also selected serial controller host microprocessor shown Figure mode selection pins DCE/DTE shared between multiple interface ports, while each port
LTC1343
APPLICATIONS INFORMATION
PORT CONNECTOR DCE/DTE
LATCH PORT CONNECTOR DCE/DTE
CONTROLLER
LATCH PORT
DCE/DTE LATCH LATCH LATCH
CONNECTOR DCE/DTE
LATCH
1343
Figure Mode Selection Controller
unique data latch signal which acts write enable. When LATCH buffers CTRL/CLK, DCE/DTE, pins transparent. When LATCH pulled high buffers latch data changes input pins will longer affect chip. mode selection also accomplished using jumpers connect mode pins ground VCC. Cable Termination Traditional implementations have included switching resistors with expensive relays, requiring user change termination modules every time interface standard changed. Custom cables have been used with termination cable head, separate terminations built board custom cable routes signals appropriate termination. Switching terminations with FETs difficult because FETs must
-10V
remain even though signal voltage beyond supply voltage drivers power off. Using LTC1344 along with LTC1343 solves cable termination switching problem. software control, LTC1344 provides termination V.10 (RS423), V.11 (RS422), V.28 (RS232) V.35 electrical protocols. V.10 (RS423) Interface typical V.10 unbalanced interface shown Figure V.10 single-ended generator output with ground connected differential receiver with inputs connected input connected signal return ground receiver's ground separate from signal return. Usually, cable termination required V.10 interfaces, receiver inputs must compliant with impedance curve shown Figure
BALANCED INTERCONNECTING CABLE
GENERATOR
LOAD CABLE TERMINATION RECEIVER
1343
Figure Typical V.10 Interface
3.25mA
1343
-3.25mA
Figure V.10 Receiver Input Impedance
LTC1343
APPLICATIONS INFORMATION
V.10 receiver configuration LTC1343 LTC1344 shown Figure V.10 mode switches inside LTC1344 inside LTC1343 turned off. Switch inside LTC1343 shorts noninverting receiver input ground input connector left floating. cable termination then input impedance ground LTC1343 V.10 receiver. V.11 (RS422) Interface typical V.11 balanced interface shown Figure V.11 differential generator with outputs with ground connected differential receiver with ground inputs connected connected V.11 interface differential termination receiver that minimum value 100. termination resistor optional V.11 specification, high speed clock data lines, termination required prevent reflections from corrupting data. reA' 51.5 51.5 LTC1344 RECEIVER 51.5 LTC1343 51.5 LTC1344
Figure V.10 Receiver Configuration
BALANCED INTERCONNECTING CABLE
GENERATOR
LOAD CABLE TERMINATION RECEIVER
Figure Typical V.11 Interface
ceiver inputs must also compliant with impedance curve shown Figure V.11 mode, switches except inside LTC1344 which connects differential termination impedance cable shown Figure V.28 (RS232) Interface typical V.28 unbalanced interface shown Figure V.28 single-ended generator output with ground connected single-ended receiver with inputs connected ground connected signal return ground V.28 mode switches except inside LTC1343 which connects (R8) impedance ground parallel with (R5) plus (R6) combined impedance shown Figure noninverting input disconnected inside LTC1343 receiver connected level reference voltage 1.4V receiver trip point.
RECEIVER LTC1343
1343
1343
Figure V.11 Receiver Configuration
BALANCED INTERCONNECTING CABLE
GENERATOR
LOAD CABLE TERMINATION RECEIVER
1343
1343
Figure Typical V.28 Interface
LTC1343
APPLICATIONS INFORMATION
51.5 51.5 LTC1344 RECEIVER 51.5 LTC1343 51.5 LTC1344 RECEIVER LTC1343
Figure V.28 Receiver Configuration
V.35 Interface typical V.35 balanced interface shown Figure V.35 differential generator with outputs with ground connected differential receiver with ground inputs connected connected V.35 interface requires delta network termination receiver generator end. receiver differential impedance measured connector must ±10, impedance between shorted terminals ground must ±15. V.35 mode, both switches inside LTC1344 connecting network impedance shown Figure Both switches LTC1343 off. input impedance receiver placed parallel with network termination, does affect overall input impedance significantly.
BALANCED INTERCONNECTING CABLE
GENERATOR
LOAD CABLE TERMINATION RECEIVER
1343
Figure Typical V.35 Interface
1343
1343
Figure V.35 Receiver Configuration
generator differential impedance must impedance between shorted terminals ground must ±15. generator termination, switches both side center resistor brought bypassed with external capacitor reduce common mode noise shown Figure mismatch driver rise fall times skew driver propagation delays will force current through center termination resistor ground, causing high frequency common mode spike terminals. common mode spike cause problems that reduced capacitor which shunts much common mode energy ground rather than down cable.
LTC1344
51.5
V.35 DRIVER
51.5 100pF
1343
Figure V.35 Driver Using LTC1344
LTC1343
APPLICATIONS INFORMATION
Echoed Clock Mode LTC1343 contains logic generate echoed clock when using serial controller with only clock pins. Figure shows chip both echoed clock EIA-530 mode. control signals shown. echoed clock configuration selected pulling low. side transmit clock receiver output connected echoed clock, SCTE, driver input. serial controller configured input. side, transmit clock from serial controller used generate both RXC. phase inverter placed signal path both side help correct phase problems with long cables. Invert high, phase data inverted. Loop-Back LTC1343 contains logic placing interface into loop-back configuration testing. Both loop-back configurations supported. Figure shows complete interface loop-back configuration with pulled high. loop-back configuration selected pulling low. Both line side logic side signals looped back. loop-back configuration shown Figure echoed clock mode selected pulling low, becomes output connected receiver output mode shown Figure echoed clock loop-back mode, driver connected driver input shown Figure
SERIAL CONTROLLER LTC1343 LTC1344 LTC1344
INVERT
CTRL/CLK
CTRL/CLK
DCE/DTE
DCE/DTE LATCH
DCE/DTE LATCH
DCE/DTE
LATCH
LATCH
Figure EIA-530 Echoed Clock Configuration
LTC1343 SERIAL CONTROLLER
SCTE
INVERT
1343
LTC1343
APPLICATIONS INFORMATION
SERIAL CONTROLLER LTC1343 LTC1344 LTC1344 LTC1343 SERIAL CONTROLLER
SCTE
CTRL/CLK
CTRL/CLK
DCE/DTE
DCE/DTE LATCH
DCE/DTE LATCH
DCE/DTE
LATCH
LTC1343
LTC1343
LATCH
CTRL/CLK
CTRL/CLK
DCE/DTE
DCE/DTE
LATCH
1343
LATCH
Figure Normal Loop-Back
SCTE
SCTE
SCTE
1343
Figure Normal Loop-Back
LTC1343
APPLICATIONS INFORMATION
SERIAL CONTROLLER LTC1343 LTC1344 LTC1344 LTC1343 SERIAL CONTROLLER
CTRL/CLK DCE/DTE
DCE/DTE LATCH
CTRL/CLK
DCE/DTE LATCH
DCE/DTE
LATCH
LTC1343
LTC1343
LATCH
CTRL/CLK
CTRL/CLK
DCE/DTE
DCE/DTE
LATCH
LATCH
Figure Echoed Clock, Loop-Back
TXCE
SCTE
1343
1343
Figure Echoed Clock, Loop-Back
LTC1343
APPLICATIONS INFORMATION
No-Cable Mode no-cable mode intended case when cable disconnected from connector. charge pump, bias circuitry, drivers receivers turned off, driver outputs forced into high impedance state, supply current drops less than 200µA. also used share lines with other drivers receivers without loading down signals. Charge Pump LTC1343 uses internal capacitive charge pump generate shown Figure voltage doubler generates about voltage inverter generates about 7.5V VEE. Four surface mounted tantalum ceramic capacitors required capacitor should minimum 3.3µF. capacitors 16V. Receiver Fail-Safe Glitch Filter LTC1343 receivers feature fail-safe operation modes except no-cable mode. receiver inputs left floating shorted together termination resistor, receiver output will always forced logic high. External pull-up resistors required receiver outputs fail-safe operation no-cable mode desired. When chip configured control signals pulling CTRL/CLK high, glitch filter connected receiver inputs. filter will reject glitches receiver inputs less than 300ns. V.10 Driver Rise Fall Times rise fall times V.10 drivers programmed placing 1/8W, resistor between (Pin ground. graph Driver Rise Fall Times Resistor Value shown Figure Enabling Single-Ended Driver Receiver When LTC1343 being used generate control signals (CTRL/CLK high) pulled low, DCE/DTE becomes enable driver receiver their inputs outputs tied together shown Figure
LTC1343 DCE/DTE CTRL/CLK
1343
PGND
Figure Charge Pump
DRIVER RISE/FALL TIME (µs)
100k RESISTANCE
1343
Figure V.10 Driver Rise Fall Time Resistor Value
Figure Single-Ended Driver Receiver Enable
LTC1343 PWRVCC
3.3µF
1343
LTC1343
APPLICATIONS INFORMATION
affect configuration when CTRL/ high except allow DCE/DTE become enable. When DCE/DTE low, driver output enabled. receiver output goes into three-state input presents load ground. When DCE/DTE high, driver output goes into threestate receiver output enabled. receiver input presents load ground modes except when configured RS232 operation when input impedance ground. Operation DCE/DTE does allow given LTC1343 reconfigured driver receiver. DCE/DTE only selects loop-back topology acts enable single-ended driver receiver control signals. However, LTC1343 configured either operation three ways: dedicated port with connector appropriate gender, port with connector that configured operation rerouting signals LTC1343 using dedicated cable dedicated cable, port with connector cable using four LTC1343s. dedicated port using DB-25 male connector shown Figure interface mode selected logic outputs from controller from jumpers either mode select pins. dedicated port using DB-25 female connector shown Figure port with DB-25 connector that configured either operation shown Figure configuration requires separate cables proper signal routing operation. example, mode, signal routed connector Pins driver LTC1343. mode, driver routes signal Pins combination DTE/DCE port that doesn't require separate DCE/DTE cables shown Figure mode, bottom LTC1343s enabled middle placed no-cable mode, which forces drivers receivers into high impedance state. mode, middle LTC1343s enabled bottom LTC1343s disabled. With this scheme, connector configured sending receiving signals. Note that only LTC1344 required. Multiprotocol Interface with Ring-Indicate DB-25 Connector signal RS232 mode implemented, driver receiver control chip tied connector order implement signal RS232 mode signal other modes. Figure shows configuration Figure configuration. mode, DCE/DTE should driven with logic signal from controller that goes only when interface RS232 mode. Since receiver input impedance greater than modes except RS232, enabled other times load down line. When driver disabled, remains high impedance state does load line. Cable-Selectable Multiprotocol Interface cable-selectable multiprotocol DTE/DCE interface shown Figure control signals implemented. select lines DCE/DTE brought connector. mode selected through cable wiring (connector 18), (connector DCE/DTE (connector ground (connector letting them float. DCE/DTE floating, pull-up resistors will pull signals VCC. select hard wired VCC. When cable pulled out, interface will into no-cable mode. Multiprotocol Interface with µDB-26 Connector controller-selectable multiprotocol DTE/DCE interface with standard µDB-26 connector shown Figure signals implemented mapped connector. cable-selectable version shown Figure signals have been dropped, still implemented.
LTC1343
APPLICATIONS INFORMATION
100pF 100pF 100pF LTC1344
LTC1343
CHARGE PUMP
3.3µF
SCTE
CTRL LATCH INVERT 100k
LTC1343
CHARGE PUMP
3.3µF
LATCH
100k
CTRL LATCH INVERT
Figure Controller-Selectable Multiprotocol Port with DB-25 Connector
LATCH
LATCH
DCE/
DB-25 MALE CONNECTOR
(141) (103) SCTE (113) SCTE
(114) (115) (104) (142)
SGND (102) SHIELD (101)
(140) (105) (108)
(109) (107) (106)
1343
LTC1343
APPLICATIONS INFORMATION
100pF 100pF 100pF LTC1344
LTC1343
CHARGE PUMP
3.3µF DB-25 FEMALE CONNECTOR SCTE (113) SCTE (103) (141)
SCTE
CTRL LATCH INVERT 100k
LTC1343
CHARGE PUMP
(106) (107) (109)
LATCH
100k
CTRL LATCH INVERT
1343
Figure Controller-Selectable Multiprotocol Port with DB-25 Connector
3.3µF
LATCH
LATCH
DCE/
(142) (104) (115) (114)
SGND (102)
SHIELD (101)
(108) (105) (140)
LTC1343
APPLICATIONS INFORMATION
100pF 100pF 100pF LTC1344
LTC1343 CHARGE PUMP
DTE_LL/DCE_DTE_TXD/DCE_RXD DTE_SCTE/DEC_RXC
DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD DTE_TM/DCE_LL
100k
CTRL LATCH INVERT
LTC1343
CHARGE PUMP
3.3µF
DTE_RL/DCE_RL DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR
DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS
LATCH
100k DCE/DTE
CTRL LATCH INVERT
Figure Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
LATCH
LATCH
3.3µF
DCE/
DB-25 CONNECTOR
SCTE SCTE
SCTE SCTE
SGND SHIELD
1343
LTC1343
APPLICATIONS INFORMATION
LTC1343 LTC1343 (142) (104) (115) (114) DCE/DTE DB-25 CONNECTOR DCE/ 100pF 100pF 100pF
LTC1343
SCTE
(106) (107) (109) SHIELD (101)
LTC1343
Figure Controller-Selectable Multiprotocol DTE/DCE Port with DB-25
LTC1344
SCTE (113) SCTE (103) (141) SGND (102)
(108) (105) (140)
1343
LTC1343
APPLICATIONS INFORMATION
100pF 100pF 100pF LTC1344
LTC1343
CHARGE PUMP
3.3µF
SCTE
100k
CTRL LATCH INVERT
LTC1343
CHARGE PUMP
3.3µF
LATCH
100k
CTRL LATCH INVERT
Figure Controller-Selectable Multiprotocol Port with DB-25 Connector
LATCH
LATCH
DCE/
DB-25 MALE CONNECTOR
(141) (103) SCTE (113) SCTE
(114) (115) (104) (142)
SGND (102)
SHIELD (101)
(140) (105) (108)
(109) (107) B/RI (125) (106)
1343
LTC1343
APPLICATIONS INFORMATION
100pF 100pF 100pF LTC1344
LTC1343
CHARGE PUMP
3.3µF
SCTE
100k
CTRL LATCH INVERT
LTC1343
CHARGE PUMP
3.3µF
RIEN RS232
1343
LATCH
100k
CTRL LATCH INVERT
Figure Controller-Selectable Multiprotocol Port with DB-25 Connector
LATCH
LATCH
DCE/
DB-25 FEMA;E CONNECTOR
(142) (104) (115) (114)
SCTE (113) SCTE (103) (141)
SGND (102) SHIELD (101)
(106) (107) B/RI (125) (109)
(108) (105) (140)
LTC1343
APPLICATIONS INFORMATION
100pF 100pF 100pF LTC1344
LTC1343
CHARGE PUMP
SCTE SCTE
DTE_TXD/DCE_RXD DTE_SCTE/DEC_RXC
DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD
100k
CTRL LATCH INVERT
LTC1343
CHARGE PUMP
DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR
DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/ DCE_RTS
100k
CTRL LATCH INVERT
Figure Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
LATCH
3.3µF DB-25 CONNECTOR
DCE/
SCTE SCTE
SGND SHIELD
3.3µF
DCE/DTE
1343
CABLE WIRING MODE SELECTION MODE V.35 EIA-530, RS449, V.36, X.21 RS232
CABLE WIRING DTE/DCE SELECTION MODE
LTC1343
APPLICATIONS INFORMATION
100pF 100pF 100pF LTC1344
LTC1343
CHARGE PUMP
DTE_LL/DCE_DTE_TXD/DCE_RXD DTE_SCTE/DEC_RXC
DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD DTE_TM/DCE_LL
100k
CTRL LATCH INVERT
LTC1343
CHARGE PUMP
DTE_RL/DCE_RI DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR
DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS DTE_RI/DCE_RL LATCH
100k DCE/DTE
CTRL LATCH INVERT
Figure Controller-Selectable Multiprotocol DTE/DCE Port with DB-26 Connector
LATCH
LATCH
3.3µF µDB-26 CONNECTOR
DCE/
SCTE SCTE
SCTE SCTE
SGND SHIELD
3.3µF
1343
LTC1343
APPLICATIONS INFORMATION
100pF 100pF 100pF LTC1344
LTC1343
CHARGE PUMP
SCTE SCTE
DTE_TXD/DCE_RXD DTE_SCTE/DEC_RXC
DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD
100k
CTRL LATCH INVERT
LTC1343
CHARGE PUMP
DTE_LL/DCE_LL DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR
DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS
100k
CTRL LATCH INVERT
1343
Figure Cable-Selectable Multiprotocol Port with DB-26 Connector
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LATCH
3.3µF µDB-26 CONNECTOR
DCE/
SCTE SCTE
SGND SHIELD
3.3µF
DCE/DTE
CABLE WIRING MODE SELECTION MODE V.35 EIA-530, RS449, V.36, X.21 RS232
CABLE WIRING DTE/DCE SELECTION MODE
LTC1343
PACKAGE DESCRIPTION
Dimensions inches (millimeters) unless otherwise noted. Package 44-Lead Plastic SSOP (Wide 0.300)
(LTC 05-08-1642)
17.805 18.059* (0.701 0.711)
10.160 10.414 (0.400 0.410)
7.417 7.595** (0.292 0.299) 0.254 0.406 (0.010 0.016)
2.463 2.641 (0.097 0.104) 2.286 2.387 (0.090 0.094)
0.231 0.3175 (0.0091 0.0125)
0.610 1.016 (0.024 0.040)
0.800 (0.0315)
0.304 0.431 (0.012 0.017)
0.127 0.292 (0.005 0.0115)
NOTE: DIMENSIONS MILLIMETERS *DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH **DIMENSION DOES INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.254mm (0.010") SIDE SHALL EXCEED 0.152mm (0.006") SIDE
SSOP 1098
RELATED PARTS
PART NUMBER
LTC1321 LTC1334 LTC1344/LTC1344A LTC1345 LTC1346A LTC1543 LTC1544 LTC1545
DESCRIPTION
Dual RS232/RS485 Transceiver Single RS232/RS485 Multiprotocol Transceiver Software-Selectable Cable Terminator Single Supply V.35 Transceiver Dual Supply V.35 Transceiver Software-Selectable Multiprotocol Transceiver Software-Selectable Multiprotocol Transceiver Software-Selectable Multiprotocol Transceiver
COMMENTS
RS232 Driver/Receiver Pairs RS485 Driver/Receiver Pairs RS232 Driver/Receiver RS232 Driver/Receiver Pairs Perfect Terminating LTC1343 Driver/3 Receiver Data Clock Signals Driver/3 Receiver Data Clock Signals Driver/3 Receiver Data Clock Signals Driver/4 Receiver Control Signals Including Driver/5 Receiver Control Signals Including
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417
(408)432-1900 FAX: (408) 434-0507 www.linear-tech.com
1343fa LT/TP 0899 PRINTED
LINEAR TECHNOLOGY CORPORATION 1996

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