purpose this application note describe operation AMCC STS-48/STM-16 mu
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OC-48 APPLICATION NOTE S3041/42/45/76, S1202 LUCENT FIBER OPTIC XCVR OC-48 APPLICATION NOTE S3041/42/45/76, S1202 LUCENT FIBER OPTIC XCVR PURPOSE
purpose this application note describe operation AMCC STS-48/STM-16 multiplexer demultiplexer solution. AMCC S3042 SONET/SDH/ASTS-48/ STM-16 demultiplexer chip which provides first stage digital processing receive SONET STS-48/STM-16 bit-serial stream. receive path converts 2.488 Gbps bit-serial data stream into 311.04 Mbps 8-bit parallel data. AMCC S3041 SONET/SDH/ASTS-48/STM-16 multiplexer chip which converts 8-bit parallel data 311.04 Mbps into bit-serial data 2.488 Gbps. AMCC SONET/ STS-48/STM-16 S3045 fully integrated STS-12/STM-4 STS-48/STM-16 multiplexer/ demultiplexer device. This device performs necessary byte interleave functions. Figure shows typical application block diagram. Figure shows design details interfacing Lucent fiber optic transceiver AMCC S3076, S3042, S3041 interface. also shows interface S3041/3042, S3045, four NILE S1202 devices. Combining these devices provides Physical Media Dependent (PMD) layer SONET/SDH data transfer.
AMCC S3041, S3042 S3045 SONET/SDH transceiver chip fully integrated serialization/ deserialization SONET STS-48/STM-16 (2.488 Gbps) interface. These devices suitable SONET based Aapplications used conjunction with AMCC SONET Mapper S1202 NILE, S3076 Clock Recovery Unit (CRU) Lucent fiber optic transceiver. AMCC S3076 SONET/SDH multi-rate Clock Recovery Unit (CRU) which receives STS-48/ STM-16 scrambled signal recovers clock from data. S3076 then outputs differential clock re-timed data AMCC S3042.
Figure Typical Network Application Block Diagram
Attenuation
77.76 Mbps
AMCC NILE S1202
Lucent Fiber Optic Transceiver Module 1417K4A
AMCC S3076
2.488 Gbps DATA CLOCK
AMCC S3042
311.04 Mbps 77.76 Mbps
AMCC NILE S1202
AMCC S3045
77.76 Mbps
AMCC NILE S1202
2.488 Gbps DATA CLOCK
AMCC S3041
311.04 Mbps 77.76 Mbps
AMCC NILE S1202
Notes: Clock Recovery Unit.
September 2000 Revision
OC-48 APPLICATION NOTE S3041/42/45/76, S1202 LUCENT FIBER OPTIC XCVR
Signal Connect Description
AMCC S3076 receives scrambled signal from Lucent 1417K4A fiber optic transceiver recovers clock from data. After clock recovered from bit-serial data stream S3076 transmits recovered clock re-timed data AMCC S3042 receiver. AMCC S3042 searches incoming serial data stream frame byte boundaries transmits byte aligned data AMCC S3045 LVDS 8-bit parallel interface rate 311.04 Mbps. AMCC S3045 receives 8-bit parallel data from S3042 demultiplexes data, converting data stream into four 8-bit parallel data sets transmitting rate 77.76 Mbps four NILE S1202 devices 8-bit parallel LVTTL interface. four NILE S1202 devices transmit 8-bit parallel data AMCC S3045 interface rate 77.76 Mbps. AMCC S3045 transmits 8-bit parallel data rate 311.04 Mbps AMCC S3041 LVDS interface. AMCC S3041 transmits bit-serial data rate 2.488 Gbps interface Lucent 1417K4A fiber optic transceiver. Figure shows block diagram fiber optic interface solution. (S3041, S3042, S3045, S3076, NILE S1202 Lucent fiber optics.)
September 2000 Revision
part part
BYTE ALIGNMENT
SERDATOP/N SERDATIP/N RX_DATA[7:0]A RX_DATA[7:0]B RX_DATA[7:0]C RX_DATA[7:0]D
part
part
part
Lucent 1417K4A
AMCC S3076
from SDT8908-R
REFCLKP REFCLKN LOCKDET
September 2000 Revision
line ground resistor must used external line line resistor must placed externally across S3042/41LVDS outputs S3045 LVDS inputs RSDP/N POUTA[7:0] LVTTL POUTB[7:0] PULSEOOF LVTTL POUTC[7:0] SEARCH POUTD[7:0] POUT[7:0]P/N LVDS 311DATIN[7:0]P/N LVDS POCLKP/N 311CLKINP/N RSCLKP/N PAROUT A,B,C,D B1ERR SERCLKOP/N BYPASS RATESEL RATESEL REFSEL LCKREFN
AMCC S3042
FLAG SDLVTTL SDLVPECL SQUELCHB POCLKA POCLKB POCLKC POCLKD FRAMEP/N Logic High DLEB DSCRBENB SDVBB FPSEL A,B,C,D VDD5
J0FP RX_CLK78A RX_CLK78B RX_CLK78C RX_CLK78D
PECL
FPP/N
RX311MCKP/N LVDS
LVDS
AMCC S3045
PARFPRXSEL
LOGIC HIGH LOGIC HIGH RESET LOGIC HIGH LOGIC HIGH
AMCC NILE S1202
TX_CLK78A TX_CLK78B,C,D TX_FRAME_INA PICLK TX_FRAME_INB
TDZo PIN[7:0]P/N PICLKP/N PCLKP/N READP/N PULSEOP/N REFCLKP REFCLKN 77MCK LVDS LVDS LVDS LVDS LVDS TSDN
DLEB LLEB RSTB KILLRXCLK LLDP/N FRAMEN LLCLKP/N LSDP/N LSCLKP/N LSCLKP/N LLCLKP/N LSDP/N TSDP LLDP/N
LVDS TRANSMISSION LINE TERMINATION
311DATOUT [7:0]P/N 311CLKOUTP/N PCLK_A SYNCRSTB 311TCLKP/N READP/N PULSEP/N
TX_FRAME_INC TX_FRAME_IND PINA[7:0] PINB[7:0] PINC[7:0] PIND[7:0]
TX_DATA[7:0]A TX_DATA[7:0]B TX_DATA[7:0]C TX_DATA[7:0]D
External AMCC S3042 S3041
internal AMCC S3042 S3041 External S3045
AMCC S3041
LVTTL
REFCLK 155.52
Figure AMCC S3041/42/45/76, NILE S1202 Lucent Fiber Optic Block Diagram
TX_FRAME_OUT LVTTL B1SELB PARFPTXSEL RSTB A,B,C,D
PARIN A,B,C,D PARERR A,B,C,D B2/M1SELB TIFP A,B,C,D
LOGIC HIGH LOGIC HIGH RESET
DLEB LLEB RSTB
LOCKDET TESTEN KILLTXCLKN
LOGIC LOGIC HIGH
J0/Z0SEL PARSEL
SCRBENB RESET
OC-48 APPLICATION NOTE S3041/42/45/76, S1202 LUCENT FIBER OPTIC XCVR
Notes: B2/M1SELB, B1SELB, J0/Z0SEL, PARSEL, DSCRBENB, SCRBENB connected general purpose registers control user requirements. When using S3045 DLEB mode SDLVTTL SDLVPECL must forced opposite states otherwise POUTA,B,C,D busses will forced zero.
Termination high speed PECL inputs (RSD,RSCLK) LVDS inputs terminated with line line biased VCC-0.65 within S3041 S3042 Note: FLAG active high: when high data valid.
OC-48 APPLICATION NOTE S3041/42/45/76, S1202 LUCENT FIBER OPTIC XCVR
Figure AMCC S3041/42/45 LVDS Termination Block Diagram
AMCC S3042/S3041 LVDS OUTPUTS
AMCC S3045 LVDS INPUTS
AMCC S3041 LVDS INPUTS
AMCC S3045 LVDS OUTPUTS
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OC-48 APPLICATION NOTE S3041/42/45/76, S1202 LUCENT FIBER OPTIC XCVR
Figure Nile Strobe Shift Circuit
September 2000 Revision
OC-48 APPLICATION NOTE S3041/42/45/76, S1202 LUCENT FIBER OPTIC XCVR
Theory Operation Receive Path
AMCC S3076 extracts clock from data re-times data from Lucent fiber optic input. S3042 receives STS-48/STM-16 (2.488 Gbps) scrambled data signals serial data stream (RSDP/N) differential LVPECL inputs. These inputs clocked into S3042 Receive Serial Clock (RSCLKP/N) differential LVPECL inputs. This clock used receive section master clock perform framing deserialization functions. After data received, frame byte boundary detection circuitry searches incoming data three consecutive bytes followed byte. Framing pattern detection enabled rising edge Out-Of-Frame (OOF) LVTTL input S3042 from PULSEOOF/OOF outputs S3045. STS-48/STM-16 byte boundary reported Frame Pulse (FP) LVDS output when 32-bit pattern matching framing pattern detected incoming data stream. This signal used start frame boundary detection circuitry state machine S3045. bit-serial data stream (RSDP/N) then converted into 8-bit parallel data format output onto Parallel Output data (POUT[7:0]). 8-bit parallel data clocked S3042 into S3045 with LVDS Parallel Output Clock (POCLKP/N) rate 311.04 Mbps. byte calculated incoming data stream STS-48/STM-16 first incoming STS12/STM-4 data stream. calculated STS-48/STM-16 byte compared received byte. there errors, then calculated STS-12/STM-4 byte inserted into device data stream POUTA[7:0]. there errors received STS-48/STM-16 byte, then errors inserted into STS-12/STM-4 byte before forwarded device This performance monitoring scheme allows NILE S1202 device master device with respect performance monitoring OC-48 data link. there failure with OC-48 data link NILE S1202 device will perform error rate monitoring OC-48 data stream. 8-bit parallel data output from S3045 into NILE S1202 parallel data output (RX_DATA[7:0] A,B,C,D) clocked Parallel Output Clock (POCLK A,B,C,D). This data output four separate LVTTL busses POUT[7:0](A,B,C,D) four separate clocks (POCLK
Theory Operation Transmit Path
8-bit parallel data input from NILE S1202 into S3045 Parallel Data Input (PIN[7:0] A,B,C,D) Parallel Input Clock (PICLK) S3045. This data input four separate LVTTL busses (A,B,C,D) PICLK clock. VDD5 pins (70, 131, 171) S3045 need connected volts that inputs volt tolerant. 8-bit parallel data output from S3045 into S3041 parallel data input (PIN[7:0]) sampled Parallel Input Clock (PICLK) S3041. This clock (PICLK) generated S3041 Parallel Clock (PCLK) which back into PICLK input 311CLKOUT output S3045. 8-bit parallel data then converted bit-serial data S3041 output through differential Transmit Serial Data (TSDP/N) connections fiber optic transmitter rate 2.488 Gbps. S3041 includes clock synthesizer which generates 2.488 clock from 155.52 reference clock. Frame alignment: proper frame alignment between NILE S1202 S3045, TX_FOUT_BYTE_TYPE[1:0] TX_FOUT_BYTE_NUMBER[3:0] registers NILE should provisioned shown Table
Table NILE S1202 Frame Alignment Settings
Data TX_DATA[7:0] when TX_FRAME_OUT First byte after last bytes TX_FOUT_BYTE_TYPE[1:0] TX_FOUT_BYTE_NUMBER[3:0] 0001
September 2000 Revision
OC-48 APPLICATION NOTE S3041/42/45/76, S1202 LUCENT FIBER OPTIC XCVR
Terminations
following list terminations that need added this particular design. pull down resistors should close sources (S3041, S3042) possible. Note these resistors shown LVDS lines Figure S3045 LVDS outputs need pull-down resistors. line-to-line termination resistors should placed close possible S3045 LVDS inputs. S3041 S3042 LVDS inputs need line-to-line termination. high frequency traces should designed transmission lines with termination depicted Figure Figure termination resistors should placed transmission line, power supply decoupling should placed close device power pins possible. Differential LVPECL signal traces should have matched length consistent spacing (for equal transit time). Differential line geometries shall fixed operation. Incident noise coupled into closely spaced parallel lines becomes common mode phenomenon, which effectively cancels far-end differential inputs. Line spacing between signals different origin should least line widths reduce potential coupling interference. Optical receiver outputs must coupled rest system because optical receiver module powered from downstream processing powered from +3.3 Capacitors data lines should exhibit less than reactance minimize affects baseline shift. Coupling capacitors clock lines should have less than reactance fundamental clock frequency. Chips that terminate high speed lines equipped with internal bias insert appropriate offset. Coupling capacitors should placed close source possible. destination line terminated line's characteristic impedance. Lucent 1417K4A inputs TD+/- have line termination bias. device must coupled externally. Differential high speed LVPECL inputs (RSDP/N, RSCLKP/N) S3042 terminated internally with resistors line-to-line biased -0.65V.
LVDS inputs (311DATIN[7:0], 311CLKIN, FRAMEP/N, 311TCLKP/N, PULSEP/N) S3045 should terminated externally with resistors line-to-line. S3041 S3042 LVDS outputs need ground source. S3045 LVDS outputs need pull down resistors. 2.488 Gbps controlled impedance clock data lines should avoid layer transitions, i.e. vias. Keep 2.488 Gbps signals single layer with trace lengths under inches. 2.488 Gbps, differential length between four lines making balanced clock data interconnect should within 0.020 inch avoid signal degradation phasing error between complimentary pairs. possible 2.488 Gbps 311.04 Mbps traces should routed internal single stripline controlled impedance layer. This will help eliminate possibility radiated interfering emissions. unused inputs S3045 should connected volts ground through resistor. series terminating resistors should placed close source possible. 2.488 Gbps lines turns layout. Uniform bend radius abrupt turns) recommended layout.
September 2000 Revision
OC-48 APPLICATION NOTE S3041/42/45/76, S1202 LUCENT FIBER OPTIC XCVR
Power Grounding
Each device power must equipped with 0.01 capacitor. capacitor should positioned close power possible. ground-side decoupling capacitors should immediately feed into solid ground plane without meandering lines. power should distributed through very short minimum mil. trace directly connected power pin. Note S3041 S3042 Board Decoupling Guidelines should also followed conjunction with this application note. Device ground pins should immediately ground plane, without meandering lines. Ground should consist single continuous plane encompassing full area. good separate analog digital power feeds with PI-filter sections isolate each power sub-net. Inductors ferrite beads used PI-filter sections should: handle load current without significant drop have self-resonance characteristics that concern specific filtering task. needed isolated power plane built internal signal layer.
Conclusion
AMCC STS-48/STM-16 solution with Lucent fiber optic transceiver combine make complete STS-48/ STM-16 Physical Media Dependent (PMD) layer SONET/SDH data transfer.
Disclaimer
circuit presented this application note based data sheet information well standard implementation termination schemes. been built tested environment.
September 2000 Revision
OC-48 APPLICATION NOTE S3041/42/45/76, S1202 LUCENT FIBER OPTIC XCVR
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 2000 Applied Micro Circuits Corporation D113/R168
September 2000 Revision
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