AN300-08 Using Serial Port ADMC300 UART Interface AN300-08

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AN300-08 Using Serial Port ADMC300 UART Interface AN300-08

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Using Serial Port ADMC300 UART Interface
AN300-08
Using Serial Port ADMC300 UART Interface
AN300-08
Analog Devices Inc., January 2000
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Using Serial Port ADMC300 UART Interface
AN300-08
Table Contents
SUMMARY.
PRINCIPLE OPERATION
Introduction UART communication serial port ADMC300 Serial port configuration.4 Hardware requirements.4
UART LIBRARY ROUTINES
Using UART routines.5 UART interface
Implementation UART routines 2.3.1 initialisation SPORT0: UART0_Init_ 2.3.2 transmitter routine: UART0_Write_.7 2.3.3 receiver routine: UART0_Read_
USAGE LIBRARY: EXAMPLE
main program: main.dsp.11 main include file: main.h
ADDITIONAL COMMENTS.
Receiver configuration Reliability communication Interrupt configuration context swapping
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Summary
This application note describes serial port ADMC300 DSP-based motor controller universal asynchronous receiver/transmitter (UART) interface. This interface widely used instance serial communication with PCs. software described herein contains subroutines sending receiving data, which permits easy usage user applications, will shown example.
Principle operation
Introduction
Universal Asynchronous Receiver/Transmitter (UART) controller component serial communications subsystem computer. UART takes bytes data transmits individual bits sequential fashion. destination, second UART re-assembles bits into complete bytes. Asynchronous transmission allows data transmitted without sender having send clock signal receiver. Instead, sender receiver must agree timing parameters advance special bits added each word, which used synchronise sending receiving units. When word given UART asynchronous transmissions, called "Start Bit" added beginning each word that transmitted. Start used alert receiver that word data about sent, force clock receiver into synchronisation with clock transmitter. After Start Bit, individual bits word data sent, with Least Significant (LSB) being sent first. Each transmission transmitted exactly same amount time other bits, receiver "looks" wire approximately halfway through period assigned each determine "0". sender does know when receiver "looked" value bit. sender only knows when clock says begin transmitting next word. When entire data word been sent, transmitter so-called Parity Bit, which used receiver perform simple error checking. However, this feature used this example. Then, least Stop sent transmitter. Stop does appear when supposed UART considers entire word garbled will report Framing Error host processor when data word read. Regardless whether data received correctly not, UART automatically discards Start Stop bits. another word ready transmission, Start word sent soon Stop previous word been sent. Because asynchronous data "self synchronising", there data transmit, transmission line idle.
UART communication serial port ADMC300
Because serial ports ADMC controller inherently synchronised clock signal (SCLK), UART interface emulated software. This achieved follows: Given baud-rate desired UART communication, serial clock three times this value. That entails that each transmitted from host, ADMC will read three (ideally identical) bits. software then provides extracting middle three, which considered correct value, assemble extracted bits into byte data. Similarly, each that sent host, ADMC required repeat value three SCLK cycles. protocol that used this example requires start bit, followed eight data bits (one byte) stop bit. parity used. That means that each data byte, serial port will send receive bits, depicted Figure routines described herein provide converting byte into this format vice-versa. Analog Devices Inc., January 2000 Page
Using Serial Port ADMC300 UART Interface Data format: UART Equivalent bit-pattern SPORT0 StartBit zeros Data Byte bits
AN300-08 StopMSB ones
Byte represented bits
Figure Data format UART start-, stop-bit, parity) BOTTOM equivalent format SPORT0 operation
Serial port configuration
Since each byte data exchanged serial interface actually requires bits transmitted received, split SPORT registers into halves bits. word-length SLEN therefore 141. data right justified into bits transmit receive buffer registers. recommended configuration transmitter alternate framing mode, internally generated active frame sync signal. serial clock course generated internally, too. receiver differently each half. first half received unframed mode (alternate framing). second word, external frame sync required (active high). More details about this found section 4.1.
Hardware requirements
serial interface consists transmitter data line (pin ADMC300) receiver data line (pin ADMC300). order generate interrupts, receiving data line must tied also RFS0 ADMC300. shifting from level +5V) UART levels (-10V +10V) required (for instance, when communicating with PC), some additional hardware necessary. schematic shown Figure makes AD7306 converter. Also, side isolated from other device means standard opto-couplers such HCPL0630. course, AD7306 only needed RS232 voltage levels required. isolation also optional. routines presented here could used implement SCI/UART type interface between processors voltage levels. that case, only pull-up resistors (RSF0 still tied DR0) required.
Refer ADSP-2100 Family User's Manual, chapter Page
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VDD1
AN300-08
C1R2IN T1OUT T2OUT R1IN(B) R1IN/R1IN(A) T3OUT(B) T3OUT(A) VC2C2+ R2OUT T1IN T2IN R1OUT T3IN 232/422SEL
0.1uF DGND1
VDD1
DGND1
0.1uF 0.1uF
R2OUT T1IN R2OUT
0.1uF
RFS0
0.1uF
UART CONN
VDD1 0.1uF DGND1
HCPL0630
VDD1
DGND
T1IN DGND1
0.1uF
AD7306JR
DGND1
HCPL0630
VDD1 ISOLATED FROM
Figure Recommended UART interface with level shifting isolation
UART Library Routines
Using UART routines
UART routines developed easy-to-use library, which linked user's application. library consists files. file "uart0.dsp" contains assembly code required subroutines. This package compiled then linked application. user simply include header file "uart0.h", which provides function-like calls routines. routines require some configuration constants, which declared dedicated section main include-file "main.h" that comes with every application note. more information about general structure application notes including libraries into user applications refer Library Documentation File. Section shows example usage this library. following sections each routine explained detail with relevant segments code which found either "uart0.h" "uart0.dsp". more information (e.g. about register use) comments those files. following table summarises macros defined this library. Operation Initialisation Read Byte from Host Write Byte Host Usage UART0_Init; UART0_Read(register); UART0_Write(register constant);
Table Command overview There initialisation routine UART0_Init that invoked prior using interface. After that data bytes sent received from host calling routines UART0_Write UART0_Read, respectively.
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UART interface
library accessed including header file "uart0.h" application code, already explained previous section. expects some constants defined "main.h". These parameters that user want modify, namely namely frequency crystal that used board (CLKIN; defaults value evaluation board ADMC300) desires transfer speed. constant UART0_Baudrate defines latter. Common values this parameter 1200, 2400,., 115200 [baud/sec]. configuration values SPORT0 then derived from these constants.
Constants that need defined main.h: .CONST Cry_clock xxxx; Crystal clock frequency [kHz] .CONST UART0_Baudrate xxxx; Desired Baudrate [Baud]
header file gives external access UART-routines. mostly self-explaining. Note last macros used pass parameter.
.MACRO UART0_Init; call UART0_Init_; .ENDMACRO; .MACRO UART0_Write(%0); AX0=%0; call UART0_Write_; .ENDMACRO; .MACRO UART0_Read(%0); call UART0_Read_; %0=AX0; .ENDMACRO;
Implementation UART routines
following more detailed description interface code included file "uart0.dsp" will given. next sections will describe initialisation (including definitions declarations), receiver- transmitter-routines separately.
2.3.1 initialisation SPORT0: UART0_Init_
clock speed SPORT calculated from configuration parameters. Next, some variables declared which used locally this module. Their will described more detail following sections. Note that there variable called UART0_Status, which represents UART status every time. This achieved through flag bits variable. They defined after declaration section.
Calculate Configuration Register Contents from Parameters Ratio between Crystal frequency frequency serial port clock Local Variables Defined this Module .VAR/RAM/DM/SEG=USER_DM .VAR/RAM/DM/SEG=USER_DM .VAR/RAM/DM/SEG=USER_DM .VAR/RAM/DM/SEG=USER_DM .VAR/RAM/DM/SEG=USER_DM .VAR/RAM/DM/SEG=USER_DM .VAR/RAM/DM/SEG=USER_DM RX0_DATA; TX0_DATA; RX0A; RX0B; TX0A; TX0B; UART0_Status; .CONST UART0_Clk
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.VAR/RAM/DM/SEG=USER_DM .VAR/RAM/DM/SEG=USER_DM
TX0_Isr_context_backup; RX0_Isr_context_backup;
{only needs saved {only needs saved
Local #defines this Module #define UART0_FirstWordReceived #define UART0_SecondWordReceived #define UART0_ReceiveBufferFull #define UART0_FirstWordTransmitted #define UART0_SecondWordTransmitted #define UART0_TransmitBufferNotEmpty
actual assembly code analysed. UART0_Init_ subroutine initialises SPORT0 registers with appropriate constants mode described section 1.3, reception first half. Then status flags reset, indicating that there pending transmissions data been received. last, routine enables serial port after clearing pending (and desired) interrupt. call this routine necessary every application before making UART interface.
UART0_Init_: .CONST UART0_Configuration b#0101111001001110; Configuration: Internally generated serial clock ISCLK Receive frame sync required RFSR Receive alternate framing mode RFSW Transmit frame sync required TFSR Transmit alternate framing mode TFSW Internal transmit frame sync ITFS Internal receive frame sync IRFS Internal receive frame sync IRFS Internal receive frame sync IRFS Transmit frame sync active INVTFS=1 Receive frame sync active HIGH INVRFS=0 Data format right just., filled DTYPE =b#00 Word length bits SLEN =0xe Clear_Bit_DM(sport0_ctrl_reg, 14); Write_DM(sport0_sclkdiv, UART0_Clk {sets serial clock frequency} Write_DM(sport0_ctrl_reg, UART0_Configuration); Write_DM(UART0_Status, 0x0000); {clear status flags
UART0_RX_Isr); Vector UART0_RX_Isr UART0_TX_Isr); Vector UART0_TX_Isr 0x0060; IMASK; setbit setbit IMASK Set_Bit_DM(SYSCNTL, 12); rts; {clear pending SPORT0 interrupts {enable receive transmit interrupts SPORT0
{enable SPORT0
2.3.2 transmitter routine: UART0_Write_
transmitter routine makes three status flags order ensure correct sequence operations. flag UART0_TransmitBufferNotEmpty indicates that previous transmission still progress when set. initially polled until there pending transmissions, i.e. buffer empty. this point demanded transmission initiated. above mentioned flag set, other bits, namely UART0_FirstWordTransmitted UART0_SecondWordTransmitted cleared indicate that none words been transmitted yet. data byte processed generate 15-bit words sent. next action that required send first word
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update status flag UART0_FirstWordTransmitted setting which indicates that first word been transmitted. correct operation under conditions, these operations interrupted other service routine. This ensured adopted sequence disabling interrupt, performing actions enabling interrupts after that again. SPORT will generate interrupt soon ready transmit another word. This will call interrupt service routine UART0_TX_Isr, which provides sending word after checking status. Again, updating status sending word interruptible means sequence described above. This time flag UART0_SecondWordTransmitted set. SPORT will generate another interrupt when ready next transmission. Now, since status indicates that both halves sent, further transfer required UART0_TransmitBufferNotEmpty cleared indicate that next transmission started.
With general description above following pieces code should mostly self-explaining. routine UART0_Write_ the, globally accessible, entry point, which initiates transmission data contained low-byte ax0. corresponding code shown below.
UART0_Write_: ar=dm(UART0_Status); ar=TSTBIT UART0_TransmitBufferNotEmpty jump UART0_Write_;{ Wait until previous transfer completed ar=dm(UART0_Status); ar=CLRBIT UART0_FirstWordTransmitted ar=CLRBIT UART0_SecondWordTransmitted None Bits been transmitted ar=SETBIT UART0_TransmitBufferNotEmpty Indicate that Transmission progress dm(UART0_Status)=ar; call PROCESS_TX0; Build words sent from data
ar=dm(UART0_Status); ar=SETBIT UART0_FirstWordTransmitted INTS; following instructions uninterruptible dm(UART0_Status)=ar; update status TX0=dm(TX0A); send half (the handled INTS; interrupt service routine) rts;
interrupt service routine reported hereafter. worth note, that only register that used this routine. been decided therefore save explicitly into backup variable restore before exiting routine instead switching secondary register ADMC300. This leaves option nesting interrupts without having worry about register alterations another service routine written final user.
UART0_TX_Isr: DM(TX0_Isr_context_backup) {save context
dm(UART0_Status); TSTBIT UART0_TransmitBufferNotEmpty jump Exit_TX0_Isr; buffer empty nothing
dm(UART0_Status); TSTBIT UART0_SecondWordTransmitted jump SendSecondWord; First word been transmitted send second} dm(UART0_Status); CLRBIT UART0_TransmitBufferNotEmpty dm(UART0_Status)=ar; second word been transmitted reset status jump Exit_TX0_Isr;
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SendSecondWord: dm(UART0_Status); ar=SETBIT UART0_SecondWordTransmitted INTS; following instructions uninterruptible dm(UART0_Status)=ar; update status TX0=dm(TX0B); send half INTS; Exit_TX0_Isr: DM(TX0_Isr_context_backup); rti;
{restore context
remaining part actual conversion from data-byte 30-bit word transmitted. word built shift register sr0. First, stop (represented binary sequence 111) inserted into positions 25-27. Then, each inserted, corresponding sequence will ORed into register positions 28-30. Simultaneously, whole register shifted down three positions, next inserted same positions previous one. After loop, shift register made from right left, stop bit, eight data bits (represented bits), beginning with most significant bit, start (000, inserted automatically shift operations). These bits occupy positions register. reason this that, since SPORT requires bits aligned right, upper half shifter contains first word transmitted already aligned properly, lower half needs only shifted position right correct alignment. last instructions this store register contents into buffer variable TX0A TX0B data memory.
PROCESS_TX0: dm(TX0_DATA)=ax0; =ax0; LSHIFT (LO); ax0= sr0; sr1=0x0e00; sr0=0x0; cntr {insert bits into Insert_Bit until ay0=ax0; {left shift bit, highest into carry flag ax0= {store shifted value ar=sr1; {store higher word preserve previous status jump Bit_0; {test shifted into carry Bit_1: ay0=0x7000; expand 111(aligned positions 28-30) ay0; {ar=111 ored into current higher word Bit_0: LSHIFT (LO); {shift word down three positions Insert_Bit: sr=sr LSHIFT (HI); {for next insert current after bits, word aligned bits 1-30 start automatically positions 28-30 (000) save content ar=byte transmitted shift data byte into high-byte}
{stop position 25-27, will shifted down when inserting data bits}
dm(TX0A)=sr1; {TX0A gets MSBs highword LSHIFT (LO); dm(TX0B)=sr0; {TX0B gets LSBs from aligned right ax0=DM(TX0_DATA); rts; {restore content
2.3.3 receiver routine: UART0_Read_
transmitter routine makes three status flags order ensure correct sequence operations. flag UART0_ReceiveBufferFull indicates that complete 30-bit word been received ready being processed, when set. initially polled until word received, i.e. buffer full. this point data byte extracted from 30-bit word stored into ax0. status reset indicate that routine ready operation. Unlike transmitter, receiving routine Analog Devices Inc., January 2000 Page
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control over start data transfer. When word received SPORT generates interrupt. Depending status flags, namely UART0_FirstWordReceived UART0_SecondWordReceived, service routine undertakes different actions. When UART0_FirstWordReceived cleared, indicating that none words been received yet, word stored RX0A, SPORT0 receiving mode second half status updated. flag UART0_SecondWordReceived cleared, word goes second half RX0B, SPORT0 receiving mode next first half status updated. none above conditions true then currently received word received before Read_UART0 processed previous words. that case, word removed from SPORT0 receive register lost further operation.
With general description above following pieces code should mostly self-explaining. routine UART0_Read_ the, globally accessible, entry point, which waits data received over SPORT0. then extracts data-byte stores low-byte ax0. corresponding code shown below.
UART0_Read_: ar=dm(UART0_Status); ar=TSTBIT UART0_ReceiveBufferFull jump UART0_Read_; wait until complete byte been received call PROCESS_RX0; extract byte from word
ar=dm(UART0_Status); ar=CLRBIT UART0_FirstWordReceived ar=CLRBIT UART0_SecondWordReceived ar=CLRBIT UART0_ReceiveBufferFull dm(UART0_Status)=ar; restore status ready reception ax0=dm(RX0_DATA); rts; store data into
interrupt service routine reported hereafter. transmitter service routine, only register that used this routine. Again same reason, saved explicitly into backup variable restored before exiting routine instead switching secondary register ADMC300.
UART0_RX_Isr: DM(RX0_Isr_context_backup) save context
dm(UART0_Status); TSTBIT UART0_FirstWordReceived Jump SecondWord; first word already received ar=dm(Sport0_Ctrl_Reg); ar=SETBIT dm(Sport0_Ctrl_Reg)=ar; dm(RX0A)=RX0;
SPORT receive mode half store first word
dm(UART0_Status); ar=SETBIT UART0_FirstWordReceived dm(UART0_Status)=ar; update status flags jump Exit_RX0_Isr; SecondWord:
dm(UART0_Status); TSTBIT UART0_SecondWordReceived Jump FlushWord; this second half ar=dm(Sport0_Ctrl_Reg); ar=CLRBIT dm(Sport0_Ctrl_Reg)=ar; prepare SPORT0 next half
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DM(RX0B)=RX0;
store second word
dm(UART0_Status); SETBIT UART0_SecondWordReceived SETBIT UART0_ReceiveBufferFull dm(UART0_Status)=ar; indicate that complete byte been received jump Exit_RX0_Isr; FlushWord: ar=RX0; Exit_RX0_Isr: DM(RX0_Isr_context_backup); rti;
restore context
remaining part actual conversion from 30-bit word data-byte. received word aligned bits shifter (the stop shifted right side order align middle first bit). Then, loop, each read from position inserted into word shifted right three positions. Therefore data-byte built from middle each triple bits.
PROCESS_RX0: mr1=DM(RX0A); mr0=DM(RX0B); LSHIFT (LO); {1st half received RX0A {2nd half received RX0B
shift stop bits middle sr=sr LSHIFT (HI); shifted down or'd ay1=0x0; contains final byte
ay0=0x1; CNTR 0x7; extract seven bits Extract_Bit until extract into byte ay1=ar; also create mirror image shift left ay1=ar; mr0=sr1; LSHIFT (LO); shift word down Extract_Bit: sr=sr LSHIFT (HI); next ay0; ay1; DM(RX0_DATA)=ar; rts; extract final byte created store RX0_DATA buffer
Usage library: example
main program: main.dsp
example demonstrates communication between host ADMC300, while simultaneously generating three-phase sine wave means block. application already been described previous note2. This section will only explain intuitive additions made that application. duty-cycle values generated within interrupt service routine.
AN300-03: Generation Three-Phase Sine-Wave Page
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main loop used processing received bytes data, echoing them back increase decrease frequency sine-wave whenever received. file "main.dsp" contains initialisation Sync Trip interrupt service routines. activate, build executable file using attached build.bat either within your prompt clicking from Windows Explorer. This will create object files main.exe example file. This file Motion Control Debugger. following, brief description additional code (put evidence bold characters) given.
Start code declaring start location program memory
Main_Program;
Next, general systems constants, configuration constants UART configuration parameters (main.h next section) included. Also included library, trigonometric library UART interface.
Include General System Parameters Libraries #include <main.h>; #include <pwm300.h>; #include <trigono.h>; #include <uart0.h>;
Variables, Labels Scope definitions identical AN300_03.
omissis
Note initialisation UART interface.
Startup: UART0_Init; PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR); 0x80; Clear pending IRQ2 inter. 0x200; unmask irq2 interrupts. IMASK; ay0; IMASK IRQ2 ints fully enabled here
main loop: Instead just waiting interrupts, this time main loop executes routine receiving data byte. Read_UART0 polls status until byte received from host. Nevertheless, interrupt service routine still executed with desired frequency. soon byte received, echoed back with call Write_UART0. After that, value compared with ASCII codes respectively. equal them, reference value AD_IN modified increment +0x100 -0x100. Then cycle begins again.
Main: UART0_Read(AR); UART0_Write(AR); ay1= 0x100; ay0=43; {ascii code '+'} ar=ax0-ay0; jump Comp_minus; DM(AD_IN); +ay1; DM(AD_IN)=ar; jump MAIN; Comp_minus: ay0=45; {ascii code '-'} ar=ax0-ay0; jump MAIN; DM(AD_IN); -ay1; DM(AD_IN)=ar; jump Main; Wait interrupt occur, meanwhile handle UART communication}
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RTS;
interrupt service routine generates duty-cycle values block. This routine makes secondary register ADMC core. This allows single cycle context switching, order interfere with main loop actions. Refer cited application note more details
Interrupt Service Routine PWMSYNC_ISR: sec_reg; DM(AD_IN); dm(Theta); Delta; mx0*my0 (SS); dm(Theta) mr1; Sin(mr1); ar*my0 (SS); dm(VrefA) mr1; dm(Theta); TwoPioverThree; ay1; Sin(ar); ar*my0 (SS); dm(VrefB) mr1; dm(Theta); TwoPioverThree; ay1; Sin(ar); ar*my0 (SS); dm(VrefC) mr1; {Clear {Preload Theta {Compute angle store Result register Multiply Scale VrefA
Compute angle phase
Result register Multiply Scale VrefA
Compute angle phase
Result register Multiply Scale VrefA
DM(VrefA); DM(VrefB); DM(VrefC); ay1= DM(Theta); RTI;
main include file: main.h
This file contains definitions ADMC300 constants, general-purpose macros configuration parameters system library routines. should included every application. more information refer Library Documentation File.
This file mostly self-explaining. relevant section this example shown here. described Library Documentation File, every library routine section "main.h" configuration parameters. following defines parameters UART interface used this example. baudrate expressed Baud.
Library: UART0 file UART0.dsp Application Note: Using serial port UART .CONST UART0_Baudrate =115200; {Desired Baudrate [Baud]
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Additional comments
Receiver configuration
mentioned section 1.3, interface requires different SPORT configuration each halve received word. reason this explained means measured timing diagram, such shown Figure represented relation between serial clock data receive line only indicative since data transmitted asynchronously from host. receiver initially with RFSR (receive frame sync required) equal zero. This entails that frame sync signal (tied data receive line) required only beginning data acquisition. Therefore, continuous stream data would read When first halve read, SPORT0 generates interrupt (the first glitch bottom track figure below) starts reading next bits. interrupt routine changes configuration setting RFSR bit. SPORT0 will from only acquire data frame sync signal applied. However, current word (the halve) still read. When this word completely transferred, second interrupt generated service routine resets RFSR initial condition. UART specification requires line held high. SPORT0 will only recognise frame sync signal when goes again, which when start-bit next data sent. Refer figures 5.13 5.15 ADSP 2100 family user's manual more information.
Figure Typical timing diagram during receive operation. Top: serial clock SCLK0; MID: data receive DR0; BOTTOM: execution interrupt service routine UART0_RX_Isr.
Reliability communication
Since process receiving nature SPORTs, trying synchronise inherently asynchronous signal internal serial clock, certain misinterpretations cannot avoided with these simple, three-times oversampling, routines. falling edge start-bit fall anywhere within cycle serial clock. receiver then stores bits falling edges serial clock. However, falling edge start-bit coincides with falling edge clock, that erroneously read whole word anticipated bit. This lead incorrect interpretation. Tests have Analog Devices Inc., January 2000 Page
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shown that this occurs with probability approx. 80ppm, when data continuously sent. probability decreases drastically delays inserted between single bytes transmitted. order avoid unacceptable behaviours, recommended echo received data host, which should check eventual misinterpretation. more robust transmission required, three-times sampling suited. think increasing sampling factor This entails more complicate routines since more words have read sent each byte, other hand allow error detection correction testing more samples each implementing some kind majority tests.
Interrupt configuration context swapping
mentioned sections 2.3.2 2.3.3, been decided primary registers interrupt service routines manually save context rather than swapping secondary provides with ADSP-21xx core. reason that serial communication tasks normally strongly linked main loop routines. Since there only register that required service routines, overhead created context saving instruction critical. advantage this approach that option nesting interrupts, such service routines with serial communication routine left user this interface. shown example, routine swaps registers, nested with serial interrupts with additional code.
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AN300-08 Using Serial Port ADMC300 UART Interface AN300-08

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