APEX 20KE vs.Virtex-E Devices Product Information Bulletin A
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LVDS Comparison
APEX 20KE vs.Virtex-E Devices
Product Information Bulletin
August 2000, ver.
Introduction
low-voltage differential signaling (LVDS) input/output (I/O) standard data interface standard that supports high-speed data transfers. Unlike other single-ended voltage standards, such complementary metal-oxide semiconductor (CMOS) standard transistor-to-transistor logic (TTL) standard, LVDS uses differential signals. Differential signals increase noise margins, design performance, design reliability. LVDS also allows reduced signal swing resulting shorter switching times higher bandwidth. This product information bulletin compares LVDS solutions offered APEX 20KE devices Virtex-E devices shows APEX 20KE devices offer better LVDS solutions than Virtex-E devices. following topics discussed:
LVDS standard Overview LVDS features LVDS receiver implementation LVDS transmitter implementation LVDS timing specifications LVDS software support Board level issues
LVDS Standard
Table compares LVDS standard other differential standards.
Altera Corporation
A-PIB-029-01
LVDS Comparison: APEX 20KE Virtex-E Devices
Table Comparison LVDS Other Differential Standards Standard
LVDS ECL/PECL PCML Notes:
Gbps: gigabits second; Mbps: megabit second. LVDS standard specifications derived from TIA/EIA-644 standard IEEE 1596.3 standard. Emitter-coupled logic (ECL) positive emitter-coupled logic (PECL) differential standards used skew clock networks transferring data. Pseudo current mode logic (PCML) differential standard that used power applications. Universal serial (USB) differential standard used peripherals.
Voltage Swing
300-600
Common Mode Voltage
Speed
Gbps Mbps Mbps Mbps
Compared other differential standards, LVDS fastest data transfer speed lowest power consumption, which makes best solution physical layer interfaces. APEX 20KE devices support LVDS standard True-LVDS interface. True-LVDS interface supports data channels high-speed data transfer rates fast Mbps. True-LVDS interface also supports differential LVDS clock input synchronize data transfers. APEX 20KE devices have built-in True-LVDS receivers True-LVDS transmitters that coupled LVDS receivers LVDS drivers. using internal phase-locked loops (PLLs), True-LVDS receivers True-LVDS transmitters offer data transfer modes. Additional deskew circuitry corrects board-level skew between data clock accurate data capture.
more information, Using LVDS APEX 20KE Devices White Paper. Four Xilinx application notes, XAPP230: LVDS Standard, XAPP231: Multi-Drop LVDS with Virtex-E FPGAs, XAPP232: Virtex-E LVDS Drivers Receivers Interface Guidelines, XAPP233: Multi-channel LVDS Data Transfer with Virtex-E Devices, describe LVDS emulation Virtex-E devices. However, analysis LVDS capability Virtex-E devices shows that LVDS implementation only support medium speed LVDS data transfer rates; unlike APEX devices, Virtex-E devices cannot support high speed LVDS data transfer rates.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Overview LVDS Features
This section describes compares LVDS features APEX 20KE devices Virtex-E devices.
True-LVDS Features APEX 20KE Devices
APEX 20KE devices include following LVDS features:
Dedicated True-LVDS circuitry incorporated silicon level Facilitates LVDS implementation Ensures that complex timing issues with minimal design efforts Dedicated True-LVDS receiver circuitry True-LVDS transmitter circuitry Supports multiple channels Performs critical serial-to-parallel parallel-to-serial conversions required convert high-speed LVDS signal rates system speeds Special-purpose PLLs Supports several LVDS data transfer modes, including data transfer modes Allows APEX 20KE devices interface with industry-standard 78-MHz clock Deskew Circuitry Implements deskew feature ensure accurate data capture compensate board-level skew
Together, these features combine create robust LVDS solution. Figure shows True-LVDS interface example APEX 20KE device that operates Mbps. Figure APEX 20KE True-LVDS Interface Example
Mbps 1-Bit Data Mbps 8-Bit Data
Serial-to-Parallel Converter
Logic Other LVDS Interfaces Mbps 1-Bit Data Parallel-to-Serial Converter Mbps 8-Bit Data
LVDS Clock
APEX 20KE Device
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
LVDS Virtex-E Devices
Virtex-E devices include following LVDS features:
Emulated LVDS dedicated LVDS circuitry silicon level Emulated LVDS receiver LVDS transmitter Consumes device resources, such block RAMs Reduces Virtex-E device capacity 311-MHz LVDS clock direct interface with other standard LVDS devices because standard devices require 78-MHz LVDS clock Delay-locked loops (DLLs) Supports only data transfer modes Needs external device, such XCV50E device, mode Needs derive clock cascading DLLs inside XCV50E device Increases clock jitter DLLs Does support data transfer mode Cannot interface with industry-standard devices, such National Semiconductor LVDS interface that mode
Figure shows LVDS interface example Virtex-E device. Figure Virtex-E LVDS Interface Example
External Circuit
Virtex-E Device
External Circuit
Receiver Interface other LVDS devices
Transmitter Interface other LVDS devices
Comparison Available Data Transfer Modes
Table compares available data transfer modes APEX 20KE devices Virtex-E devices.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Table Comparison Available Data Transfer Modes Data Transfer Mode
Note:
Data transfer modes based Virtex-E LVDS implementation described Xilinx Application Note XAPP233: Multi-channel LVDS Data Transfer with Virtex-E Devices.
APEX 20KE
Virtex-E
Requires external circuitry
LVDS Receiver Implementation
This section compares LVDS receiver implementation APEX 20KE devices Virtex-E devices.
APEX 20KE True-LVDS Receiver Implementation
APEX 20KE True-LVDS receiver implemented dedicated LVDS circuitry. Figure shows example True-LVDS receiver APEX 20KE device operating Mbps, transfer mode.
Figure True-LVDS Receiver Circuit APEX 20KE Device
APEX 20KE LVDS
Serial Data Mbps data[7.0] Serial-to-Parallel Converter
CLK_LVDS2 Clock
Dedicated Clock
True-LVDS receiver accepts 105-MHz clock. This clock multiplied with create internal 840-MHz clock. This 840-MHz clock samples data converts serial data parallel data using dedicated serial-to-parallel converter circuit. Internal logic access parallel data. LVDS configured clock multiplication, allowing receiver support transfer modes. True-LVDS receiver support data channels that each speeds Mbps.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Virtex-E LVDS Receiver Implementation
Because Virtex-E devices have dedicated LVDS circuitry silicon level, LVDS receiver LVDS transmitter must designed separately. XAPP233: Multi-channel LVDS Data Transfer with Virtex-E Devices describes LVDS receiver implementation that been validated only software emulation. Analysis LVDS receiver implementation suggests that would have difficulty operating Mbps real design. LVDS receiver implementation described XAPP233 requires on-board clock running achieve data rate Mbps. Each data channel requires registers that clocked rising edges falling edges 311-MHz clock. data captured these registers passed 4-bit registers that serial-to-parallel converter. prescaler, consisting cascaded multiplexers, steps clock frequency down MHz. Then 155-MHz clock clocks parallel data that will stored block RAM. receiver also requires external clock running 77.75 shift data block RAM. achieve 622-Mbps data rate Virtex-E devices, signal routing between configurable logic block (CLB) registers block must tightly controlled placing block close possible CLB. This implementation requires both hand routing hand placement only applies data transfer mode. Both data transfer modes require separate implementations with different constraint files guide files each implementation.
Timing Issues with Virtex-E Receiver Implementation
equalize path delays different registers, dummy load required. According XAPP233, dummy load placed appropriate locations, delays reduced within picoseconds (ps). However, results show that Virtex-E devices cannot generate repeatable delays with accuracy. Furthermore, since timing parameters vary with operating conditions, dummy load placement will vary. dummy load placement that works under operating conditions work under different operating conditions. Therefore, Virtex-E LVDS implementation cannot function throughout device's operating range.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Because Virtex-E LVDS implementation requires that clock global line, LVDS clock routed local interconnects inside Virtex-E device. This non-global clock will have clock skew problems. XAPP233 specifies that maximum clock skew This skew number solely derived from software from characterization data. Considering behavior silicon, very difficult guarantee clock skew values exactly XAPP233 identifies worst-case delay data captured 4-bit registers 2,925 worst-case delay clock 2,166 This indicates potential race condition between clock data. work correctly, LVDS receiver implementation requires that data clock delays match adjust using similar routing clock paths data paths. However, timing these routing resources depends upon operating voltage, temperature, fan-out. Therefore, valid LVDS operations, design re-routed different devices different operating conditions.
LVDS Transmitter Implementation
This section compares LVDS transmitter implementation APEX 20KE devices Virtex-E devices.
APEX 20KE True-LVDS Transmitter Implementation
APEX 20KE True-LVDS transmitter implemented dedicated LVDS circuitry. Figure shows example True-LVDS transmitter circuit APEX 20KE device operating data transfer mode.
Figure LVDS Transmitter Circuit APEX 20KE Device
APEX 20KE LVDS Interface
Serial Data Mbps
data[6.0] Built-In Parallel-to-Serial Converter
66-MHz CLK_LVDS3
Internal Global Clock
CLKLVDS_OUT3
Internal Global Clocks
Figure built-in parallel-to-serial converter serializes data that will transmitted through differential channels.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
user configure APEX drivers true differential LVDS drivers that drive true complement signals each channel. Like True-LVDS receiver, True-LVDS transmitter utilizes internal that offers clock multiplication. Figure shows example functionality APEX 20KE device. Figure Example Functionality APEX 20KE Device
Allows conversion 8-bit parallel CMOS data.
LVDS
LVDS Clock
Dedicated Clock
usage ensures that both critical setup times hold times met. create LVDS clock signal, non-multiplied output routed pins. usage also minimizes skew between data transmitted LVDS clock.
Virtex-E LVDS Transmitter Implementation
Like LVDS receiver, LVDS transmitter must implemented with hardware emulation Virtex-E device. XAPP233 describes LVDS transmitter implementation using CLBs block RAMs. transfer data Mbps, transmitter must have on-board clock operating 77.75 MHz. cascaded DLLs used increase clock frequency MHz. parallel data then internal shift registers, that parallel-to-serial converter network. Using these shift registers more internal registers, alternate bits data multiplexer. 311-MHz clock, with 3.2-ns period, controls select line multiplexer. Within each clock cycle, consecutive bits data streamed using double data rate technique. Thus, output multiplexer switches (622 Mbps). second multiplexer generates LVDS clock output from transmitter. This second multiplexer balances delays associated with clock data paths reduces skew between clock data signals.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Both data clock signals then inverted near element create true complementary outputs. voltage swing between signal complement external, on-board voltage divider circuit, which consists resistor packs, used step down swing from LVDS voltage (maximum swing.
Timing Issues with Virtex-E Transmitter Implementation
implementation described XAPP233 only works data transfer mode. limitations support industry-standard mode, modes require separate implementations. These modes described XAPP233 must user-designed. work correctly, LVDS implementation requires propagation delay less than between internal registers multiplexer. delay between shift registers internal registers must also less than minimum maximum delays-both which must these paths-can only hand routing with constraint files guide files. Even user successfully create guide files, both minimum maximum delays cannot simultaneously satisfied. implementation expects 311-MHz clock routed global line. Furthermore, registers 2-to-1 multiplexers must MHz. This high performance clock implies that clock setup (tSU), clock hold (tH), clock-to-output (tCO)times must guaranteed every register that used implementation, task that very difficult achieve.
LVDS Timing Specifications
This section compares LVDS timing specifications APEX 20KE devices Virtex-E devices. accurate data transfer data transfer modes, data synchronization required. Various timing parameters dictate this data synchronization well overall performance LVDS interface.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Table describes timing parameters used with LVDS. Table LVDS Timing Parameters Timing Parameter
Sampling window (SW)
Description
defines window where internal receiver clock rising edge should placed capture data. setup hold times determine ideal strobe position within sampling window. input data must valid sampling window tCCS defined timing difference between fastest slowest output edges, including variation clock skew. Skew variation arrival time signals specified arrive same time. skew occurs registered output because differences propagation delay clock signal through clock network. RSKM timing margin between clock input data input user board design, which allows LVDS cable skew jitter LVDS PLL. RSKM (Bit Time Period tCCS SW)/2
Channel-to-channel skew (tCCS)
Receiver input skew margin (RSKM)
Timing Specifications APEX 20KE True-LVDS Circuitry
Because APEX 20KE devices have dedicated True-LVDS circuitry, True-LVDS timing parameters APEX 20KE devices quantified.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Table compares timing requirements APEX 20KE devices Virtex-E devices. Table LVDS Timing Requirements APEX 20KE Virtex-E Devices Symbol Parameter Mode APEX 20KE Device (ps) Minimum
tCCS Transmitter output channel-to-channel skew RSKM Receiver skew margin with deskew Mbps Mbps Mbps RSKM Receiver skew margin with deskew Receiver input sampling window Mbps Mbps Mbps Note
Virtex-E devices have specified timing requirements. more information, "Timing Specifications Virtex-E LVDS" section this document.
Maximum
1,744
Virtex-E Device
"eye diagram" visual representation jitter output driver quality LVDS output signal. diagram obtained sending pseudo-random data over LVDS channel using sampling oscilloscope perform persistence measurement. transitions captured plotted over time. Horizontal closure jitter, while vertical closure signal attenuation noise. Therefore larger "eye" indicates better quality driver. Figure shows diagram APEX EP20K400E with True-LVDS circuitry device operating Mbps mode.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Figure True-LVDS Circuitry Diagram Mbps
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Timing Specifications Virtex-E LVDS
XAPP233 does specify timing parameters Virtex-E LVDS interface. Without these timing parameters, impossible evaluate LVDS performance Virtex-E devices. application note does mention emulation-related timings, such setup time hold time different signals. However, these timing numbers derived through software simulation. application note also shows waveforms that illustrate Virtex-E LVDS operation with 622-Mbps data transfer rate. However, these waveforms solely derived from simulation program with integrated circuit emphasis (SPICE) simulations. These waveforms have been verified Virtex-E device under operating conditions include diagram that would show driver quality.
LVDS Software Support
This section compares LVDS software support APEX 20KE devices Virtex-E devices.
True-LVDS Software Support APEX 20KE Devices
user Quartus development tool easily implement True-LVDS receivers True-LVDS transmitters APEX 20KE devices. Quartus software features megafunctions, altlvds_rx altlvds_tx, that directly implement LVDS receivers LVDS transmitters. Figure shows True-LVDS receiver True-LVDS transmitter megafunctions.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Figure True-LVDS Receiver True-LVDS Transmitter Megafunctions
NUMBER_OF_CHANNELS=16 DESERIALIZATION_FACTOR=4 REGISTERED_OUTPUT="ON" INCLOCK_PERIOD altlvds_rx rx_in[] rx_inclock rx_deskew inst rx_out[] rx_outclock rx_locked
NUMBER_OF_CHANNELS=16 DESERIALIZATION_FACTOR=4 REGISTERED_OUTPUT="ON" MULTI_CLOCK="OFF" INCLOCK_PERIOD CLOCK_SETTING="UNUSED" altlvds_tx tx_in[] tx_inclock sync_inclock inst1 tx_out[] tx_outclock tx_locked
True-LVDS transmitter True-LVDS receiver megafunctions fully customizable. customizable parameters include number data channels, deserialization factor, clock input frequency. Incorporating these megafunctions within design allows push-button compilation LVDS interface implementation multiple channels with data rates Mbps. Because True-LVDS circuits specifically designed verified silicon satisfy timing requirements associated with 840-Mbps data rate, design does require constraint file guide file. Therefore, True-LVDS interface APEX 20KE devices implemented with minimal design effort.
LVDS Software Support Virtex-E Devices
Unlike APEX 20KE devices, Virtex-E devices have drop-in solution. LVDS software support exists, equivalent megafunctions available implement LVDS receiver LVDS transmitter Virtex-E device. Instead, designer must spend significant time effort implement LVDS receiver LVDS transmitter software verify that timing meets specifications described earlier sections. Because Virtex-E LVDS implementation cannot easily scaled modified, software solution provided XAPP233 difficult unwieldy.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Board-Level Issues
This section compares following board-level issues APEX 20KE devices Virtex-E devices:
Deskew circuitry Power consumption balance Board layout issues Board level noise Board space
Deskew Circuitry
APEX 20KE devices have internal deskew circuitry that compensate board skew much ±25% time period. This deskew circuitry over-sampling circuit that captures input with four separate clocks. capture results examined determine which clock captured data correctly. This clock then used normal operation. deskew circuitry enables APEK 20KE True-LVDS circuitry work correctly high speeds even there significant board skew. Virtex-E devices have internal deskew circuitry, therefore cannot compensate board-level skew. minimize skew Virtex-E devices, stringent board layout requirements must applied. example, stringent board layout requirements will allow timing specifications will allow design scaled easily.
Power Consumption
APEX 20KE devices have True-LVDS drivers. Figure shows structure APEX 20KE True-LVDS drivers.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Figure Structure APEX 20KE True-LVDS Drivers
APEX 20KE Device Current Source (-3.5
Driver
Receiver
~350
voltage swing current APEX 20KE True-LVDS drivers very power-efficient. Figure shows structure Virtex-E LVDS drivers. Figure Structure Virtex-E LVDS Drivers
Virtex-E Device
0-2.5
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Virtex-E devices 2.5-V drivers. voltage swing 2.5-V drivers with typical current XAPP233, Virtex-E LVDS implementation uses on-board resistor divider network that consumes minimum current on-board resistor divider network makes Virtex-E devices consume times more power than APEX 20KE devices. Table compares power consumption APEX 20KE devices Virtex-E devices. Table Power Consumption Comparison Number Channels
APEX 20KE (mW)
11.2 22.4 44.8 89.6 179.2
Virtex-E (mW)
21.2 42.4 86.8 169.6 339.2
increased power consumption Virtex-E devices compromises low-power advantages LVDS standard. addition, high 2.5-V swing Virtex-E LVDS drivers produces more electromagnetic interference (EMI) than voltage swing APEX 20KE devices.
Balance
drivers APEX 20KE devices differential drivers. When using differential drivers, balance determines common mode noise skew margins. Therefore, APEX 20KE drivers have excellent balance, which leads high common-mode rejection ratio (CMRR) increase better noise immunity. Instead using differential drivers, Virtex-E devices low-voltage transistor-transistor logic (LVTTL) drivers combination with on-board resistor network. LVTTL drivers have balance generate common mode noise when used differentially. LVTTL drivers on-board resistor network reduces LVDS interface's CMRR introduces extraneous noise into LVDS signal. Figure shows balance LVDS drivers APEX 20KE devices Virtex-E devices.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Figure Balance LVDS Drivers
APEX 20KE True-LVDS Driver
Voltage
Differential Driver Driver Time
Virtex-E LVDS Driver
0-2.5
Voltage
LVTTL Driver Time
Driver
Board Layout Issues
LVDS pins APEX 20KE devices placed along outer edge device. positive negative pins each channel adjacent each other. This close proximity minimizes board-level skew between pins simplifies trace layout. Figure shows True-LVDS placement example APEX 20KE device.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Figure Example True-LVDS Placement APEX 20KE Device
LVDSTXINCLK LVDSTXOUTCLK
LVDS input output pairs placed outer ball rows minimize skew.
LVDS pins Virtex-E devices placed from each other. minimize skew, user must compensate this distance adjusting trace lengths positive channels negative channels board. According XAPP233, 311-MHz clock must delayed board relative data using additional trace lengths driver with well characterized propagation delay. user adjust trace lengths create exact delay. Depending operating conditions-which includes voltage, temperature, noise other signals, other operating conditions-trace delays vary significantly. Therefore, user able achieve required 1.1-ns delay under ideal conditions, changing operating conditions guarantee that design will work field.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Figure shows that Virtex-E LVDS transmitter needs board delay clock line. Figure On-Board Delay Required Virtex-E LVDS Transmitter
Resistor Divider Network
Termination Resistors
Delay
Clock
Clock
Clock
Virtex-E LVDS Transmitter
Virtex-E LVDS Receiver
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Figure shows proposed interface Virtex-E LVDS data transfer mode. Figure Proposed Interface Virtex-E LVDS
Other LVDS Device
Data
Data
Virtex-E Device
XCV50E Device
Clock Running 77.75
Clock Running
Board-Level Noise
Virtex-E devices have board-level noise problems. Virtex-E LVDS implementation, derived clock running output pin. Switching such high frequency lead ground bounce issues results ground-bounce problems adjacent pins. More importantly, LVDS outputs have dedicated power pins, which adds noise signals.
Board Space
described earlier sections, Virtex-E drivers LVDS drivers, LVTTL drivers. using costly on-board resistor divider networks, user must convert LVTTL drivers LVDS drivers. These on-board resistors increases board space utilization, problem that will escalate quickly with increasing number data channels. Figure shows on-board resistor packs compromise board space Virtex-E devices.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Figure On-Board Resistor Packs Board Space Virtex-E Devices
0-2.5
Resistor Divider Every LVDS Pair
APEX 20KE device drivers need external board-level components. This saves board space, simplifies board layout, offers more flexibility freedom board design.
Conclusion
Virtex-E devices have dedicated LVDS circuitry, drop-in compilation support, stringent board layout requirements, higher power consumption, require extensive design efforts. APEX 20KE True-LVDS solution offers LVDS interface that robust, flexible, easy-to-use. APEX 20KE devices outperform Virtex-E devices many levels: APEX 20KE devices have dedicated LVDS circuitry, built-in deskew circuitry, drop-in compilation support Quartus software, better on-chip LVDS placement, increased noise immunity, simple board-level design requirements, improved power efficiency. APEX 20KE True-LVDS solution offers clear advantage over Virtex-E LVDS solution.
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Notes:
Altera Corporation
LVDS Comparison: APEX 20KE Virtex-E Devices
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Altera, APEX, APEX 20KE, Quartus, True-LVDS, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2000 Altera Corporation. rights reserved.
Printed Recycled Paper.
Altera Corporation
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