Application Note April 1999, ver. Introduction Altera®

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Application Note April 1999, ver. Introduction Altera®

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Integrating Product-Term Logic APEX Devices
Application Note
April 1999, ver.
Introduction
Altera® APEX20K devices feature MultiCorearchitecture, which combines product-terms, look-up tables (LUTs), embedded memory MultiCore architecture improves system performance: product-term architecture provides higher performance combinatorial functions (e.g., address decoding complex state machines), while architecture contributes superior performance registered data path functions. This architecture eliminates off-chip delays that result from using separate product-term devices. Figure shows system performance using separate product-term devices, including typical board delay. contrast, Figure shows system performance with integrated product-term architecture.
Figure System Performance with PLDs
EPF10K100E-1
Register Product Term
EPM7064AE-4
Register
Critical Path
Figure System Performance with MultiCore Architecture
APEX 20K-1
Register Product Term Register
tLAD
Critical Path
Altera Corporation
A-AN-112-01
112: Integrating Product-Term Logic APEX Devices
more information APEX devices, APEX Programmable Logic Device Family Data Sheet. This application note describes APEX architecture explains implement product-term logic.
MegaLAB Structure
basic building block APEX family MegaLABstructure, which contains logic array blocks (LABs), each comprised logic elements (LEs); these architecturally equivalent FLEX® 6000 LEs. Each APEX MegaLAB structure also embedded system block (ESB) that configurable 2,048-bit dual-port RAM, ROM, content-addressable memory (CAM), product-term macrocells. Each macrocell contains product terms that combined through gate gate, programmable inverter wide-input functions. output each macrocell registered with each register containing clock enable asynchronous clear. register also emulate asynchronous preset using NOT-Gate PushBack option Quartussoftware. Additionally, macrocell includes parallel expanders that feed adjacent macrocell. Parallel expanders improve system performance routability, making product-term architecture ideal applications that require wide multiplexing high fan-in. Figure shows MegaLAB structure.
Figure MegaLAB Structure
MegaLAB Interconnect
Adjacent IOEs
LE10
LE10
LE10
Local Interconnect
LABs
Implements Product-Term Logic
Altera Corporation
112: Integrating Product-Term Logic APEX Devices
Product-Term Logic
product-term portion MultiCore architecture implemented with ESB. configured block macrocells ESB-by-ESB basis. Each inputs from adjacent local interconnect; therefore, driven MegaLAB interconnect adjacent LAB. Also, macrocells feed back into through local interconnect higher performance. Dedicated clock pins, global signals, additional inputs from local interconnect drive control signals. product-term mode, each contains macrocells. Each macrocell consists product terms programmable register. programmable register implement flipflops. Parallel expanders make product-term configuration ideal applications requiring wide multiplexing high fan-in. Figure shows APEX macrocell.
Figure APEX Macrocell
Parallel Expander
CLRN
Parallel Expander
Parallel expanders make product-term configuration ideal applications requiring wide multiplexing high fan-in because they used drive product terms single macrocell. Figures show APEX parallel expanders feedback, respectively.
Altera Corporation
112: Integrating Product-Term Logic APEX Devices
Figure APEX Parallel Expanders
Parallel Expanders
MC16
Local Interconnect
Implementing Product-Term Logic
Altera Corporation
112: Integrating Product-Term Logic APEX Devices
Figure APEX Feedback
Macrocells Feedback Local Interconnect
MC16
Local Interconnect
Implementing Product-Term Logic
Altera Corporation
112: Integrating Product-Term Logic APEX Devices
Improving Performance Using Product Terms
MultiCore architecture improves system performance: productterm architecture provides higher performance combinatorial functions such address decoding state machines, while architecture contributes superior performance registered data path functions. Subdesigns such wide-input functions state machines implemented more efficiently product terms; therefore, combining architectures device results better performance device utilization. Table compares performance device utilization common applications implemented product-term LUT-based architectures. Thirty-two product terms require same silicon area LEs. wide-input gate state machine faster implemented more efficiently product-term architecture, while multiplier multiplexer better implemented LUT. product-term delay APEX approximately parallel expander delays approximately
Altera Corporation
112: Integrating Product-Term Logic APEX Devices
Table APEX Performance Utilization Common Applications
Function Product Terms Performance (MHz)
32-bit gate with registered inputs outputs 8-state, 6-input/ 11-output 148-transition state machine 16-to-1 registered multiplexer
LUTs Performance (MHz)
Ideal Solution Product Term
Utilization
product term (die size equivalent LEs) product terms (die size equivalent LEs) product terms (die size equivalent LEs) product terms (die size equivalent 1,097 LEs)
Utilization
APEX Performance (MHz)
registered multiplier
Note:
Input registers included utilization numbers.
Register Placement Optimal Performance
optimal performance product-term mode, registers that used drive product terms placed that adjacent ESB. This directly drives local interconnect that drives ESB, eliminating routing delays through MegaLAB interconnect. Timing-driven compilation Quartus software will also this placement meet user-specified timing requirements. Figure
Altera Corporation
112: Integrating Product-Term Logic APEX Devices
Figure Optimal Placement Logic
MegaLAB Interconnect
LE10
LE10
Register
Product Terms
Register
Adjacent Local Interconnect
Using Turbo Mode
APEX "turbo" mode that improves performance logic implemented ESB. Quartus software provides designers with option turn this feature improved performance turn this feature reduced power consumption. Using Quartus software, implement this APEX feature ESB-by-ESB basis.
Using Quartus Software Implement Product-Term Logic
Altera's Quartus software, which supports APEX devices, allows control APEX implementation product-term mode either specific blocks logic ESB-by-ESB basis. implement product-term, LUT, configurations using Assignment Organizer dialog (see Figure page 11). RAM, ROM, logic designs implemented through megafunctions.
Altera Corporation
112: Integrating Product-Term Logic APEX Devices
Quartus software supports multiple methods implementing logic product-term mode. example, logic targeted productterm mode hierarchical level. target hierarchy level product-term mode, that hierarchy level lower levels will implemented using product-term mode configuration. using Quartus software, also target hierarchy level AUTO. Based area utilization algorithm, Quartus software automatically decides logic better implemented product terms LUTs. lower hierarchy level targeted different logic implementation than parent hierarchy level (only targeted higher level AUTO). Figure demonstrates hierarchical implementation capability logic product-term mode using Quartus software.
Figure Hierarchical Implementation
Top-Level Hierarchical Design
AUTO Assignment Product-Term Assignment Assignment
AUTO
Product Term
AUTO
AUTO
AUTO
Product Term
AUTO
Product Term
Product-Term Assignment
Logic targeted globally entity-by-entity basis. target entity product-term implementation. other instances entity occur within design, Quartus software also provides option have other instances implemented product-term mode. Figure demonstrates entity-based implementation capability logic product-term mode using Quartus software.
Altera Corporation
112: Integrating Product-Term Logic APEX Devices
Figure Entity-Based Implementation
Top-Level Hierarchical Design
Entity
Entity
Entity
Product-Term Assignment
Entity
Other instantiations same entity also implemented product-term mode.
Using Quartus software, perform following steps designate hierarchy level product-term mode. Open Project Navigator Quartus software. Right-click desired hierarchy level choose Assignments. Figure
Figure Targeting Logic Product-Term Mode
Altera Corporation
112: Integrating Product-Term Logic APEX Devices
Open list files under Options Entities Only select Technology Mapper assignment category Assignment Organizer dialog box. This selection maps logic specified mode (see Figure 11). Choose Pterm Setting drop-down list click Add/Change. Click Apply continue adjust assignments click finished.
Figure Assignment Organizer Dialog
Altera Corporation
112: Integrating Product-Term Logic APEX Devices
Third-Party Software Support
Quartus software supports product-term logic designs created Exemplar Logic, Synopsys, Synplicity, Viewlogic synthesis tools. Quartus software features true WYSIWYG (What-You-See-Is-WhatYou-Get) option that allows third-party tools synthesize product-term logic APEX architecture. Logic blocks pass through Quartus Compiler without further synthesis, ensuring optimal design implementation. WYSIWYG product-term structure passed from third-party tools Quartus software through Verilog HDL, EDIF, VHDL files. addition product-term mode, access logic, RAM, storage through third-party tools.
Conclusion
Altera's APEX devices feature MultiCore architecture, which combines product-term, LUT, embedded memory architectures. using MultiCore architecture, integrate your design into device, improving system performance. more information APEX devices Quartus software, APEX Programmable Logic Device Data Sheet Quartus Programmable Logic Development System Software Data Sheet.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: (888) 3-ALTERA lit_req@altera.com
Altera, APEX, APEX 20K, EPF10K100E, EPM7064S, FLEX, FLEX 6000, MegaLAB, MultiCore, Quartus, System-on-a-Programmable-Chip trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1999 Altera Corporation. rights reserved.
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Application Note April 1999, ver. Introduction Altera®

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