Preliminary Data Features 9254-2 CMOS Stores complete v

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Preliminary Data Features 9254-2 CMOS Stores complete v

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MBit Dynamic Sequential Access Memory Television Applications (TV-SAM) with On-chip Noise Reduction Filter
Preliminary Data Features
9254-2
CMOS
Stores complete video field (4:1:1) chip adaptive recursive noise reduction filter (4:1:1) noise reduction classes selectable Special noise reduction mode 4:2:2 applications 12-bit organization Triple port architecture 12-bit input shift register 12-bit output shift registers Shift registers independently simultaneously accessible (one output shift register used internally noise reduction filtering) Continuous data flow even maximum speed 40-MHz shift rate 0.96-Gbit/s total data rate inputs outputs TTL-compatible Tristate outputs Random access groups bits wide range applications Refresh-free operation possible power supply operating temperature range power dissipation: active, standby Suitable common standards Allows flicker noise reduction simultaneously with only field memory Applications: VCR, image processing, video printers, data compressors, delay lines, time base correctors, HDTV
P-MQFP-64-1
Type 9254-2
Ordering Code request
Package P-MQFP-64-1
Semiconductor Group
1998-01-16
9254-2
Functional Description General 9254-2 combination TV-SAM 9253 adaptive recursive filter achieve reduction noise video signals. closed loop output ports triple port memory connected internally noise reduction filter. External access this port possible. characteristic noise reduction filter adjustable three pins (CLASS2, CLASS1, CLASS0).
SDC0 NR422 CLASS
Noise Reduction Filter
Port Field Memory
Port
Port
SQA0
UEB10379
Figure Block Diagram memory capacity 9254-2 enables field based filtering 4:1:1 video signals (pin NR422 `0'). 4:2:2 applications supported special noise reduction mode (pin NR422 `1'). this mode filtering applied only luminance signal, chrominance signals delayed internal delay line remain unfiltered. storage planes chrominance signal 9251-2X requested additionally.
Semiconductor Group
1998-01-16
9254-2
CLASS
SDC4.11
NR422 SQA4.11 9254-2 SDC0.3 DLO0.3 DLI0.3 SQA0.3
SDC0.3
9251-2X
SQA0.3
UEB10380
Figure Noise Reduction with 4:2:2 Signals
Adaptive Field Based Noise Reduction reduction noise performed recursive filtering. filter following transfer function:
fielddelay
transfer function H(z) that means filtering performed input data remains unchanged. noise reduction filtering activated. input data delayed data from memory combined according H(z).
Semiconductor Group
1998-01-16
9254-2
SDC0 Video Input
Input Luminance
DEMUX Input Chrominance
CLASS
Motion Detector
Recursive Filter
Memory Port
delayed Luminance
DEMUX
delayed Chrominance Clock Control
Memory Port
UEB10381
Figure Block Diagram Noise Reduction Filtering avoid artefacts moving parts picture motion detector implemented control filter coefficient according detected changes between adjacent fields. motion detector performs pass filtering field differences builds absolute values. results control filter coefficient choosing predefined values between characteristic this assignment influences amount noise reduction adjustable CLASS-pins. calculation filter coefficient practised each pixel field. Adjustment Characteristic Noise Reduction Filter CLASS2 CLASS1 CLASS0 Amount Noise Reduction Low-mid Mid-high High Noise reduction
These four possible adjustments wide field different intensities noise reduction user's disposal. recursive filter also enables reduction cross color interference because Motion Detector exploits only luminance data. Semiconductor Group 1998-01-16
9254-2
following diagram shows requested data format 4:1:1 signals input SDC0 SDC11. output data format pins SQA0 SQA11 corresponds input format.
13.5 U1,7 U1,6 V1,7 V1,6 U1,5 U1,4 V1,5 V1,4 U1,3 U1,2
V1,3
U1,1 U1,0 V1,1 V1,0
U2,7 U2,6 V2,7 V2,6
U2,5 U2,4 V2,5 V2,4
UED08600
V1,2
Figure Input Data Format (4:1:1) Memory memory capacity 2605056 bit. organized rows columns arrays allows storage active part complete 4:1:1-TV field using 13.5 sample rate. memory fabricated using same CMOS technology used 4-Mbit standard dynamic random access memories. extremely high maximum data rate achieved three internal shift registers, each 16-bit length 12-bit width, which perform serial parallel conversion between asynchronous input/output data streams memory array. parallel data transfer from 12-bit input shift register addressed location memory array from memory array 12-bit output shift registers controlled serial row-(SAR) column address (SAC) which contains desired column address instruction code (mode bits) transfer refresh.
Semiconductor Group
1998-01-16
9254-2
Circuit Description Memory Architecture shown block diagram memory part (see figure TV-SAM comprises memory arrays, which accessed parallel. Each memory array size rows columns. rows columns arrays randomly addressed, reading writing bits time. obtain extremely high data rate 12-bit wide data input (port outputs (port parallel serial conversion done using shift registers 16-bit length 12-bit width. this memory speed increased factor (This independent number ports total data rate regarded.) Independent operation serial input serial outputs guaranteed using three shift registers. decoupling from common 12-bit memory data done three latches which allow flexible memory timing flying real-time data transfer. real-time data transfer necessary ensure continuous data flow data pins even maximum clock speed. save pins without loosing speed, TV-SAM addressed serially using serial 8-bit address serial 8-bit column address which includes mode control bits. serial column addresses converted parallel addresses internally, then latched column decoders. internal memory controller responsible timing memory read/write access refresh operation. Data Input (SDC, SCB) data pins connected input recursive filter. delay time from memory port caused filter amounts periods clock SCB. delay time considered generation signal (see diagram Data shifted into memory using serial port rising edge shift clock SCB. After clock pulses data have transferred from shift register latch more than clock pulses occur before latching data, only last sixteen 12-bit data values accepted. Data Input (DLI), Data Output (DLO, OEDLO) 4:2:2-mode bitplanes chrominance signals connected internal delay line pins DLI. After periods clock input data supplied delay line output DLO. output enable OEDLO output buffers switched into tristate. 4:1:1-mode pins should connected OEDLO should connected VDD. Data Transfer from Shift Register Latch (WT) contents shift register transferred latch falling edge write transfer signal timing restrictions between clock respected, continuous data flow input port possible without loosing data. This transfer operation asynchronous other transfer operations except small forbidden window conditioned latch memory transfer, diagram
Semiconductor Group
1998-01-16
9254-2
Write Transfer from Latch Memory (RE) data latch transferred preaddressed location memory array rising edge mode bits were (M1) (M0), "Addressing Mode Control." Addressing Mode Control (SAR, SAC, SCAD, serial 8-bit address 8-bit column address/mode code serially shifted into TV-SAM (LSB first) rising edge address clock SCAD. After SCAD cycles, falling edge internally latches SAC. column address itself needs only bits. last bits defined mode bits determine read/write refresh operation memory arrays triggered signal.
Mode
Mode
Operation Read transfer from memory latch Read transfer from memory latch Write transfer from latch memory Refresh with internal address
Read Transfer from Memory Latch (RE) Memory data from preaddressed location transferred latch falling edge depending mode control bits, "Addressing Mode Control". Data Transfer from Latch Shift Register (RA) data latch transferred shift register falling edge read transfer signal timing restrictions between shift clock taken into account, continuous data flow output without interrupts possible. This transfer operation independent other transfer operations except small forbidden time window conditioned memory latch transfer. Data Transfer from Latch Shift Register (RB) data latch transferred shift register falling edge read transfer signal timing restrictions between shift clock taken into account, continuous data flow memory output port without interrupts possible. This transfer operation independent other transfer operations except small forbidden time window conditioned memory latch transfer. correct operation recursive filtering memory output data port must phase with input data SDC. This restriction forces fixed space time between clock periods (see diagram
Semiconductor Group
1998-01-16
9254-2
Data Output (SQA, SCA, OEA) Data shifted through serial port (SQA0 SQA11) rising edge shift clock SCA. After clock cycles data have transferred from latch shift register Otherwise data values cyclically repeated. output enable output buffers switched into tristate. shift clock completely independent shift clock port (SCB). Memory Output (Port SCB) Data shifted through serial port rising edge shift clock SCB. After clock cycles data have transferred from latch shift register Otherwise data values cyclically repeated. shift clock also used input port Refresh Either refresh cycles (refresh with external address) read/write cycles consecutive addresses beginning with address have executed within interval maintain data memory arrays. refresh with internal adress determined mode control bits, "Addressing Mode Control". this refresh mode, column addresses ignored (see diagram 6b). Initialization device incorporates on-chip substrate bias generator well dynamic circuitry. Therefore initial pause required after power followed eight RE-cycles before proper device operation achieved. Typical Memory Cycle Sequence typical application TV-SAM real-time noise reduction filtering combined with flicker reduction. This achieved, example, writing reading with 13.5-MHz clock rate port simultaneously reading port with 27-MHz double speed clock. main cycle consecutive cycles transfer needed: 1st. 2nd. 3rd. 4th. RE-cycle: RE-cycle: RE-cycle: RE-cycle: Read transfer from memory latch Read transfer from memory latch Same 1st. cycle Write transfer from latch memory
Each transfer cycle preceeded address cycle shown diagram page clock rates mentioned this means serial cycle time port port addressing cycle time each port given times serial data rate. Thus have addressing cycle time approx. 1184 port port address port must loaded every Since addresses shifted sequentially, cycle time approx. necessary.
Semiconductor Group
1998-01-16
9254-2
beginning block serial data port determined respectively. serial input data block port controlled Since independently chosen (except small forbidden time windows when memory transfers executed), serial data streams shifted against each other without influencing cycles. activated noise reduction timing restrictions must considered (see Data Transfer from latch Shift Register
Semiconductor Group
1998-01-16
Addressing Serial Clock Cycles 16x37 Addressing Serial Clock Cycles 16x74 Addressing Write Transfer Serial Clock Cycles Addressing Write Transfer Read Transfer Serial Clock Cycles Read Transfer
Addressing
Semiconductor Group
Serial Port Serial Port Serial Port
Figure Typical Memory Cycle Sequence
Cycle
UED02042
Read Transfer
Addressing
Read Transfer
9254-2
Functionally coherent blocks emphasized vertical arrows indicate moment data transfer from latch shift register, vice versa
1998-01-16
9254-2
Configuration (top view)
P-MQFP-64-1
SDC3 SDC2 SDC1 SDC0 NR422 DLI0 DLI1 DLI2 DLI3 SQA0 SQA1
SDC4 SDC5 SCAD CLASS2 SDC6 SDC7
9254-2
SDC8 SDC9 SDC10 SDC11 CLASS0 CLASS1 DLO0 DLO1 DLO2 DLO3 SQA11 SQA10
SQA2 SQA3 SQA4 SQA5 OEDL0 SQA6 SQA7 SQA8 SQA9
UEP10382
Figure
Semiconductor Group
1998-01-16
9254-2
Definitions Functions Symbol SQA11 SQA8 SQA7 SQA6 SQA5 SQA4 SQA3 SQA0 OEDLO SDC11 SDC8 SDC7 SDC6 SDC5 SDC4 SDC3 SDC2 SDC1 SDC0 SCAD CLASS0 CLASS1 Input Output Function
Serial data output port (luminance signal)
Serial data output port (chrominance signal)
Serial clock input port Read transfer control input (latch shift register Output enable input port Serial clock input port Read transfer control input (latch shift register Output enable input delay line output
Serial data input port (luminance signal)
Serial data input port (chrominance signal)
Write transfer control input (shift register latch Serial address input Serial column address mode control input Serial address clock input RAM-enable input (also latches addresses) Characteristic noise reduction filter
Semiconductor Group
1998-01-16
9254-2
Definitions Functions (cont'd) Symbol CLASS2 DLO3 DLO2 DLO1 DLO0 DLI3 DLI2 DLI1 DLI0 NR422 Input Output Function (medium strong)
Delay line output (for 4:2:2-mode)
Delay line input (for 4:2:2-mode)
Noise reduction 4:2:2 Horizontal blanking input Data output power supply Data output power supply (GND) Memory power supply must connected VDD2 Memory power supply (GND), must connected VSS2
VDD2 VSS2 VDD1 VSS1
Semiconductor Group
1998-01-16
9254-2
Port Port Shift Register Latch Shift Register Latch Memory Cell Arrays Shift Register Latch SQA11 SQA0
Latches Column Address Decoder Internal Memory Controller
SCAD
UEB08602
Figure Block Diagram Memory
Semiconductor Group
1998-01-16
9254-2
Absolute Maximum Ratings Parameter Storage temperature Soldering temperature Soldering time Input/output voltage Power supply voltage Data current (short circuit) Total power dissipation Power dissipation output Operating Range Parameter Supply voltage Supply voltage Supply voltage Supply voltage H-input voltage (except CLASS2) L-input voltage (except CLASS2) H-input voltage (CLASS2) L-input voltage (CLASS2) Ambient temperature Symbol min. Limit Values typ. max. Unit Symbol Limit Values min. max. Unit Remarks
Tstg Tsold tsold VI/Q Ptot
VDD1 VDD2 VSS1 VSS2 VIHC VILC
Semiconductor Group
1998-01-16
9254-2
Characteristics Parameter H-output voltage L-output voltage Input leakage current Output leakage current Average supply current Symbol min. Limit Values typ. max. Unit Test Condition
ICCa
IOUT IOUT
OEDLO (tSC port min) (tSC port min) (tSC port min) (tRC min) ICCa depends cycle rate output loading. Specified values measured with open output. OEDLO VDD1) (SCA, SCB, SCAD) max. (tSC)
Standby supply current
ICCb
Semiconductor Group
1998-01-16
9254-2
Characteristics Parameter Memory read write cycle time Symbol min. Limit Values typ. max. 100000 Operation with tRCmin ensures that 8-bit serial data shifted within cycle taking tSCmin. diagram diagram diagram diagram diagram diagram diagram diagram Unit Test Condition
time Serial port cycle time precharge time Address setup time Address hold time SCAD set-up time SCAD hold time delay time
tROS tROH tRRD
100000 100000
tRRD tRRL restrictive operating parameters only memory read transfer cycles. diagram
delay time. diagram diagram
lead time set-up time pulse width hold time
tRRL
tRSS
tRPW tRSH
diagram diagram
Semiconductor Group
1998-01-16
9254-2
Characteristics (cont'd) Parameter lead time Symbol min. Limit Values typ. max. Unit Test Condition
tWRL
tWRL tRWL restrictive
operating parameters only memory write transfer cycles. that case tWRL applies write transfer from shifter latch occurs before rising edge Otherwise tRWL satisfied. diagram
lead time Output buffer turnoff delay
tRWL tOFF
lead time
tOFF (max) defines time which output achieves open-circuit condition referenced output voltages levels.
diagram diagram diagram diagram diagram diagram diagram diagram diagram
delay time lead time pulse width output access time Access time from Access time from Data input set-up time
tWTD tWTL tWTP tOAA tCAA tCBA
Data input hold time OEDLO output access time
tODA
Semiconductor Group
1998-01-16
9254-2
Characteristics (cont'd) Parameter Refresh period Symbol min. Limit Values typ. max. Either refresh cycles read/write cycles consecutive addresses have performed within interval maintain data Transition times measured between VIL. diagram diagram diagram diagram diagram Unit Test Condition
tREF
Transition time (rise/fall)
L-serial clock time H-serial clock time
tSCL tSCH
Hold time from tCAH Hold time from tCBH Input capacitance (SCA, SCB) Input capacitance (all other pins) Output capacitance (SQA 0-11,
Semiconductor Group
1998-01-16
9254-2
Operation Truth Table
Cycle SCAD Mode RA0.RA RA0.RA RA0.RA CA0.CA CA0.CA CA0.CA Read transfer from memory shifter Read transfer from memory shifter Write transfer from shifter memory Refresh with internal address Serial read port Data output Serial read port OEDLO Cycle Operation
Note: Don't care
address, column address mode bits have defined cycle order become effective cycle
Semiconductor Group
1998-01-16
9254-2
Input conditions
HIGH
Output conditions Output loading:
UED10454
1.31
Diagram AC-Timing Measuring Conditions
Semiconductor Group
1998-01-16
9254-2
SCAD
SQA(0-11)
UET07391
Diagram Read Transfer Memory Port Semiconductor Group 1998-01-16
9254-2
SCAD
Port
UET08603
Diagram Read Transfer Memory Port Semiconductor Group 1998-01-16
9254-2
SCAD
Port
UET08604
Diagram Write Transfer from Port Memory
Semiconductor Group
1998-01-16
9254-2
Serial Read Operation Port
SQA(0-11)
Valid Data
Valid Data
Valid Data
Serial Read Operation Port
Port Serial Write Operation Port
Valid Data
Valid Data
Valid Data
Port
Valid Data
Valid Data
Valid Data
UET08605
Diagram Serial Read Write Operations
Semiconductor Group
1998-01-16
9254-2
SCAD
UED08620
Diagram Refresh with Internal Address
Semiconductor Group
1998-01-16
9254-2
SCAD
UED08617
Mode bits arbitrary, except combination
Mode bits should toggle successive cycles Diagram Refresh with External Address
Semiconductor Group
1998-01-16
9254-2
OEDLO
UET08618
Diagram Timing BLN,
Semiconductor Group
1998-01-16
9254-2
Port
Port
Delay recursive filter
RBWT
UET08619
Diagram Timing Restrictions
Semiconductor Group
1998-01-16
9254-2
Application Circuit best performance operation within specified parameter limits mandatory separate decoupling capacitors VSS1/VDD1 VSS2/VDD2 with VSS1 shorted VSS2 VDD1 shorted VDD2 board shown figure below. Decoupling capacitors inductance multilayer type least should used. avoid malfunction even permanent damage device strongly recommended other supply configuration.
9254-2
UES10383
Figure
Semiconductor Group
1998-01-16
9254-2
Application Information Digital Storage Field standard digital systems, CCIR recommendation defines field lines with pixels line. sampling frequency 13.5 with resolution pixel. Information stored different channels: channel luminance (Y), channels chrominance bandwidth ratio between different channels either Y:U:V 4:1:1 4:2:2 depending coding method. width 4:1:1 format bit, 4:2:2 format requires 9251-2X memory device additionally. 9254-2 designed cost large area flicker- noise reduction systems. following block diagram shows typical application 4:1:1 signals.
CVBS Triple 9206 SYNC 9254-2
Display Processor 9280
YOUT UOUT VOUT
Address SYNC Deflection
UEB08607
9220-5
Figure Cost Flicker- Noise Reduction System with 9254-2
Semiconductor Group
1998-01-16
9254-2
Package Outlines P-MQFP-64-1 (Plastic Metric Quad Flat Package)
Sorts Packing Package outlines tubes, trays etc. contained Data Book "Package Information". Surface Mounted Device Semiconductor Group
Dimensions 1998-01-16
GPM05250

Preliminary Data Features 9254-2 CMOS Stores complete v

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