9253 Preliminary Data Features CMOS 12-bit organization

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

9253 Preliminary Data Features CMOS 12-bit organization

Datasheet Thumbnail

Top Searches for this datasheet

MBit Dynamic Sequential Access Memory Television Applications (TV-SAM)
9253
Preliminary Data Features
CMOS
12-bit organization Triple port architecture 12-bit input shift register 12-bit output shift registers Shift registers independently simultaneously accessible Continuous data flow even maximum speed 40-MHz shift rate 0.96-Gbit/s total data rate inputs outputs TTL-compatible Tristate outputs Random access groups bits wide range applications Refresh-free operation possible power supply operating temperature range power dissipation: active, standby Suitable common standards Allows flicker noise reduction simultaneously with only field memory Applications: VCR, image processing, video printers, data compressors, delay lines, time base correctors, HDTV
P-MQFP-64-1
Type 9253
Ordering Code Q67101-H5171
Package P-MQFP-64-1
Semiconductor Group
1998-01-30
9253
Functional Description 9253 triple port 2605056 dynamic sequential-access memory high-data-rate video applications. organized rows columns arrays allow storage 12-bit planes field (NTSC, PAL, SECAM, MAC) standard studio quality (13.5-MHz basic sample rate) 12-bit planes parts HDTV field. memory fabricated using same CMOS technology used 4-Mbit standard dynamic random access memories. extremely high maximum data rate achieved three internal shift registers, each 16-bit length 12-bit width, which perform serial parallel conversion between asynchronous input/output data streams memory array. parallel data transfer from 12-bit input shift register addressed location memory array from memory array 12-bit output shift registers controlled serial row-(SAR) column address (SAC) which contains desired column address instruction code (mode bits) transfer refresh. Circuit Description Memory Architecture shown block diagram, TV-SAM comprises memory arrays, which accessed parallel. Each memory array size rows columns. rows columns arrays randomly addressed, reading writing bits time. obtain extremely high data rate 12-bit wide data input (SDC) outputs (SQA, SQB), parallel serial conversion done using shift registers 16-bit length 12-bit width. this memory speed increased factor (This independent number ports total data rate regarded.) Independent operation serial input serial outputs guaranteed using three shift registers. decoupling from common 12-bit memory data done three latches which allow flexible memory timing flying real-time data transfer. real-time data transfer necessary ensure continuous data flow data pins even maximum clock speed. save pins without loosing speed, TV-SAM addressed serially using serial 8-bit address serial 8-bit column address which includes mode control bits. serial column addresses converted parallel addresses internally, then latched column decoders. internal memory controller responsible timing memory read/write access refresh operation.
Semiconductor Group
1998-01-30
9253
Data Input (SDC, SCB) Data shifted through serial port (SDC0, SDC11) rising edge shift clock SCB. After clock pulses data have transferred from shift register latch more than clock pulses occur before latching data, only last sixteen 12-bit data values accepted. Data Transfer from Shift Register Latch (WT) contents shift register transferred latch falling edge write transfer signal timing restrictions between clock respected, continuous data flow input possible without loosing data. This transfer operation asynchronous other transfer operations except small forbidden window conditioned latch memory transfer, diagram Write Transfer from Latch Memory (RE) data latch transferred preaddressed location memory array rising edge mode bits were (M1) (M0), "Addressing Mode Control." Addressing Mode Control (SAR, SAC, SCAD, serial 8-bit address 8-bit column address/mode code serially shifted into TV-SAM (LSB first) rising edge address clock SCAD. After SCAD cycles, falling edge internally latches SAC. column address itself needs only bits. last bits defined mode bits determine read/write refresh operation memory arrays triggered signal.
Mode
Mode
Operation Read transfer from memory latch Read transfer from memory latch Write transfer from latch memory Refresh with internal address
Read Transfer from Memory Latch (RE) Memory data from preaddressed location transferred latch falling edge depending mode control bits, "Addressing Mode Control". Data Transfer from Latch Shift Register (RA) contents latch transferred shift register falling edge read transfer signal timing restrictions between shift clock taken into account, continuous data flow output without interrupts possible. This transfer operation independent other transfer operations except small forbidden time window conditioned memory latch transfer.
Semiconductor Group
1998-01-30
9253
Data Transfer from Latch Shift Register (RB) contents latch transferred shift register falling edge read transfer signal timing restrictions between shift clock taken into account, continuous data flow output without interrupts possible. This transfer operation independent other transfer operations except small forbidden time window conditioned memory latch transfer. Data Output (SQA, SCA, OEA) Data shifted through serial port (SQA0 SQA11) rising edge shift clock SCA. After clock cycles data have transferred from latch shift register Otherwise data values cyclically repeated. output enable output buffers switched into tristate. shift clock completely independent shift clock port (SCB). Data Output (SQB, SCB, OEB) Data shifted through serial port (SQB0 SQB11) rising edge shift clock SCB. After clock cycles data have transferred from latch shift register Otherwise data values cyclically repeated. shift clock also used input port output enable output buffers switched into tristate. Refresh Either refresh cycles read/write cycles consecutive addresses beginning with address have executed within interval maintain data memory arrays. refresh cycle determined mode control bits, "Addressing Mode Control". refresh mode, column addresses ignored. Initialization device incorporates on-chip substrate bias generator well dynamic circuitry. Therefore initial pause required after power followed eight RE-cycles before proper device operation achieved.
Semiconductor Group
1998-01-30
9253
Typical Memory Cycle Sequence typical application TV-SAM real-time interfield image processing combined with flicker reduction. This achieved, example, writing reading with 13.5-MHz clock rate port simultaneously reading port with 27-MHz double speed clock. main cycle consecutive cycles transfer needed:
1st. 2nd. 3rd. 4th.
RE-cycle: RE-cycle: RE-cycle: RE-cycle:
Read transfer from memory latch Read transfer from memory latch Same 1st. cycle Write transfer from latch memory
Each transfer cycle preceeded address cycle shown diagram page clock rates mentioned this means serial cycle time port port addressing cycle time each port given times serial data rate. Thus have addressing cycle time approx. 1184 port port address port must loaded every Since addresses shifted sequentially, cycle time approx. necessary. beginning block serial data port determined respectively. serial input data block port controlled Since independently chosen (except small forbidden time windows when memory transfers executed), serial data streams shifted against each other without influencing cycles.
Semiconductor Group
1998-01-30
Addressing Serial Clock Cycles 16x37 Addressing Serial Clock Cycles 16x74 Addressing Write Transfer Serial Clock Cycles Addressing Write Transfer Read Transfer Serial Clock Cycles Read Transfer
Addressing
Semiconductor Group
Serial Port Serial Port Serial Port
Figure Typical Memory Cycle Sequence
Cycle
UED02042
Read Transfer
Addressing
Read Transfer
Functionally coherent blocks emphasized vertical arrows indicate moment data transfer from latch shift register, vice versa
9253
1998-01-30
9253
Configuration (top view)
SDC4 SDC5 SCAD VDD1 VSS1 SDC6 SDC7 SQA2 SQA3 VDD2 VSS2 SQA4 SQA5 VSS1 VDD1 SQA6 SQA7 VSS2 VDD2 SQA8 SQA9
SDC8 SDC9 SDC10 SDC11 SQB6 SQB7 VDD2 VSS2 SQB8 SQB9 SQB10 SQB11 VDD2 VSS2 SQA11 SQA10
SDC3 SDC2 SDC1 SDC0 SQB0 SQB1 VDD2 VSS2 SQB2 SQB3 SQA4 SQA5 VDD2 VSS2 SQA0 SQA1
9253
UEP07388
Figure
Semiconductor Group
1998-01-30
9253
Definitions Functions Symbol SQA0 SQA11 SQB0 SQB11 SDC0 SDC11 SCAD Input Output Function
Serial data output port
Serial clock input port Read transfer control input (latch shift register Output enable input port
Serial data output port
Serial clock input port Read transfer control input (latch shift register Output enable input port
Serial data input port
Write transfer control input (shift register latch Serial address input Serial column address mode control input Serial address clock input RAM-enable input (also latches addresses) Data output power supply Data output power supply (GND) Memory power supply must connected VDD2 Memory power supply (GND), must connected VSS2 Test function (for factory only)
VDD2 VSS2 VDD1 VSS1
Semiconductor Group
1998-01-30
9253
VDD1
VDD2
VSS1
VSS2
Shift Register Latch Shift Register Latch Memory Cell Arrays Shift Register Latch SQA11 SQA0
Latches Column Address Decoder Internal Memory Controller
SCAD
UEB07389
Figure Block Diagram
Semiconductor Group
1998-01-30
9253
Absolute Maximum Ratings Parameter Storage temperature Soldering temperature Soldering time Input/output voltage Test function input voltage Power supply voltage Data current (short circuit) Total power dissipation Power dissipation output Operating Range Parameter Supply voltage Supply voltage Supply voltage Supply voltage H-input voltage L-input voltage Ambient temperature Symbol min. Limit Values typ. max. Unit Symbol Limit Values min. max. factory only Unit Remarks
Tstg Tsold tsold VI/Q Ptot
VDD1 VDD2 VSS1 VSS2
Semiconductor Group
1998-01-30
9253
Characteristics Parameter Test enable input high voltage Symbol min. Limit Values typ. max. normal operation connected VDD1 level left unconnected. test enable input high voltage Unit Test Condition
Test disable input voltage H-output voltage L-output voltage Input leakage current
VDD1
IOUT IOUT
(tSC port min) (tSC port min) (tSC port min) (tRC min) ICCa depends cycle rate output loading. Specified values measured with open output. VDD1) (SCA, SCB, SCAD) max. (tSC)
Output leakage current Average supply current ICCa
Standby supply current ICCb
Semiconductor Group
1998-01-30
9253
Characteristics Parameter Memory read write cycle time Symbol min. Limit Values typ. max. 100000 Operation with tRCmin ensures that 8-bit serial data shifted within cycle taking tSCmin. diagram diagram diagram diagram diagram diagram diagram diagram Unit Test Condition
time Serial port cycle time precharge time Address setup time Address hold time SCAD set-up time SCAD hold time delay time
tROS tROH tRRD
100000 100000
tRRD tRRL restrictive operating parameters only memory read transfer cycles. diagram
delay time. diagram diagram
lead time set-up time pulse width hold time
tRRL
tRSS
tRPW tRSH
diagram diagram
Semiconductor Group
1998-01-30
9253
Characteristics (cont'd) Parameter lead time Symbol min. Limit Values typ. max. Unit Test Condition
tWRL
tWRL tRWL restrictive
operating parameters only memory write transfer cycles. that case tWRL applies write transfer from shifter latch occurs before rising edge Otherwise tRWL satisfied. diagram
lead time Output buffer turnoff delay
tRWL tOFF
lead time
tOFF (max) defines time which output achieves open-circuit condition referenced output voltages levels.
diagram diagram diagram diagram diagram diagram diagram diagram diagram
delay time lead time pulse width output access time output access time Access time from Access time from Data input set-up time
tWTD tWTL tWTP tOAA tOBA tCAA tCBA
Data input hold time
Semiconductor Group
1998-01-30
9253
Characteristics (cont'd) Parameter Refresh period Symbol min. Limit Values typ. max. Either refresh cycles read/write cycles consecutive addresses have performed within interval maintain data Transition times measured between VIL. diagram diagram diagram diagram diagram Unit Test Condition
tREF
Transition time (rise/fall)
L-serial clock time H-serial clock time
tSCL tSCH
Hold time from tCAH Hold time from tCBH Input capacitance (SCA, SCB) Input capacitance (all other pins) Output capacitance (SQA 0-11, 0-11)
Semiconductor Group
1998-01-30
9253
Operation Truth Table
Cycle SCAD Mode RA0.RA RA0.RA RA0.RA CA0.CA CA0.CA CA0.CA Read transfer from memory shifter Read transfer from memory shifter Write transfer from shifter memory Refresh with internal address Serial read port Serial read port Serial read port Cycle Operation
Note: Don't care address, column address mode bits have V(TF)= VDD1 (TF) connected defined cycle order become effective cycle
Semiconductor Group
1998-01-30
9253
Input conditions
HIGH
Output conditions Output loading:
UED10454
1.31
Diagram AC-Timing Measuring Conditions
Semiconductor Group
1998-01-30
9253
SCAD
SQA(0-11)
UET07391
Diagram Read Transfer Memory Port
Semiconductor Group
1998-01-30
9253
SCAD
SQA(0
UET07392
Diagram Read Transfer Memory Port
Semiconductor Group
1998-01-30
9253
SCAD
SDC(0
UET07393
Diagram Write Transfer from Port Memory
Semiconductor Group
1998-01-30
9253
Serial Read Operation Port
SQA(0 Serial Read Operation Port Valid Data Valid Data Valid Data
SQB(0 Serial Write Operation Port Valid Data Valid Data Valid Data
SDC(0
Valid Data
Valid Data
Valid Data
UET07394
Diagram
Semiconductor Group
1998-01-30
9253
SCAD
UED02050
Diagram Refresh with External Address
Semiconductor Group
1998-01-30
9253
Application Circuit best performance operation within specified parameter limits mandatory separate decoupling capacitors VSS1/VDD1 VSS2/VDD2 with VSS1 shorted VSS2 VDD1 shorted VDD2 board shown figure below. Decoupling capacitors inductance multilayer type least should used. avoid malfunction even permanent damage device strongly recommended other supply configuration.
9253
UES07395
Figure
Semiconductor Group
1998-01-30
9253
Application Information Digital Storage Field standard digital systems, CCIR recommendation defines field lines with pixels line. sampling frequency 13.5 with resolution pixel. Information stored different channels: channel luminance (Y), channels chrominance bandwidth ratio between different channels either Y:U:V 4:1:1, 4:2:2 4:4:4 depending coding method. following table shows memory requirements field buffer number memory chips when 9253 9251 used.
Table Memory Requirements Number Memory Chips Digital TV-Field Buffer Y:U:V 4:1:1 4:2:2 4:4:4 Clock Rate 13.5 2.37 Mbit 3.16 4.75 Number Required Memory Devices 9253 9253 9251 9253 Width
typical application 9253 field memory device Siemens MEGAVISION system. memory capacity 9253 times that 9251 therefore able substitute 9251. 4:1:1 sampling format there need device application without Line Flicker Reduction devices application with Line Flicker Reduction (see figure).
Semiconductor Group
1998-01-30
9253
SDA9251X
3ADC 9206 9251X 9290 9253 9270 9280 Picture Processor 9253 Field Mixer Display Processor
YOUT
VOUT
SYNC
SYNC
MSC3 9220
SYNC
UEB07396
Figure MEGAVISION Block Diagram Line Flicker Reduction
Semiconductor Group
1998-01-30
9253
Package Outlines P-MQFP-64-1 (Plastic Metric Quad Flat Package)
Sorts Packing Package outlines tubes, trays etc. contained Data Book "Package Information". Surface Mounted Device Semiconductor Group
Dimensions 1998-01-30
GPM05250

9253 Preliminary Data Features CMOS 12-bit organization

Top Searches for this datasheet

Other recent searches