SYNCBURSTSRAM Fast clock access times Single +3.3V +0.3V/-0.165V
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4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
SYNCBURSTSRAM
Fast clock access times Single +3.3V +0.3V/-0.165V power supply (VDD) Separate +3.3V +2.5V isolated output buffer supply (VDDQ) SNOOZE MODE reduced-power standby Single-cycle deselect (Pentium® BSRAM-compatible) Common data inputs data outputs Individual BYTE WRITE control GLOBAL WRITE Three chip enables simple depth expansion address pipelining Clock-controlled registered addresses, data I/Os control signals Internally self-timed WRITE cycle Burst control (interleaved linear burst) Automatic power-down portable applications 100-lead TQFP package high density, high speed 119-bump package capacitive loading x18, versions available
MT58L256L18P, MT58L128L32P, MT58L128L36P; MT58L256V18P, MT58L128V32P, MT58L128V36P
3.3V VDD, 3.3V 2.5V I/O, Pipelined, Single-Cycle Deselect
100-Pin TQFP*
119-Bump
OPTIONS
Timing (Access/Cycle/MHz) 3.1ns/5ns/200 3.5ns/6ns/166 4.0ns/7.5ns/133 5ns/10ns/100 Configurations 3.3V 256K 128K 128K 2.5V 256K 128K 128K Packages 100-pin TQFP 119-bump, 14mm 22mm Operating Temperature Range Commercial (0°C +70°C) Industrial (-40°C +85°C)
MARKING
-7.5
MT58L256L18P MT58L128L32P MT58L128L36P MT58L256V18P MT58L128V32P MT58L128V36P None
*JEDEC-standard MS-026 (LQFP).
GENERAL DESCRIPTION
Micron® SyncBurstSRAM family employs highspeed, low-power CMOS designs that fabricated using advanced CMOS process. Micron's SyncBurst SRAMs integrate 256K 128K 128K SRAM core with advanced synchronous peripheral circuitry 2-bit burst counter. synchronous inputs pass through registers controlled positive-edge-triggered single clock input (CLK). synchronous inputs include addresses, data inputs, active chip enable (CE#), additional chip enables easy depth expansion (CE2, CE2#), burst control inputs
Part Number Example: MT58L256L18PT-6
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc. registered unregistered trademarks sole property their respective companies.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM 256K
SA0, SA1, MODE ADV# ADDRESS REGISTER
SA0, SA1'
BINARY COUNTER LOGIC
SA0'
ADSC# ADSP# BYTE WRITE REGISTER BYTE WRITE DRIVER 256K MEMORY ARRAY SENSE AMPS
BWb#
OUTPUT REGISTERS
OUTPUT BUFFERS
BWa# BWE# CE2#
BYTE WRITE REGISTER
BYTE WRITE DRIVER
DQPa DQPb
ENABLE REGISTER
PIPELINED ENABLE
INPUT REGISTERS
FUNCTIONAL BLOCK DIAGRAM 128K 32/36
SA0, SA1,
ADDRESS REGISTER
SA0,
MODE ADV# BINARY COUNTER SA0'
SA1'
ADSC# ADSP#
BWd#
BYTE WRITE REGISTER
BYTE WRITE DRIVER BYTE WRITE DRIVER BYTE WRITE DRIVER BYTE WRITE DRIVER INPUT REGISTERS
128K (x32) 128K (x36) MEMORY ARRAY SENSE AMPS
BWc#
BYTE WRITE REGISTER
OUTPUT REGISTERS
BWb#
BYTE WRITE REGISTER
OUTPUT BUFFERS
DQPa
DQPd
BWa#
BWE# CE2#
BYTE WRITE REGISTER
ENABLE REGISTER
PIPELINED ENABLE
NOTE:
Functional Block Diagrams illustrate simplified device operation. Truth Table, Descriptions timing diagrams detailed information.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
(ADSC#, ADSP#, ADV#), byte write enables (BWx#) global write (GW#). Asynchronous inputs include output enable (OE#), clock (CLK) snooze enable (ZZ). There also burst mode input (MODE) that selects between interleaved linear burst modes. data-out (Q), enabled OE#, also asynchronous. WRITE cycles from bytes wide (x18) from four bytes wide (x32/x36), controlled write control inputs. Burst operation initiated with either address status processor (ADSP#) address status controller (ADSC#) inputs. Subsequent burst addresses internally generated controlled burst advance input (ADV#). Address write control registered on-chip simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes written. During WRITE cycles device, BWa# controls DQa's DQPa; BWb# controls DQb's DQPb. During WRITE cycles devices, BWa# controls DQa's DQPa; BWb# controls DQb's DQPb; BWc# controls DQc's DQPc; BWd# controls DQd's DQPd. causes bytes written. Parity bits only available versions. This device incorporates single-cycle deselect feature during READ cycles. device immediately deselected after READ cycle, output goes High-Z state tKQHZ nanoseconds after rising edge clock. Micron's SyncBurst SRAMs operate from +3.3V power supply, inputs outputs TTLcompatible. Users choose either 3.3V 2.5V version. device ideally suited Pentium PowerPC pipelined systems systems that benefit from very wide, high-speed data bus. device also ideal generic 16-, 18-, 32-, 36-, 72-bit-wide applications. Please refer Micron site (www.micron.com/ mti/msp/html/sramprod.html) latest data sheet.
TQFP ASSIGNMENT TABLE
x32/x36 NC/DQPc* VDDQ VDDQ VDDQ x32/x36 VDDQ NC/DQPd* MODE x32/x36 NC/DQPa* VDDQ VDDQ VDDQ x32/x36 VDDQ NC/DQPb* ADV# ADSP# ADSC# BWE# CE2# BWa# BWb# BWc# BWd#
DQPb
DQPa
Connect (NC) used version. Parity (DQPx) used version.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
ASSIGNMENT (Top View) 100-Pin TQFP (D-1)
VDDQ DQPa VDDQ VDDQ VDDQ ADV# ADSP# ADSC# BWE# CE2# BWa# BWb#
MODE
ADV# ADSP# ADSC# BWE# CE2# BWa# BWb# BWc# BWd#
NC/DQPb* VDDQ VDDQ VDDQ VDDQ NC/DQPa*
VDDQ VDDQ VDDQ DQPb VDDQ
x32/x36
MODE
Connect (NC) used version. Parity (DQPx) used version.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
NC/DQPc* VDDQ VDDQ VDDQ VDDQ NC/DQPd*
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
TQFP DESCRIPTIONS
x32/x36 SYMBOL TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs registered must meet setup hold times around rising edge CLK. 32-35, 44-50, 32-35, 44-50, 80-82,
BWa# BWb# BWc# BWd#
Input
Synchronous Byte Write Enables: These active inputs allow individual bytes written must meet setup hold times around rising edge CLK. byte write enable WRITE cycle HIGH READ cycle. version, BWa# controls pins DQPa; BWb# controls pins DQPb. versions, BWa# controls pins DQPa; BWb# controls pins DQPb; BWc# controls pins DQPc; BWd# controls pins DQPd. Parity only available versions. Byte Write Enable: This active input permits BYTE WRITE operations must meet setup hold times around rising edge CLK. Global Write: This active input allows full 18-, 36-bit WRITE occur independent BWE# BWx# lines must meet setup hold times around rising edge CLK. Clock: This signal registers address, data, chip enable, byte write enables burst control inputs rising edge. synchronous inputs must meet setup hold times around clock's rising edge. Synchronous Chip Enable: This active input used enable device conditions internal ADSP#. sampled only when external address loaded. Synchronous Chip Enable: This active input used enable device sampled only when external address loaded. Synchronous Chip Enable: This active HIGH input used enable device sampled only when external address loaded. Output Enable: This active LOW, asynchronous input enables data output drivers. Synchronous Address Advance: This active input used advance internal burst counter, controlling burst access after external address loaded. HIGH this effectively causes wait states generated address advance). ensure correct address during WRITE cycle, ADV# must HIGH rising edge first clock after ADSP# cycle initiated. Synchronous Address Status Processor: This active input interrupts ongoing burst, causing external address registered. READ performed using address, independent byte write enables ADSC#, dependent upon CE#, CE2#. ADSP# ignored HIGH. Powerdown state entered CE2# HIGH.
BWE#
Input
Input
Input
Input
CE2#
Input
Input
ADV#
Input Input
ADSP#
Input
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
TQFP DESCRIPTIONS (continued)
x32/x36 SYMBOL ADSC# TYPE Input DESCRIPTION Synchronous Address Status Controller: This active input interrupts ongoing burst, causing external address registered. READ WRITE performed using address LOW. ADSC# also used place chip into power-down state when HIGH. Mode: This input selects burst sequence. this selects "linear burst." HIGH this selects "interleaved burst." alter input state while device operating. Snooze Enable: This active HIGH, asynchronous input causes device enter low-power standby mode which data memory array retained. When active, other inputs ignored.
MODE
Input
Input
56-59, 72-75, 6-9, 22-25,
Input/ SRAM Data I/Os: version, Byte pins; Byte Output pins. versions, Byte pins; Byte pins; Byte pins; Byte pins. Input data must meet setup hold times around rising edge CLK.
NC/DQPa NC/DQPb NC/DQPc NC/DQPd VDDQ Connect/Parity Data I/Os: version, these pins Connect (NC). version, Byte parity DQPa; Byte parity DQPb. version, Byte parity DQPa; Byte parity DQPb; Byte parity DQPc; Byte parity DQPd.
1-3, 28-30, 51-53,
Supply Power Supply: Electrical Characteristics Operating Conditions range. Supply Isolated Output Buffer Supply: Electrical Characteristics Operating Conditions range. Supply Ground: GND.
Use: These signals either unconnected wired improve package heat dissipation. Connect: These signals internally connected connected ground improve package heat dissipation.
Function: These pins internally connected have capacitance input pin. allowable leave these pins unconnected driven signals.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
BUMP LAYOUT (Top View) 119-Bump
x32/x36
VDDQ VDDQ VDDQ VDDQ VDDQ VIEW VDDQ MODE DQPb BWE# VDDQ BWa# VDDQ BWb# ADV# VDDQ DQPa ADSC# CE2# ADSP# VDDQ
VDDQ NC/DQPc* VDDQ VDDQ VDDQ NC/DQPd* VDDQ VIEW VDDQ MODE NC/DQPa* BWE# VDDQ BWd# BWa# VDDQ BWc# ADV# BWb# VDDQ NC/DQPb* ADSC# CE2# ADSP# VDDQ
Connect (NC) used version. Parity (DQPx) used version.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
BUMP DESCRIPTIONS
x32/x36 SYMBOL TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs registered must meet setup hold times around rising edge CLK.
BWa# BWb# BWc# BWd#
Input
Synchronous Byte Write Enables: These active inputs allow individual bytes written must meet setup hold times around rising edge CLK. byte write enable WRITE cycle HIGH READ cycle. version, BWa# controls DQa's DQPa; BWb# controls DQb's DQPb. versions, BWa# controls DQa's DQPa; BWb# controls DQb's DQPb; BWc# controls DQc's DQPc; BWd# controls DQd's DQPd. Parity only available versions. Byte Write Enable: This active input permits BYTE WRITE operations must meet setup hold times around rising edge CLK. Global Write: This active input allows full 18-, 36-bit WRITE occur independent BWE# BWx# lines must meet setup hold times around rising edge CLK. Clock: This signal registers address, data, chip enable, byte write enables burst control inputs rising edge. synchronous inputs must meet setup hold times around clock's rising edge. Synchronous Chip Enable: This active input used enable device conditions internal ADSP#. sampled only when external address loaded. Synchronous Chip Enable: This active input used enable device sampled only when external address loaded. Snooze Enable: This active HIGH, asynchronous input causes device enter low-power standby mode which data memory array retained. When active, other inputs ignored. Synchronous Chip Enable: This active HIGH input used enable device sampled only when external address loaded. Output Enable: This active LOW, asynchronous input enables data output drivers. Synchronous Address Advance: This active input used advance internal burst counter, controlling burst access after external address loaded. HIGH ADV# effectively causes wait states generated address advance). ensure correct address during WRITE cycle, ADV# must HIGH rising edge first clock after ADSP# cycle initiated.
BWE#
Input
Input
Input
Input
CE2#
Input
Input
Input
ADV#
Input Input
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
BUMP DESCRIPTIONS (continued)
x32/x36 SYMBOL ADSP# TYPE Input DESCRIPTION Synchronous Address Status Processor: This active input interrupts ongoing burst, causing external address registered. READ performed using address, independent byte write enables ADSC#, dependent upon CE#, CE2#. ADSP# ignored HIGH. Powerdown state entered CE2# HIGH. Synchronous Address Status Controller: This active input interrupts ongoing burst, causing external address registered. READ WRITE performed using address LOW. ADSC# also used place chip into power-down state when HIGH. Mode: This input selects burst sequence. this input selects "linear burst." HIGH this input selects "interleaved burst." alter input state while device operating.
ADSC#
Input
MODE
Input
Input/ SRAM Data I/Os: version, Byte DQa's; Byte Output DQb's. versions, Byte DQa's; Byte DQb's; Byte DQc's; Byte DQd's. Input data must meet setup hold times around rising edge CLK.
NC/DQPa NC/DQPb NC/DQPc NC/DQPd VDDQ
Connect/Parity Data I/Os: version, these Connect (NC). version, Byte parity DQPa; Byte parity DQPb. version, Byte parity DQPa; Byte parity DQPb; Byte parity DQPc; Byte parity DQPd.
Supply Power Supply: Electrical Characteristics Operating Conditions range. Supply Isolated Output Buffer Supply: Electrical Characteristics Operating Conditions range.
Supply Ground: GND.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
BUMP DESCRIPTIONS (continued)
x32/x36 SYMBOL TYPE DESCRIPTION Use: These signals either unconnected wired improve package heat dissipation. Connect: These signals internally connected connected ground improve package heat dissipation.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE HIGH)
FIRST ADDRESS (EXTERNAL) X.X00 X.X01 X.X10 X.X11 SECOND ADDRESS (INTERNAL) X.X01 X.X00 X.X11 X.X10 THIRD ADDRESS (INTERNAL) X.X10 X.X11 X.X00 X.X01 FOURTH ADDRESS (INTERNAL) X.X11 X.X10 X.X01 X.X00
LINEAR BURST ADDRESS TABLE (MODE LOW)
FIRST ADDRESS (EXTERNAL) X.X00 X.X01 X.X10 X.X11 SECOND ADDRESS (INTERNAL) X.X01 X.X10 X.X11 X.X00 THIRD ADDRESS (INTERNAL) X.X10 X.X11 X.X00 X.X01 FOURTH ADDRESS (INTERNAL) X.X11 X.X00 X.X01 X.X10
PARTIAL TRUTH TABLE WRITE COMMANDS (x18)
FUNCTION READ READ WRITE Byte WRITE Byte WRITE Bytes WRITE Bytes BWE# BWa# BWb#
PARTIAL TRUTH TABLE WRITE COMMANDS (x32/x36)
FUNCTION READ READ WRITE Byte WRITE Bytes WRITE Bytes NOTE: BWE# BWa# BWb# BWc# BWd#
Using BWE# BWa# through BWd#, more bytes written.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
TRUTH TABLE
ADDRESS CE2# USED Deselected Cycle, Power-Down None Deselected Cycle, Power-Down None Deselected Cycle, Power-Down None Deselected Cycle, Power-Down None Deselected Cycle, Power-Down None SNOOZE MODE, Power-Down None READ Cycle, Begin Burst External READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst NOTE: External External External External Next Next Next Next Next Next Current Current Current Current Current Current OPERATION ADSP# ADSC# ADV# WRITE# High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
means "Don't Care." means active LOW. means logic HIGH. means logic LOW. WRITE#, means more byte write enable signals (BWa#, BWb#, BWc# BWd#) BWE# LOW. WRITE# BWx#, BWE#, HIGH. BWa# enables WRITEs DQa's DQPa. BWb# enables WRITEs DQb's DQPb. BWc# enables WRITEs DQc's DQPc. BWd# enables WRITEs DQd's DQPd. DQPa DQPb only available versions. DQPc DQPd only available version. inputs except must meet setup hold times around rising edge (LOW HIGH) CLK. Wait states inserted suspending burst. WRITE operation following READ operation, must HIGH before input data setup time held HIGH throughout input data hold time. This device contains circuitry that will ensure outputs will High-Z during power-up. ADSP# always initiates internal READ edge CLK. WRITE performed setting more byte write enable signals BWE# subsequent edge CLK. Refer WRITE timing diagram clarification.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage Supply Relative -0.5V +4.6V Voltage VDDQ Supply Relative -0.5V +4.6V -0.5V VDDQ 0.5V Storage Temperature (plastic) -55°C +150°C Storage Temperature (BGA) -55°C +125°C Junction Temperature** +150°C Short Circuit Output Current 100mA *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature airflow. Micron Technical Note TN-05-14 more information.
3.3V ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
(0°C 70°C; VDD, VDDQ +3.3V +0.3V/-0.165V unless otherwise noted) DESCRIPTION Input High (Logic Voltage Input (Logic Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Supply Voltage Isolated Output Buffer Supply NOTE: CONDITIONS SYMBOL VDDQ -0.3 -1.0 -1.0 3.135 3.135 UNITS NOTES
Output(s) disabled, -4.0mA 8.0mA
voltages referenced (GND). Overshoot: +4.6V tKC/2 20mA Undershoot: -0.7V tKC/2 20mA Power-up: +3.6V 3.135V 200ms MODE internal pull-up, input leakage ±10µA. load used VOH, testing shown Figure 3.3V I/O. load current higher than shown values. curves available upon request. VDDQ should never exceed VDD. VDDQ connected together, 3.3V operation only.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
2.5V ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
(0°C 70°C; +3.3V +0.3V/-0.165V; VDDQ +2.5V +0.4V/-0.125V unless otherwise noted) DESCRIPTION Input High (Logic Voltage Input (Logic Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Supply Voltage Isolated Output Buffer Supply Output(s) disabled, VDDQ (DQx) -2.0mA -1.0mA 2.0mA 1.0mA CONDITIONS Data (DQx) Inputs SYMBOL VIHQ VDDQ -0.3 -1.0 -1.0 3.135 2.375 VDDQ UNITS NOTES
TQFP THERMAL RESISTANCE
DESCRIPTION Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) CONDITIONS Test conditions follow standard test methods procedures measuring thermal impedance, EIA/JESD51. SYMBOL UNITS °C/W °C/W NOTES
THERMAL RESISTANCE
DESCRIPTION Junction Ambient (Airflow 1m/s) Junction Case (Top) Junction Bumps (Bottom) NOTE: CONDITIONS Test conditions follow standard test methods procedures measuring thermal impedance, EIA/JESD51. SYMBOL UNITS °C/W °C/W °C/W NOTES
voltages referenced (GND). Overshoot: +4.6V tKC/2 20mA Undershoot: -0.7V tKC/2 20mA Power-up: +3.6V 3.135V 200ms MODE internal pull-up, input leakage ±10µA. load used VOH, testing shown Figure 2.5V I/O. load current higher than shown values. curves available upon request. This parameter sampled.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
OPERATING CONDITIONS MAXIMUM LIMITS
(Note (0°C 70°C; +3.3V +0.3V/-0.165V unless otherwise noted) DESCRIPTION Power Supply Current: Operating Power Supply Current: Idle CONDITIONS Device selected; inputs VIH; Cycle time MIN; MAX; Outputs open Device selected; MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; inputs VDDQ 0.2; Cycle time Device deselected; MAX; inputs VDDQ 0.2; inputs static; frequency Device deselected; MAX; inputs VIH; inputs static; frequency Device deselected; MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; inputs VDDQ 0.2; Cycle time SYMBOL -7.5 UNITS NOTES
IDD1
CMOS Standby
ISB2
Standby
ISB3
Clock Running
ISB4
TQFP CAPACITANCE
DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance CONDITIONS 25°C; MHz; 3.3V SYMBOL UNITS NOTES
CAPACITANCE
DESCRIPTION Address/Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance NOTE: CONDITIONS 25°C; 3.3V SYMBOL UNITS NOTES
VDDQ +3.3V +0.3V/-0.165V 3.3V configuration; VDDQ +2.5V +0.4V/-0.125V 2.5V configuration. specified with output current increases with faster cycle times. IDDQ increases with faster cycle times greater output loading. "Device deselected" means device power-down mode defined truth table. "Device selected" means device active (not power-down mode). Typical values measured 3.3V, 25°C 10ns cycle time. This parameter sampled.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
(Note (0°C 70°C; +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock time Output Times Clock output valid Clock output invalid Clock output Low-Z Clock output High-Z output valid output Low-Z output High-Z Setup Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) Hold Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) NOTE: SYMBOL
tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ tADSS tAAS tCES tADSH tAAH tCEH
-7.5
UNITS NOTES
Test conditions specified with output loading shown Figure 3.3V (VDDQ +3.3V +0.3V/-0.165V) Figure 2.5V (VDDQ +2.5V +0.4V/-0.125V) unless otherwise noted. Measured HIGH above below VIL. This parameter measured with output loading shown Figure 3.3V Figure 2.5V I/O. This parameter sampled. Transition measured ±500mV from steady state voltage. Refer Technical Note TN-58-09, "Synchronous SRAM Contention Design Considerations," more thorough discussion these parameters. "Don't Care" when byte write enable sampled LOW. WRITE cycle defined least byte write enable ADSP# HIGH required setup hold times. READ cycle defined byte write enables HIGH ADSC# ADV# ADSP# required setup hold times. This synchronous device. addresses must meet specified setup hold times rising edges when either ADSP# ADSC# chip enabled. other synchronous inputs must meet setup hold times with stable logic levels rising edges clock (CLK) when chip enabled. Chip enable must valid each rising edge when either ADSP# ADSC# remain enabled.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
3.3V TEST CONDITIONS
Input pulse levels (VDD/2.2) 1.5V (VDD/2.2) 1.5V Input rise fall times Input timing reference levels VDD/2.2 Output reference levels VDDQ/2.2 Output load Figures
2.5V TEST CONDITIONS
Input pulse levels (VDD/2.64) 1.25V (VDD/2.64) 1.25V Input rise fall times Input timing reference levels VDD/2.64 Output reference levels VDDQ/2 Output load Figures
1.5V
Figure 3.3V OUTPUT LOAD EQUIVALENT
1.25V
Figure 2.5V OUTPUT LOAD EQUIVALENT
+3.3V
1,538
+2.5V 1,667
Figure 3.3V OUTPUT LOAD EQUIVALENT
Figure 2.5V OUTPUT LOAD EQUIVALENT
LOAD DERATING CURVES
Micron 256K 128K 128K SyncBurst SRAM timing dependent upon capacitive loading outputs. Consult factory copies current versus voltage curves.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
SNOOZE MODE
SNOOZE MODE low-current, "power-down" mode which device deselected current reduced ISB2Z. duration SNOOZE MODE dictated length time HIGH state. After device enters SNOOZE MODE, inputs except become gated inputs ignored. asynchronous, active HIGH input that causes device enter SNOOZE MODE. When becomes logic HIGH, ISB2Z guaranteed after setup time met. READ WRITE operation pending when device enters SNOOZE MODE guaranteed complete successfully. Therefore, SNOOZE MODE must initiated until valid pending operations completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION Current during SNOOZE MODE active input ignored inactive input sampled active snooze current inactive exit snooze current NOTE: This parameter sampled. CONDITIONS SYMBOL ISB2Z
tRZZ tZZI tRZZI
2(tKC)
UNITS
NOTES
2(tKC) 2(tKC)
SNOOZE MODE WAVEFORM
INPUTS (except
Outputs
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
,,,,
SUPPLY
ISB2Z
RZZI
DESELECT READ Only
High-Z
DON'T CARE
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
READ TIMING
ADDRESS
GW#, BWE#, BWa#-BWd#
(NOTE
READ TIMING PARAMETERS
SYMBOL
tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ
,,,, ,,,,,, ,,,,,,, ,,,, ,,,, ,,,,, ,,,, ,,,,
ADSS tADSH
ADSP#
ADSS
tADSH
ADSC#
Burst continued with base address.
tCEH
Deselect cycle.
tAAH
(NOTE
ADV#
ADV# suspends burst.
(NOTE
OEHZ
KQLZ
OELZ
KQHZ
High-Z
Q(A1)
Q(A2)
Q(A2
Q(A2
Q(A2
Q(A2)
Q(A2
(NOTE
Single READ
BURST READ
Burst wraps around initial state.
DON'T CARE
UNDEFINED
-7.5
UNITS SYMBOL tADSS
tAAS tCES tADSH tAAH tCEH
-7.5
UNITS
NOTE: Q(A2) refers output from address Q(A2 refers output from next internal burst address following CE2# have timing identical CE#. this diagram, when LOW, CE2# HIGH. When HIGH, CE2# HIGH LOW. Timing shown assuming that device enabled before entering into this sequence. does cause driven until after following clock rising edge. Outputs disabled within clock cycle after deselect.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
WRITE TIMING
ADDRESS
BWE#, BWa#-BWd#
(NOTE
WRITE TIMING PARAMETERS
SYMBOL
tOEHZ tADSS tAAS
,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,, ,,,, ,,,,, ,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,, ,,,,, ,,,,,,, ,,,,
ADSS tADSH
ADSP#
ADSS tADSH
ADSC# extends burst.
ADSS tADSH
ADSC#
Byte write signals ignored first cycle when ADSP# initiates burst.
(NOTE
tCEH
tAAH
ADV#
(NOTE
ADV# suspends burst.
(NOTE
High-Z
D(A1)
D(A2)
D(A2
D(A2
D(A2
D(A2
D(A3)
D(A3
D(A3
tOEHZ
(NOTE
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON'T CARE
UNDEFINED
-7.5
UNITS
SYMBOL
tCES tADSH tAAH tCEH
-7.5
UNITS
NOTE: D(A2) refers input address D(A2 refers input next internal burst address following CE2# have timing identical CE#. this diagram, when LOW, CE2# HIGH. When HIGH, CE2# HIGH LOW. must HIGH before input data setup held HIGH throughout data hold time. This prevents input/output data contention time period prior byte write enable inputs being sampled. ADV# must HIGH permit WRITE loaded address. Full-width WRITE initiated LOW; HIGH BWE#, BWa# BWb# device; HIGH BWE#, BWa#-BWd# devices.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
READ/WRITE TIMING
ADDRESS BWE#, BWa#-BWd# (NOTE
(NOTE ADV#
,,,,,,,,,,, ,,,, ,,,,, ,,,,,,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,
ADSS tADSH
ADSP#
ADSC#
tCEH
OELZ
High-Z
tKQLZ
tOEHZ
D(A3)
D(A5)
D(A6)
(NOTE Q(A4)
High-Z
Q(A1)
Q(A2)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs (NOTE
Single WRITE
BURST READ
Back-to-Back WRITEs
DON'T CARE
UNDEFINED
READ/WRITE TIMING PARAMETERS
SYMBOL
tKQLZ tOELZ tOEHZ
-7.5
UNITS SYMBOL tADSS
tCES tADSH tCEH
-7.5
UNITS
NOTE: Q(A4) refers output from address Q(A4 refers output from next internal burst address following CE2# have timing identical CE#. this diagram, when LOW, CE2# HIGH. When HIGH, CE2# HIGH LOW. data remains High-Z following WRITE cycle unless ADSP#, ADSC# ADV# cycle performed. HIGH. Back-to-back READs controlled either ADSP# ADSC#.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
INDEX
0.38 0.22 22.20 21.95 0.65
20.20 19.90 DETAIL
1.60 1.40 14.10 13.90 16.20 15.95 GAGE PLANE 0.25
0.10
0.75 0.45 DETAIL
1.45 1.35
NOTE:
dimensions millimeters
typical where noted. Package width length include mold protrusion; allowable mold protrusion .01" side.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
4Mb: 256K 128K 32/36 PIPELINED, SYNCBURST SRAM
119-BUMP
22.20 21.80 20.04 19.84 Substrate material: resin laminate (TYP) 12.04 11.84 14.20 13.80 0.15 2.40 SEATING PLANE 0.70 0.50 1.00 0.80
CORNER
CORNER
0.90 (dimension applies 0.60 noncollapsed solder ball)
1.27
7.62
1.27 20.32
NOTE:
typical where noted. Package width length include mold protrusion; allowable mold protrusion 0.01" side. dimensions millimeters Solder ball land 0.6mm.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron registered trademark Micron Technology, Inc.
4Mb: 256K 128K 32/36 Pipelined, SyncBurst SRAM MT58L256L18P.p65 Rev. 9/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
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