12-BIT SERIAL DAISY-CHAIN CONVERTER 8143RP OUT1 OUT2 AGND

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12-BIT SERIAL DAISY-CHAIN CONVERTER 8143RP OUT1 OUT2 AGND

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PACE PRODUCTS
12-BIT SERIAL DAISY-CHAIN CONVERTER
8143RP
OUT1 OUT2 AGND
VREF
8143RP
DGND
Memory
FEATURES
Microprocessor interfacing serially controlled systems Buffered digital output daisy-chaining multiple DACs Minimizes address-decoding multiple systems three wire interface number DACs data line line load line Improved resistance Operating temperature:
DESCRIPTION:
Space Electronics' 8143RP -PAK®) 12-bit serial-input daisy-chain CMOS converter that features serial data input buffered serial data output. designed multiple serial systems, where serially daisy-chaining after another greatly simplified. 8143RP also minimizes address decoding lines enabling simpler logic interfacing. allows three-wire interface number DACs: data line, line load line. Serial data input register (MSB first) sequentially clocked data word (MSB first) simultaneously clocked from pin. strobe inputs used clock in/out data rising falling (user selected) strobe edges (STB1, STB2, STB3, STB4). When shift register's data been updated, data word transferred register with inputs. Separate LOAD control inputs allow simultaneous output updating multiple DACs. asynchronous CLEAR input resets register without altering data input register. Improved linearity gain error performance permits reduced circuit parts count through elimination trimming components. Fast interface timing reduces timing design considerations while minimizing microprocessor wait states.
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8143RP
PARAMETER DGND DGND DGND AGND DGND DGND AGND Digital Input Voltage Range Output Voltage (Pin Operating Temperature Range Junction Temperature Storage Temperature Lead Temperature (Soldering, sec)
12-BIT SERIAL DAISY-CHAIN CONVERTER
TABLE 8143RP ABSOLUTE MAXIMUM RATINGS
SYMBOL -0.3 -0.3 TSTG -MAX
Memory
TABLE 8143EP ELECTRICAL HARACTERISTICS 10V; VOUT1 VOUT2 VAGND VDGND FULL TEMPERATURE PECIFIED UNDER BSOLUTE AXIMUM RATIN UNLESS OTHERWISE PECIFIE
PARAMETER STATIC ACCURACY Resolution Nonlinearity Differential Nonlinearity Gain Error Gain Tempco (Gain/Temp) Power Supply Rejection Ratio (Gain/VDD) Output Leakage Current Zero Scale Error Input Resistance PERFORMANCE Output Current Settling Time Feedthrough Error (VREF IOUT1 Digital-to-Analog Glitch Energy 3,10 Total Harmonic Distortion Output Noise Voltage Density 3,11 DIGITAL INPUTS/OUTPUTS Digital Input HIGH
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SYMBOL
ONDITIONS
TCGFS PSRR ILKG IZSE kHz, load CEXT register loaded with between IOUT Full Temperature Range Full Temperature Range
-2.4
-±0.0006 -±0.002 ±0.01 0.380
±0.002 ±0.03 ±0.15
Bits ppm/o nV/Hz
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8143RP
PARAMETER Digital Input Input Leakage Current Input Capacitance Digital Output High Digital Output ANALOG OUTPUTS Output Capacitance Output Capacitance TIMING CHARACTERISTICS Serial Input Strobe Setup Times (tSTB COUT1 COUT2 COUT1 COUT2 Digital Inputs Digital Inputs Digital Inputs Digital Inputs SYMBOL -200 ONDITIONS
12-BIT SERIAL DAISY-CHAIN CONVERTER
TABLE 8143EP ELECTRICAL HARACTERISTICS 10V; VOUT1 VOUT2 VAGND VDGND FULL TEMPERATURE PECIFIED UNDER BSOLUTE AXIMUM RATIN UNLESS OTHERWISE PECIFIE
-TYP -MAX -0.4
tDS1 tDS2 tDS3 tDS4 tDH1 tDH2 STB1 used strobe STB2 used strobe STB3 used strobe full temperature range STB4 used strobe STB1 used strobe full temperature range STB2 used strobe full temperature range STB3 used strobe STB4 used strobe full temperature range -100 temperature range 4.75 digital inputs digital inputs tDH3 tDH4 tSRI tSTB1 tSTB2 tSTB3 tSTB3 tLD1 tLD2 tASB tCLR -220 -5.25
Memory
Serial Input Strobe Hold Times (tSTB Propagation Delay Data Pulsewidth STB1 Pulsewidth (STB1 STB2 Pulsewidth (STB2 STB3 Pulsewidth (STB3 STB4 Pulsewidth (STB4 Load Pulsewidth Strobe into Input Register Load Register Time Pulsewidth POWER SUPPLY Supply Voltage Supply Current
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8143RP
PARAMETER Power Dissipation SYMBOL ONDITIONS
12-BIT SERIAL DAISY-CHAIN CONVERTER
TABLE 8143EP ELECTRICAL HARACTERISTICS 10V; VOUT1 VOUT2 VAGND VDGND FULL TEMPERATURE PECIFIED UNDER BSOLUTE AXIMUM RATIN UNLESS OTHERWISE PECIFIE
-TYP -MAX Digital inputs Digital inputs VIL,
grades monotonic bits over temperature. Using internal feedback resistor. Guaranteed design tested. Applies OUT; digital inputs VIL, 10V; specification also applied OUT2 when digital inputs 10V, digital inputs Calculated from worst case REF: IZSE LSBs) ILKG 4096)/VREF. Absolute temperature coefficient less than ppm/oC. IOUT, Load CEXT digital input Extrapolated LSB: propagation delay (tPD) where equals measured time constant final decay. digital inputs digital inputs Calculations from where: Boltzmann constant, J/KR resistance resistor temperature, bandwidth, Digital input CMOS gates; typically Measured from active strobe edge (STB) data output SRO; Minimum time pulsewidth STB1, minimum high time pulsewidth
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FIGURE MULTIPLE WITH THREE-WIRE INTERFACE
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8143RP
12-BIT SERIAL DAISY-CHAIN CONVERTER
FIGURE MULTIPLYING MODE FREQUENCY RESPONSE DIGITAL CODE
FIGURE ULTIPLYING MODE TOTAL HARMONIC DISTORTION FREQUENCY
Memory
FIGURE SUPPLY CURRENT LOGIC NPUT VOLTAGE
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8143RP
12-BIT SERIAL DAISY-CHAIN CONVERTER
FIGURE LINEARITY ERROR DIGITAL CODE
FIGURE LINEARITY ERROR EFERENCE VOLTAGE
Memory
FIGURE OGIC THRESHOLD VOLTAGE SUPPLY VOLTAGE
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8143RP
12-BIT SERIAL DAISY-CHAIN CONVERTER
FIGURE ERROR EFERENCE OLTAGE
FIGURE IGITAL OUTPUT OLTAGE OUTPUT URRENT
Memory
Definition Specifications resolution number states into which full-scale range (FSR) divided resolved), where equal number bits. Settling Time Time required analog output settle within final value given digital input stimulus; i.e., zero full-scale. Gain Ratio DAC's external operational amplifier output voltage VREF input voltage when digital inputs HIGH. Feedthrough Error Error caused capacitive coupling from VREF output. Feedthrough error limits specified with switches off. Output Capacitance Capacitance from IOUT1 ground. Output Leakage Current Current appearing OUT1 when digital inputs LOW, IOUT2 terminal when inputs HIGH.
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8143RP
General Circuit Information
12-BIT SERIAL DAISY-CHAIN CONVERTER
8143RP 12-bit serial-input, buffered serial-output, multiplying CMOS converter. R-2R resistor ladder network, 12-bit input sift register, 12-bit register, control logic circuitry, buffered digital output stage. control logic forms interface which serial data loaded, under microprocessor control, into input sift register then transferred, parallel, register. addition, buffered serial output data present when input data loaded into input register. This buffered data follows digital input data (SRI) clock cycles available daisy-chaining additional DACs. asynchronous CLEAR function allows resetting register zero code (0000 0000 0000) without altering data stored registers. simplified circuit 8143RP shown Figure inverses R-2R ladder network consisting silicon-chrome, thin-film resistors, twelve pairs NMOS current-steering switches. These switches steer binarily weighted currents into either OUT1 OUT2. Switching current IOUT1 IOUT2 yields constant current each ladder leg, regardless digital input code. This constant current results constant input resis tance VREF equal (typically VREF input driven reference voltage current, that within limits stated Absolute Maximum Ratings chart. twelve output current-steering switches series with R-2R resistor ladder, therefore, introduce errors essential design these switches such that switch "ON" resistance binarily scaled that voltage drop across each switch remains constant. example, Switch Figure designed with "ON" resistance Switch etc., constant drop would then maintained across each switch. further ensure accuracy across full temperature range, permanently "ON" switches were included series with feedback resistor R-2R ladder's terminating resistor. Simplified Circuit, Figure shows location these switches. These series switches equivalently scaled times Switch (MSB) Switch (LSB) maintain constant relative voltage drops with varying temperature. During testing resistor ladder RFEEDBACK (such incoming inspection), must present turn "ON" these serial switches.
Memory
FIGURE SIMPLIFIED IRCUIT
Protection 8143RP digital inputs have been designed with resistance incorporated through careful layout inclusion input protection circuitry. Figure shows input protection diodes. High voltage static charges applied digital inputs shunted supply ground rails through forward biased diodes. These protection diodes were designed clamp inputs well below dangerous levels during static discharge conditions.
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8143RP
12-BIT SERIAL DAISY-CHAIN CONVERTER
FIGURE DIGITAL INPUT PROTECTION
Equivalent Circuit Analysis Figures show equivalent circuits 8143RP internal with bits HIGH, respectively. reference current switched IOUT2 when data bits LOW, IOUT1 when bits HIGH. ILEAKAGE current source combination surface junction leakages substrate. 1/4096 current source represents constant 1-bit current drain, through ladder's terminating resistor.
Memory
Output capacitance dependent upon digital input code. This because capacitance transistor changes with plied gate voltage. This output capacitance varies between high values.
FIGURE EQUIVALENT CIRCUIT (ALL NPUTS LOW)
FIGURE EQUIVALENT IRCUIT (ALL INPUT HIGH)
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8143RP
Dynamic Performance
Analog Output Impedance
12-BIT SERIAL DAISY-CHAIN CONVERTER
output resistance, case output capacitance, varies with digital input code. This resistance, looking back into IOUT1 terminal, varies between (the feedback resistor alone when digital input LOW) (the feedback resistor parallel with approximately R-2R ladder network resistance when single logic HIGH). Static accuracy dynamic performance will affected these variations. gain phase stability output amplifier, board layout, power supply decoupling will affect dynamic performance 8143RP. small compensation capacitor required when high speed operational amplifier's feedback resistor provide necessary phase compensation critically damp output. considerations when using high speed amplifiers are: Phase compensation (see Figures 17). Power supply decoupling device socket proper grounding techniques. Output Amplifier Considerations When using high speed amps, small feedback capacitor (typically pF-30 should used across amplifiers minimize overshoot ringing. speed static applications, specification amplifier very critical. high speed applications, slew rate, settling time, openloop gain gain/phase margin specifications amplifier should selected desired performance. already been noted that offset caused including usual bias current compensation resistor amplifier's noninverting input terminal. This resistor should used. Instead, amplifier should have bias current that over temperature range interest. Static accuracy affected variation DAC's output resistance. This variation best illustrated using cuit Figure equation:
Memory
FIGURE SIMPLIFIED CIRCUIT
Where function digital code, and: more than four bits Logic single Logic
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8143RP
Therefore, offset gain varies follows: code 0011 1111 1111,
12-BIT SERIAL DAISY-CHAIN CONVERTER
code 0100 0000 0000,
error difference Since weight (for 10V) 8143RP, clearly important that minimized, using either amplifier's pulling pins, external pulling network, selection amplifier with inherently Amplifiers with sufficiently include OP77RP, OP07RO OP27RP. Interface Logic Operation microprocessor interface 8143RP been designed with multiple STROBE LOAD inputs maximize interfacing option Control signals decoding done chip with external decoding circuitry (see Figure 21). Serial data clocked into input register buffered output stage with STB2, STB4. strobe inputs active rising edge. STB3 used with falling edge clock data. Serial data output (SRO) follows serial data input (SRI) clocked bits. Holding STROBE input selected state (i.e., STB2, STB4 logic HIGH STB3 logic LOW) will prevent further data input. When data word been entered into input register, transferred register asserting both LOAD inpu input allows asynchronous resetting register 0000 0000 0000. This reset does affect data held input registers. While unipolar mode, CLEAR will result analog output going bipolar mode, output will REF. Interface Input Description STB1 (Pin (Pin STB4 (Pin Input register buffered output strobe. Inputs active falling edge. Selected load serial data into input register buffered output stage. Table details. STB3 (Pin Input register buffered output strobe input. Active falling edge. Selected load serial data into input register buffered output stage. Table details. (Pin (Pin Load register inputs. Active low. Selected together load contents input register into register. (Pin Clear input. Active low. Asynchronous. When LOW, 12-bit register forced zero code (0000 0000 0000) regardless other interface inputs.
Memory
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8143RP
12-BIT SERIAL DAISY-CHAIN CONVERTER
FIGURE TIMING DIAGRAM
Strobe waveform inverted used strobe serial data bits into input register. Data strobed into input shift register first.
Memory
TABLE TRUTH TABLE
NPUT EGISTER/D IGITAL UTPUT STB4 STB3 CONTROL INPUTS STB2 STB1 REGISTER ONTROL INPUT Serial data loaded from into input register digital output (SRO pin) after clocked bits operation (input register SRO)
OPERATION
NOTES
Reset register zero code (Code: 0000 0000 0000) Asynchronous operations) operation (DAC register SRO) Load register with contents input register
Serial data loaded into Input Register first, edges shown. positive edges, negative edge. Logic LOW, Logic HIGH, Don't care. asynchronously resets register 0000 0000 0000, effect Input Register.
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8143RP
Applications Information
12-BIT SERIAL DAISY-CHAIN CONVERTER
Unipolar Operation (2-Quadrant) circuit shown Figures used with reference voltage. circuit's output will range between (4095/4096) depending upon digital input analog output shown Table voltage range maximum input voltage range ±25V, whichever lowest.
TABLE NIPOLAR CODE TABLE
IGITAL NPUT 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000 NOMINAL ANALOG UTPUT HOWN FIGURES -VREF (4095/4096) -VREF (2049/4096) -VREF (2048/4096) -VREF/2 -VREF (2047/4096) (1/4096) (0/4096)
FIGURE NIPOLAR OPERATION WITH HIGH CCURACY (2-QUADRANT
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FIGURE UNIPOLAR OPERATION WITH FAST GAIN ERROR TRIMMING (2-QUADRANT
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8143RP
12-BIT SERIAL DAISY-CHAIN CONVERTER
many applications, 8143RP zero scale error gain error, permit elimination external trimming components without adverse effects circuit performance. applications requiring tighter gain error than 0.024% grade part, 0.048% lower grade part, circuit Figure used. Gain error trimmed adjusting register must first loaded with then adjusted until -VREF (4095/4096). case adjustable VREF, RFEEDBACK omitted, with VREF adjusted yield desired full-scale output. Bipolar Operation (4-Quadrant) Figure details suggested circuit bipolar, offset binary, operation. Table shows digital input-to-analog output relationship. circuit uses offset binary coding. Twos complement code converted offset binary software inversion addition external inverter input. Resistor must selected match within 0.01% must same (preferably metal foil) type assure temperature coefficient match. Mismatching between causes offset full-scale error. Calibration performed loading register with 1000 0000 0000 adjusting ratio yield Full scale adjusted loading register with 1111 1111 1111 adjusting either amplitude value until desired VOUT achieved.
TABLE BIPOLAR FFSET INARY CODE ABLE
IGITAL NPUT 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000 NOMINAL ANALOG UTPUT SHOWN FIGURE (2047/2048) (1/2048) (1/2048) -VREF (2047/2048) -VREF (2048/2048)
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Daisy-Chaining 8143RP Many applications multiple serial input DACs that numerous interconnecting lines address decoding data lines. addition, they some type buffering reduce loading bus. 8143RP ideal just such application. only reduces number interconnecting lines, also reduces loading. 8143RP daisy-chained with only three lines: data line, load lines, Figure
FIGURE BIPOLAR PERATION (4-QUADRANT, OFFSET INARY)
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8143RP
12-BIT SERIAL DAISY-CHAIN CONVERTER
FIGURE MULTIPLE 8143RP WITH THREE NTERFACE
Memory
Analog/Digital Division transfer function 8143RP connect multiplying mode shown Figures
where assumes value "ON" "OFF" bit. transfer function modified when connected feedback operational amplifier shown Figure
above transfer function division analog voltage (VREF) digital word. amplifier goes rails with bits "OFF" since division zero infinity. With bits "ON", gain LSB). gain becomes 4096 with LSB, "ON".
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8143RP
12-BIT SERIAL DAISY-CHAIN CONVERTER
FIGURE ANALOG/DIGITAL DIVIDER
Memory
Application Tips most applications, linearity depends potential OUT1, IOUT2, AGND (Pins being exactly equal each other. most applications, connected external with noninverting input tied ground (see Figures 17). amplifier selected should have input bias current drift over temperature. amplifier's input offset voltage shoudl nulled less than ±200 (less than LSB). operational amplifier's noninverting input should have minimum resistance connection ground; usual bias current pensation resistor should used. This resistor cause variable offset voltage appearing varying output error. grounded pins should single common ground point, avoiding ground loops. power supply should have noise level with transients greater than 17V. recommended that digital input taken ground high value resistor, this will prevent accumulation static charge card disconnected from system. Peak supply current flows digital input pass through transition region (see Figure supply current decreases input voltage approaches supply rails (VDD DGND), i.e., rapidly slewing lofic signals that settle very near supply rails will minimize supply current. Interfacing MC6800 shown Figure, 8143RP interfaced 6800 successively executing memory WRITE instruction while manipulating data between WRITEs, that each WRITE presents next bit. this example, most significant bits found memory locations 0000 0001. four MSBs found lower half 0000, eight LSBs 0001. data taken from line. serial data loading triggered STB4 which asserted decoded memory WRITE memory location, R/W, WRITE another address location transfers data from input register register.
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8143RP
12-BIT SERIAL DAISY-CHAIN CONVERTER
FIGURE MC6800 INTERFACE
Interface 8085 8143RP's interface 8085 microprocessor shown Figure Note that microprocessor's line used present data serially DAC. Data strobed into 8143RP executing memory write instructions. strobe input generated decoding address location Data loaded into register with memory write instruction another address location. Serial data supplied 8143RP must present right-justified format registers microprocessor.
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FIGURE 8085 NTERFACE
Interface 68000 Figure shows 8143RP configured 68000 microprocessor. Serial data input similar that 6800 Figure
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8143RP
12-BIT SERIAL DAISY-CHAIN CONVERTER
FIGURE 8143RP 68000 NTERFACE
Memory
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8143RP
12-BIT SERIAL DAISY-CHAIN CONVERTER
Memory
RAD-PAK® FLAT PACKAGE
YMBOL 0.325 0.020 0.005 0.120 0.015 0.004 -0.245 -0.130 0.030 DIMENSION 0.135 0.017 0.005 0.415 0.280 -0.156 0.062 0.050 0.335 0.033 0.024 0.345 0.045 0.045 0.150 0.022 0.009 0.440 0.285 0.315
F16-01 Note: Dimensions inches
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8143RP
Important Notice:
12-BIT SERIAL DAISY-CHAIN CONVERTER
These data sheets created using chip manufacturers published specifications. Space Electronics verifies functionality testing parameters either 100% testing, sample testing characterization. specifications presented within these data sheets represent latest most accurate information available date. However, these specifications subject change without notice Space Electronics assumes responsibility this information. Space Electronics' products authorized critical components life support devices systems without express written approval from Space Electronics. claim against Space Electronics Inc. must made within days from date shipment from Space Electronics. Space Electronics' liability shall limited replacement defective parts.
Memory
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12-BIT SERIAL DAISY-CHAIN CONVERTER 8143RP OUT1 OUT2 AGND

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