8/16-BIT FULL SPEED COMPOSITE DEVICES WITH ENDPOINTS, ROM, RAM, I2C, S
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ST92163
8/16-BIT FULL SPEED COMPOSITE DEVICES WITH ENDPOINTS, ROM, RAM, I2C, SCI,
Internal Memories: Kbytes ROM/EPROM/ OTP, Kbytes Register oriented 8/16 core general purpose registers available RAM, accumulators index pointers Minimum instruction cycle time: (@24 frequency) power modes: WFI, SLOW, HALT STOP controller reduced processor overhead Full speed interface with DMA, compliant with specifications version normal voltage mode) Embedded Functions with fully configurable endpoints (buffer size programmable), supporting data transfer types (Isochronous included) On-chip transceiver voltage regulator Multimaster I2C-bus serial interface 400KHz. with capability Serial Communications Interface (SCI) with capability: Asynchronous mode Kb/s Synchronous mode External memory interface (8-bit data/16-bit address) with capability from 16-bit Multi-Function Timer operating modes) with capability 16-bit Timer with 8-bit prescaler Watchdog 6-channel, 8-bit Converter (ADC) interrupt pins interrupt channels pins programmable wake-up additional external interrupts fully programmable I/Os with high sink pads Programmable clock generator (RCCU) using frequency external quartz MHz) On-chip oscillator power operation
TQFP64
Voltage Detector Reset some devices Rich instruction with addressing modes Several operating voltage modes available some devices1: Normal Voltage Mode 8-MHz Voltage Mode 16-MHz Voltage Mode clock operation 4.0-5.5 (all devices) clock operation 3.0-4.0 (8MHz 16-MHz Voltage devices) clock operation 3.0-4.0 (16-MHz Voltage devices only) Division-by-zero trap generation temperature range design supporting single sided Complete development tools, including assembler, linker, C-compiler, archiver, source level debugger hardware emulators, Real Time Operating System
Note Refer "Device Summary" page
January 2002
Rev.
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Table Contents
ST92163
GENERAL DESCRIPTION INTRODUCTION 1.1.1 Core Architecture 1.1.2 Instruction 1.1.3 External MEMORY INTERFACE 1.1.4 OPERATING MODES 1.1.5 On-chip Peripherals DESCRIPTION PORT PINS MEMORY ST92163 REGISTER DEVICE ARCHITECTURE CORE ARCHITECTURE MEMORY SPACES 2.2.1 Register File 2.2.2 Register Addressing SYSTEM REGISTERS 2.3.1 Central Interrupt Control Register 2.3.2 Flag Register 2.3.3 Register Pointing Techniques 2.3.4 Paged Registers 2.3.5 Mode Register 2.3.6 Stack Pointers MEMORY ORGANIZATION
MEMORY MANAGEMENT UNIT ADDRESS SPACE EXTENSION 2.6.1 Addressing 16-Kbyte Pages 2.6.2 Addressing 64-Kbyte Segments REGISTERS 2.7.1 DPR[3:0]: Data Page Registers 2.7.2 CSR: Code Segment Register 2.7.3 ISR: Interrupt Segment Register 2.7.4 DMASR: Segment Register USAGE 2.8.1 Normal Program Execution 2.8.2 Interrupts 2.8.3 INTERRUPTS INTRODUCTION
INTERRUPT VECTORING 3.2.1 Divide Zero trap 3.2.2 Segment Paging During Interrupt Routines INTERRUPT PRIORITY LEVELS
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Table Contents
PRIORITY LEVEL ARBITRATION 3.4.1 Priority Level (Lowest) 3.4.2 Maximum Depth Nesting 3.4.3 Simultaneous Interrupts 3.4.4 Dynamic Priority Level Modification ARBITRATION MODES
3.5.1 Concurrent Mode 3.5.2 Nested Mode EXTERNAL INTERRUPTS MANAGEMENT WAKE-UP LINES EXTERNAL INTERRUPT LINES LEVEL INTERRUPT ON-CHIP PERIPHERAL INTERRUPTS 3.10 INTERRUPT RESPONSE TIME 3.11 INTERRUPT REGISTERS 3.12 WAKE-UP INTERRUPT LINES MANAGEMENT UNIT (WUIMU) 3.12.1 Introduction 3.12.2 Main Features 3.12.3 Functional Description 3.12.4 Programming Considerations 3.12.5 Register Description ON-CHIP DIRECT MEMORY ACCESS (DMA) INTRODUCTION
PRIORITY LEVELS TRANSACTIONS CYCLE TIME SWAP MODE REGISTERS RESET CLOCK CONTROL UNIT (RCCU) INTRODUCTION CLOCK CONTROL UNIT 5.2.1 Clock Control Unit Overview CLOCK MANAGEMENT 5.3.1 Clock Multiplier Programming 5.3.2 Clock Prescaling 5.3.3 Peripheral Clock 5.3.4 Power Modes 5.3.5 Interrupt Generation CLOCK CONTROL REGISTERS
OSCILLATOR CHARACTERISTICS RESET/STOP MANAGER 5.6.1 RESET Timing STOP MODE VOLTAGE DETECTOR (LVD) RESET EXTERNAL MEMORY INTERFACE (EXTMI)
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Table Contents
INTRODUCTION EXTERNAL MEMORY SIGNALS 6.2.1 Address Strobe 6.2.2 Data Strobe 6.2.3 DS2: Data Strobe 6.2.4 Read/Write 6.2.5 BREQ, BACK: Request, Acknowledge 6.2.6 PORT 6.2.7 PORT 6.2.8 WAIT: External Memory Wait REGISTER DESCRIPTION
PORTS INTRODUCTION SPECIFIC PORT CONFIGURATIONS PORT CONTROL REGISTERS INPUT/OUTPUT CONFIGURATION ALTERNATE FUNCTION ARCHITECTURE 7.5.1 Declared 7.5.2 Declared Alternate Function Input 7.5.3 Declared Alternate Function Output STATUS AFTER WFI, HALT RESET
ON-CHIP PERIPHERALS TIMER/WATCHDOG (WDT) 8.1.1 Introduction 8.1.2 Functional Description 8.1.3 Watchdog Timer Operation 8.1.4 Interrupts 8.1.5 Register Description MULTIFUNCTION TIMER (MFT) 8.2.1 Introduction 8.2.2 Functional Description 8.2.3 Input Assignment 8.2.4 Output Assignment 8.2.5 Interrupt 8.2.6 Register Description PERIPHERAL (USB) 8.3.1 Introduction 8.3.2 Main Features 8.3.3 Functional Description 8.3.4 Register Description 8.3.5 Register pages summary MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) 8.4.1 8.4.2 8.4.3 8.4.4 Introduction Main Features Functional Description SCI-M Operating Modes
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Table Contents
8.4.5 Serial Frame Format 8.4.6 Clocks Serial Transmission Rates 8.4.7 Initialization Procedure 8.4.8 Input Signals 8.4.9 Output Signals 8.4.10 Interrupts 8.4.11 Register Description INTERFACE
8.5.1 Introduction 8.5.2 Main Features 8.5.3 Functional Description 8.5.4 State Machine 8.5.5 Interrupt Features 8.5.6 Features 8.5.7 Register Description CONVERTER (A/D) 8.6.1 Introduction 8.6.2 Main Features 8.6.3 General Description 8.6.4 Register Description ELECTRICAL CHARACTERISTICS GENERAL INFORMATION 10.1 EPROM/OTP PROGRAMMING
10.2 PACKAGE DESCRIPTION 10.3 ORDERING INFORMATION 10.4 TRANSFER CUSTOMER CODE SUMMARY CHANGES
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ST92163 GENERAL DESCRIPTION
GENERAL DESCRIPTION
INTRODUCTION ST9216x family brings enhanced register-based architecture range highperformance microcontrollers specifically designed (Universal Serial Bus) applications. Their performance derives from flexible 256-register programming model ultrafast context switching real-time event response. intelligent on-chip peripherals offload core from data management processing tasks allowing critical application tasks maximum core resources. devices support power consumption voltage operation power-efficient low-cost embedded systems. ST92163 family, four different types device available: Normal Voltage Devices with function They operate Normal Voltage Mode only (4.05.5V 24MHz) include Voltage Detector (LVD) function. Normal Voltage Devices without function They operate Normal Voltage Mode only (4.05.5V 24MHz) include Voltage Detector (LVD) function. Device Summary
Device ST921631 ST92T163 ST92E163 ST92163E1 ST92T163E ST92E163E ST92163L1 ST92T163L ST92E163L ST92163V1 ST92T163V1 ST92E163V1
8-MHz Voltage Devices They include Voltage Detector (LVD) function they support operating voltage modes: Normal Voltage mode (4.0-5.5V 24MHz) with full functionality including USB. 8-MHz Voltage mode (3.0-4.0V 8MHz) without interface. 16-MHz Voltage Devices They include Voltage Detector (LVD) function they support three operating voltage modes: Normal Voltage mode (4.0-5.5V 24MHz) with full functionality including USB. 8-MHz Voltage mode (3.0-4.0V 8MHz) without interface. 16-MHz Voltage mode (3.0-4.0V 16MHz) without interface. Figure page shows operating range ST92163 devices.
Package TQFP64 CQFP64 TQFP64 CQFP64 TQFP64 CQFP64 TQFP64 CQFP64
Program Memory EPROM EPROM EPROM EPROM
16-MHz 8-MHz Voltage Voltage Mode Mode
Normal Mode only
Contact sales office availability
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ST92163 GENERAL DESCRIPTION
INTRODUCTION (Cont'd) Figure Maximum Operating Frequency (fMAX) versus Supply Voltage
FREQUENCY (MHz) SUPPLY VOLTAGE FUNCTIONALITY GUARANTEED THIS AREA
16-MHz VOLTAGE MODE
NORMAL VOLTAGE MODE
8-MHz VOLTAGE MODE
Notes: This mode supported 16-MHz Voltage devices only This mode supported 8-MHz Voltage devices 16-MHz Voltage devices This mode supported devices
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ST92163 GENERAL DESCRIPTION
INTRODUCTION (Cont'd) Figure ST92163 Architectural Block Diagram
BACK BREQ WAIT A[15:0] D[7:0] TINA TINB TOUTA TOUTB AIN[5:0] EXTRG
P0[7:0] P1[7:0] P3[7:0] P4[3:0] P5[7:0] P6[5:0] P6[7:6]*
ROM/ EPROM/OTP External Memory Interface
USBGND USBVCC USBDM0 USBDP0 USBOE USBSOF with endpoints 5V/3.3V Voltage Regulator MEMORY TIMER
Converter
bytes Register File 8/16-bit
Fully Prog. I/Os
INT[7:0]
Interrupt Management ST9+ CORE REGISTER
Voltage Detector LVD**
WKUP[14:0]
OSCIN OSCOUT RESET INTCLK
Wakeup Interrupt Management RCCU
TXCLK RXCLK SOUT CLKOUT
WATCHDOG TIMER
WDIN WDOUT
MIRROR REGISTER
alternate functions (Italic characters) mapped Ports 0,1, *64-pin devices only **on some devices only (refer "Device Summary" page
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ST92163 GENERAL DESCRIPTION
INTRODUCTION (Cont'd) 1.1.1 Core Architecture nucleus ST92163 enhanced Core that includes Central Processing Unit (CPU), register file, interrupt controller, Memory Management Unit (MMU). Three independent buses controlled Core: 22-bit memory bus, 8-bit register addressing 6-bit interrupt/DMA which connects interrupt controllers on-chip peripherals with core. This multiple architecture makes family devices highly efficient accessing off-chip memory fast exchange data with on-chip peripherals. general-purpose registers used accumulators, index registers, address pointers. Adjacent register pairs make 16-bit registers addressing 16-bit processing. Although 8-bit ALU, chip handles 16-bit operations, including arithmetic, loads/stores, memory/register memory/memory exchanges. Many opcodes specify byte word operations, hardware automatically handles 16-bit operations accesses. interrupts subroutine calls, uses system stack conjunction with stack pointer (SP). separate user stack separate stacks, without size limitations, on-chip Register File) off-chip memory. 1.1.2 Instruction instruction consists instruction types, including instructions handling, byte (8-bit) word (16-bit) data, well Boolean formats. Instructions have been added facilitate large program data handling through MMU, well improve performance code density Function calls. addressing modes available, including powerful indirect addressing capabilities. bit-manipulation instructions set, clear, complement, test set, load, various logic instructions (AND, XOR). Math
functions include add, subtract, increment, decrement, decimal adjust, multiply divide. 1.1.3 External MEMORY INTERFACE ST92163 device 16-bit external address allowing address bytes external memory. 1.1.4 OPERATING MODES optimize performance versus power consumption device, devices support range operating modes that dynamically selected depending performance functionality requirements application given moment. Mode. This full speed execution mode with peripherals running maximum clock speed delivered Phase Locked Loop (PLL) Clock Control Unit (CCU). Slow Mode. Power consumption significantly reduced running peripherals reduced clock speed using Prescaler Clock Divider. Wait Interrupt Mode. Wait Interrupt (WFI) instruction suspends program execution until interrupt request acknowledged. During WFI, clock halted while peripheral interrupt controller keep running frequency programmable CCU. this mode, power consumption device reduced more than WFI). Halt Mode. When executing HALT instruction, Watchdog enabled, peripherals stop operating status machine remains frozen (the clock also stopped). reset necessary exit from Halt mode. Stop Mode. Under user program control, (see Wake-up Interrupt Management Unit), peripherals stop operating status machine remains frozen (the clock also stopped) until program execution woken event external Wake-up pin.
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ST92163 GENERAL DESCRIPTION
INTRODUCTION (Cont'd) 1.1.5 On-chip Peripherals Interface interface provides full speed compliant port with embedded transceiver voltage regulator. endpoints available supporting devices. Separate transmit receive channels available each device fast data transfers with internal RAM. Parallel Ports provided with dedicated lines input/ output. These lines, grouped into 8-bit ports, independently programmed provide parallel input/output carry input/output signals from on-chip peripherals core. ports have active pull-ups pull-down resistors compatible with loads. addition pull-ups turned open drain operation weak pullups turned save chip resistive pullups. Input buffers either CMOS compatible. High Current outputs available driving external devices such LEDs. Multifunction Timer Multifunction Timer 16-bit Up/Down counter supported 16-bit compare registers, 16-bit input capture registers channels. Timing resolution programmed using 8-bit prescaler. operating modes allow range different timing functions easily performed such complex waveform generation, measurement output.
16-bit Timer/Watchdog Timer/Watchdog peripheral used watchdog wide range other timing functions such generating periodic interrupts, measuring input signal pulse widths, requesting interrupt after number events. also generate square wave output signal. Serial Communications Controller provides synchronous asynchronous serial port using channels. Baud rates data formats programmable. Controller applications further benefit from self test address wake-up facility offered character search mode. Interface synchronous serial connecting multiple devices using data line clock line. Multimaster slave modes supported. Data transfer between memory performed DMA. interface supports 10-bit addressing. operates multimaster slave mode supports speeds KHz. events (Bus busy, slave address recognized) error conditions automatically flagged peripheral registers interrupts optionally generated. Analog/Digital Converter provides analog inputs with onchip sample hold, fast conversion time 8bit resolution. Conversion triggered signal from Multifunction Timer (MFT).
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ST92163 GENERAL DESCRIPTION
DESCRIPTION
Figure 64-Pin Package Pin-Out
WKUP14/A10/P1.2 WKUP14/A9/P1.1 WKUP14/A8/P1.0 D7/A7/P0.7 D6/A6/P0.6 D5/A5/P0.5 D4/A4/P0.4 D3/A3/P0.3 D2/A2/P0.2 D1/A1/P0.1 D0/A0/P0.0 AIN5/P6.7 AIN4/P6.6 USBSOF/AIN3/P6.5 USBSOF/AIN2/P6.4 XTOUT/WKUP13/AIN1/P6.3
P1.3/A11/WKUP14 P1.4/A12/WKUP14 P1.5/A13/WKUP14 P1.6/A14/WKUP14 P1.7/A15/WKUP14 N.C. N.C. P4.0/BREQ P4.1/WAIT P4.2 P4.3//BACK USBDM0 USBDP0 N.C. N.C. USBVCC USBGND P3.0/INT7/SOUT P3.1/INT7/RTS P3.2/INT7/TXCLK/CLKOUT P3.3/INT7/RXCLK P3.4/INT7/DCD P3.5/INT7/SIN P3.6/INT7/AS P3.7/INT7/SDS RESET P5.0/INT1/TINA N.C.
N.C. connected
AVDD WKUP12/AIN0/INTCLK/P6.2 WKUP11/SCL/EXTRG/INT6/P6.1 WKUP10/SDA/INT5/P6.0 OSCIN OSCOUT WDOUT/NMI/P5.7 WKUP9/TOUTB/P5.6 RW/WDIN/INT0/P5.5 USBOE/WKUP8/P5.4 TOUTA/INT2/P5.3 INT3/P5.2 TINB/INT4/P5.1 N.C.
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ST92163 GENERAL DESCRIPTION
Figure 56-Pin Package Pin-Out
WKUP3/RXCLK/INT7/P3.3 WKUP2/CLKOUT/TXCLK/INT7/P3.2 WKUP1/RTS/INT7/P3.1 WKUP0/SOUT/INT7/P3.0 USBGND USBVCC USBDP0 USBDM0 BACK/P4.3 P4.2 WAIT/P4.1 BREQ/P4.0 WKUP14/A15/P1.7 WKUP14/A14/P1.6 WKUP14/A13/P1.5 WKUP14/A12/P1.4 WKUP14/A11/P1.3 WKUP14/A10/P1.2 WKUP14/A9/P1.1 WKUP14/A8/P1.0 D7/A7/P0.7 D6/A6/P0.6 D5/A5/P0.5 D4/A4/P0.4 D3/A3/P0.3 P3.4/INT7/DCD/WKUP4 P3.5/INT7/SIN/WKUP5 P3.6/INT7/ASN/WKUP6 P3.7/INT7/SDS/WKUP7 RESET P5.0/INT1/TINA P5.1/INT4/TINB P5.2/INT3 P5.3/INT2/TOUTA P5.4/WKUP8/USBOE P5.5/INT0/WDIN/RW P5.6/TOUTB/WKUP9 P5.7/NMI/WDOUT OSCOUT OSCIN P6.0/INT5/SDA/WKUP10 P6.1/INT6/EXTRG/SCL/WKUP11 P6.2/INTCLK/AIN0/WKUP12 AVDD P6.3/AIN1/WKUP13/XTOUT P6.4/AIN2/USBSOF P6.5/AIN3/USBSOF P0.0/A0/D0 P0.1/A1/D1 P0.2/A2/D2
Note: ST92163 devices DIP56 available development purposes. Table Power Supply Pins
QFP64 DIP56 Name Function Main Power Supply Voltage pins internally connected) Digital Circuit Ground pins internally connected) Analog Circuit Supply Voltage EPROM Programming Voltage. Must connected ground normal operating mode.
Table Primary Function pins
Name OSCIN OSCOUT RESET USBGND USBVCC USBDM0 USBDP0 Data Strobe Oscillator Input Oscillator Output Reset initialize ground level voltage regulator output Upstream port Data- line Upstream port Data+ line Function QFP64 DIP56
AVDD
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ST92163 GENERAL DESCRIPTION
Port Pins ports device programmed Input/Output Input mode, compatible with CMOS levels (except where Schmitt Trigger present). Each programmed individually (Refer ports chapter). TTL/CMOS Input those port bits where input schmitt trigger implemented, always possible program input level CMOS compatible programming relevant PxC2.n control bit. Refer Ports Chapter section titled "Input/ Output Configuration". Push-Pull/OD Output output buffer programmed pushpull open-drain: attention must paid fact that open-drain option corresponds only disabling P-channel transistor buffer itself: still present physically connected pin. Consequently possible increase output voltage over VDD+0.3 Volt, avoid direct junction biasing. Pure Open-drain Output user increase voltage over VDD+0.3 Volt where P-channel transistor physically absent: this allowed "Pure Open Drain" pins. course, this case push-pull option available weak pull-up must implemented externally.
Table Port Characteristics
Port 0[7:0] Port 1[7:0] Port 3[7:0] Port 4[3:0] Port 5[7:0] Port 6[1:0] Port 6[5:2] Port Port Input TTL/CMOS TTL/CMOS Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger TTL/CMOS Schmitt trigger TTL/CMOS Output Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Push-Pull/OD Pure Open Drain with high sink capability Push-Pull/OD with high sink capability Push-Pull/OD with high sink capability Push-Pull/OD with high sink capability Weak Pull-Up Reset State Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional
Legend: Weak Pull-Up, Open Drain
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ST92163 GENERAL DESCRIPTION
Table ST92163 Alternate Functions
QFP64 DIP56 Alternate Functions
Port Name
General Purpose
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0
A0/D0 A1/D1 A2/D2 A3/D3 A4/D4 A5/D5 A6/D6 A7/D7 WKUP14 WKUP14 WKUP14 WKUP14 WKUP14 WKUP14 WKUP14 WKUP14 WKUP0
Ext. Mem. Address/Data Ext. Mem. Address/Data Ext. Mem. Address/Data Ext. Mem. Address/Data Ext. Mem. Address/Data Ext. Mem. Address/Data Ext. Mem. Address/Data Ext. Mem. Address/Data Ext. Mem. Address Wakeup Line (***)
P1.1
Ext. Mem. Address Wakeup Line (***)
P1.2
P1.3
P1.4
ports useable general purpose (input, output bidirectional)
Ext. Mem. Address Wakeup Line (***)
Ext. Mem. Address Wakeup Line (***)
Ext. Mem. Address Wakeup Line (***)
P1.5
Ext. Mem. Address Wakeup Line (***)
P1.6
Ext. Mem. Address Wakeup Line (***)
P1.7
Ext. Mem. Address Wakeup Line (***) Wakeup Line External Interrupt Data Output Wakeup Line External Interrupt Request Send
P3.0
INT7 SOUT WKUP1
P3.1
INT7
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ST92163 GENERAL DESCRIPTION
Port Name
QFP64
DIP56
General Purpose
Alternate Functions
WKUP2 P3.2 INT7 TXCLK CLKOUT WKUP3 P3.3 INT7 RXCLK
Wakeup Line External Interrupt Transmit Input Clock Output Wakeup Line External Interrupt Receive Input
WKUP4 P3.4 INT7
Wakeup Line External Interrupt Data Carrier Detect
P3.5
WKUP5 ports useable INT7 general pur55 pose (input, output bidirectional) WKUP6 INT7 (**) WKUP7
Wakeup Line External Interrupt Data Input
Wakeup Line External Interrupt Ext. Mem. Address Strobe Wakeup Line External Interrupt Synchronous Data Send Ext. Mem. Request Ext. Mem. Wait Input Ext. Mem. Read/Write Mode Select
P3.6
P3.7
INT7
P4.0 P4.1
BREQ WAIT
P4.2
(**)
Ext. Mem. Address Strobe
P4.3
BACK
Ext. Mem. acknow
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ST92163 GENERAL DESCRIPTION
Port Name
QFP64
DIP56
General Purpose
Alternate Functions
INT1 P5.0 TINA
External Interrupt Timer Input
INT4 P5.1 TINB
External Interrupt Timer Input
P5.2 P5.3
INT3 INT2 TOUTA WKUP8 USBOE WDIN
External Interrupt External Interrupt Timer Output Wakeup Line Output enable Watchdog Timer Input External Interrupt Ext. Mem. Read/Write Mode Select Wakeup Line Timer Output Maskable Interrupt Watchdog Timer Output Wakeup Line External Interrupt Data Data Wakeup Line External Interrupt Clock External Trigger Clock Analog Input Wakeup Line Internal Clock Wakeup Line Analog Input Clock Output (same frequency external crystal)
P5.4
P5.5
INT0
P5.6
P5.7
WKUP9 ports useable TOUTB general purpose (input, output bidirec- WDOUT tional) WKUP10 INT5 SDAI SDAO WKUP11 INT6
P6.0
P6.1
SCLI EXTRG SCLO AIN0
P6.2
WKUP12 INTCLK WKUP13
P6.3
AIN1 XTOUT
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ST92163 GENERAL DESCRIPTION
Port Name
QFP64
DIP56
General Purpose
Alternate Functions
P6.4 P6.5
AIN2 USBSOF
Analog Input Synchro Analog Input Synchro Analog Input
P6.6
ports useable AIN3 general purUSBSOF pose (input, AIN4 output bidirec- tional) AIN5
P6.7
Analog Input
*Eight interrupt lines internally connected INT7 through boolean function. cannot disabled software ASAF (Page Register 245) once corresponding P3.6 configured Alternate Function output.
***Eight wakeup lines internally connected WKUP14 through boolean function. Note: reset state Port Port Input, Weak Pull-Up. interface external memory, ports must configured software alternate function output.
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ST92163 GENERAL DESCRIPTION
configure ports configure ports, information Table Table Port Configuration Table Ports Chapter page 101. Note hardware characteristics fixed each port line. Inputs: note TTL/CMOS, either CMOS input level selected software. note Schmitt trigger, selecting CMOS input software effect, input will always Schmitt Trigger. Outputs: note Push-Pull, either Push Pull Open Drain selected software. note Open Drain, selecting Push-Pull software effect, input will always Open Drain. Alternate Functions (AF) More than cannot assigned external same time: selected follows, simultaneous availability several functions obviously impossible. Inputs: selected implicitly enabling corresponding peripheral. Exceptions this
inputs which selected explicitly software. Outputs Bidirectional Lines: case Outputs I/Os, selected explicitly software. Example Timer/Watchdog input WDIN, Port: P5.5, note: Input Schmitt Trigger. Write port configuration bits: P5C2.5=1 P5C1.5=0 P5C0.5=1 Enable peripheral software described chapter. Example Timer/Watchdog output WDOUT, Port: P5.7, note: None Write port configuration bits: P5C2.7=0 P5C1.7=1 P5C0.7=1 Example input AIN0, Port: P6.2, note: Does apply Write port configuration bits: P6C2.2=1 P6C1.2=1 P6C0.2=1
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ST92163 GENERAL DESCRIPTION
MEMORY Figure ST92163 Memory
3FFFFFh
External Memory
Upper Memory (usually external mapped Segment 23h)
220000h 21FFFFh
SEGMENT Kbytes
Reserved
Internal Kbytes
20FFFFh
210000h 20FFFFh
PAGE Kbytes
20C000h 20BFFFh
20F800h
PAGE Kbytes SEGMENT Kbytes
208000h 207FFFh
PAGE Kbytes
204000h 203FFFh
Note: Internal addresses repeated each Kbytes inside segment 20h.
PAGE Kbytes
200000h 1FFFFFh
External Memory
Lower Memory (usually external ROM/EPROM mapped Segment
010000h 00FFFFh 00C000h 00BFFFh 008000h 007FFFh
PAGE Kbytes PAGE Kbytes PAGE Kbytes SEGMENT Kbytes
Reserved
Internal ROM/EPROM Kbytes
004FFFh
Internal ROM/EPROM
000000h
004000h 003FFFh 000000h
PAGE Kbytes
Note: total amount external memory Kbytes.
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ST92163 GENERAL DESCRIPTION
ST92163 REGISTER Table contains group peripheral pages. common registers used each peripheral listed Table very careful correctly program both: registers dedicated particular function peripheral. Table Common Registers
Function Peripheral SCI, PORTS EXTERNAL INTERRUPT RCCU
Registers common other functions. particular, double-check that registers with "undefined" reset values have been correctly initialized. Warning: Note that EIVR each register, bits significant. Take care when defining base vector addresses that entries Interrupt Vector table overlap.
Common Registers CICR NICR REGISTERS PORT REGISTERS CICR NICR PORT REGISTERS CICR NICR EXTERNAL INTERRUPT REGISTERS PORT REGISTERS PORT REGISTERS MODER INTERRUPT REGISTERS PORT REGISTERS INTERRUPT REGISTERS MODER
Figure ST92163 Register Groups
REGISTER FILE PAGED REGISTERS SYSTEM REGISTERS
These register groups registers group) potentially reserved DMA. amount reserved registers depends number endpoints used program. registers used endpoint).
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ST92163 GENERAL DESCRIPTION
Table Group Pages Register Resources available ST92163 device:
Page Register R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 Res. R245 R244 Res. R243 R242 R241 Res. R240 Port Res. RCCU Port Res. Res. Common Port Res. Port Res. Res. Res. Port Port Res.
Endpoints
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ST92163 GENERAL DESCRIPTION
Table Detailed Register
Page Block Port Reg. R227 R228 R229 R230 R231 R232 System Core R233 R234 R235 R236 R237 R238 R239 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 Port Port Port Port R252 R253 R254 R240 R241 R242 R244 R245 R246 R248 R249 R250 R251 Register Name P3DR P4DR P5DR CICR FLAGR MODER USPHR USPLR SSPHR SSPLR EITR EIPR EIMR EIPLR EIVR NICR WDTHR WDTLR WDTPR WDTCR P3C0 P3C1 P3C2 P4C0 P4C1 P4C2 P5C0 P5C1 P5C2 P6C0 P6C1 P6C2 P6DR Description Port Data Register Port Data Register Port Data Register Central Interrupt Control Register Flag Register Pointer Register Pointer Register Page Pointer Register Mode Register User Stack Pointer High Register User Stack Pointer Register System Stack Pointer High Reg. System Stack Pointer Reg. External Interrupt Trigger Register External Interrupt Pending Reg. External Interrupt Mask-bit Reg. External Interrupt Priority Level Reg. External Interrupt Vector Register Nested Interrupt Control Watchdog Timer High Register Watchdog Timer Register Watchdog Timer Prescaler Reg. Watchdog Timer Control Register Wait Control Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Configuration Register Port Data Register Reset Value Hex. Doc. Page
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ST92163 GENERAL DESCRIPTION
Page
Block
Reg. R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R240 R241
Register Name EP0RA EP0RB EP1RA EP1RB EP2RA EP2RB EP3RA EP3RB EP4RA EP4RB EP5RA EP5RB EP6RA EP6RB EP7RA EP7RB EP8RA EP8RB EP9RA EP9RB EP10RA EP10RB EP11RA EP11RB EP12RA EP12RB EP13RA EP13RB EP14RA EP14RB EP15RA EP15RB DCPR DAPR T_IVR IDCR IOCR
Description Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Endpoint Register (Transmission) Endpoint Register (Reception) Counter Pointer Register Address Pointer Register Interrupt Vector Register Interrupt/DMA Control Register Connection Register
Reset Value Hex.
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Points
R242 R243 R248
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Page
Block
Reg. R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R240 R241 R242 R243 R244 R245 R246
Register Name REG0HR REG0LR REG1HR REG1LR CMP0HR CMP0LR CMP1HR CMP1LR T_ICR PRSR OACR OBCR T_FLAGR IDMR DADDR0 DADDR1 DADDR2 DADDR3 DADDR4 DADDR5 DADDR6 DADDR7 USBIVR USBISTR USBIMR USBIPR USBCTLR CTRINF FNRH FNRL
Description Capture Load Register High Capture Load Register Capture Load Register High Capture Load Register Compare Register High Compare Register Compare Register High Compare Register Timer Control Register Timer Mode Register External Input Control Register Prescaler Register Output Control Register Output Control Register Flags Register Interrupt/DMA Mask Register Device Address Register Device Address Register Device Address Register Device Address Register Device Address Register Device Address Register Device Address Register Device Address Register Interrupt Vector Register Interrupt Status Register Interrupt Mask Register Interrupt Priority Register Control Register Interrrupt Flags Frame Number Register High Frame Number Register
Reset Value Hex.
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Common
R247 R248 R249 R250 R251 R252 R253 R254 R255
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Page
Block
Reg. R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R240 R241 R242
Register Name I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR I2CADR I2CISR I2CIVR I2CRDAP I2CRDC I2CTDAP I2CTDC I2CECCR I2CIMR DPR0 DPR1 DPR2 DPR3 DMASR EMR1 EMR2 RDCPR RDAPR TDCPR TDAPR S_IVR S_ISR RXBR TXBR IDPR CHCR BRGHR BRGLR SICR SOCR
Description Control Register Status Register Status Register Clock Control Register Address Register Address Register Data Register General Call Address Interrupt Status Register Interrupt Vector Register Receiver Source Addr. Pointer Receiver Transaction Counter Transmitter Source Addr. Pointer Transmitter Transaction Counter Extended Clock Control Register Interrupt Mask Register Data Page Register Data Page Register Data Page Register Data Page Register Code Segment Register Interrupt Segment Register Segment Register External Memory Register External Memory Register Receiver Transaction Counter Pointer Receiver Source Address Pointer Transmitter Transaction Counter Pointer Transmitter Destination Address Pointer Interrupt Vector Register Address/Data Compare Register Interrupt Mask Register Interrupt Status Register Receive Buffer Register Transmitter Buffer Register Interrupt/DMA Priority Register Character Configuration Register Clock Configuration Register Baud Rate Generator High Reg. Baud Rate Generator Register Synchronous Input Control Synchronous Output Control
Reset Value Hex.
Doc. Page
R243 R244 R248 R249 R245 R246 R240 R241 R242 R243 R244 R245 R246 R247
EXTMI
R248 R248 R249 R250 R251 R252 R253 R254 R255
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Page
Block
Reg. R248 R249 R250 R251 R252 R253 R254 R255 R240
Register Name P8C0 P8C1 P8C2 P8DR P9C0 P9C1 P9C2 P9DR CLKCTL CLK_FLAG PLLCONF WUCTRL WUMRH WUMRL WUTRH WUTRL WUPRH WUPRL DEVCONF1 DEVCONF2 MIRRA MIRRB ADDTR ADCLR ADINT
Description Port Configuration Register Port Configuration Register Port Configuration Register Port Data Register Port Configuration Register Port Configuration Register Port Configuration Register Port Data Register Clock Control Register Clock Flag Register Configuration Register Wake-Up Control Register Wake-Up Mask Register High Wake-Up Mask Register Wake-Up Trigger Register High Wake-Up Trigger Register Wake-Up Pending Register High Wake-Up Pending Register device configuration device configuration Mirror Register Mirror Register Channel Data Register Control Logic Register Interrupt Register
Reset Value Hex.
Doc. Page
Port Port
RCCU
R242 R246 R249 R250 R251
WUIMU
R252 R253 R254 R255 R244 R245 R246 R247 R240
R241 R242
Note: denotes byte with undefined value, some bits have defined values. register description details.
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DEVICE ARCHITECTURE
CORE ARCHITECTURE which hold data control bits on-chip peripherals I/Os. single linear memory space accommodating both program data. physically separate memory areas, including internal ROM, internal external memory mapped this common address space. total addressable memory space Mbytes (limited size on-chip memory number external address pins) arranged segments Kbytes. Each segment further subdivided into four pages Kbytes, illustrated Figure Memory Management Unit uses pointer registers address 22-bit memory field using 16-bit address-based instructions. 2.2.1 Register File Register File consists (see Figure MEMORY SPACES general purpose registers (Group There separate memory spaces: registers R223) Register File, which comprises 8-bit system registers System Group (Group registers, arranged groups (Group registers R224 R239) each containing sixteen 8-bit registers plus pages, depending device configura64 pages registers mapped Group tion, each containing registers, mapped Group (R240 R255), Figure Figure Single Program Data Memory Address Space
Address
3FFFFFh 3F0000h 3EFFFFh 3E0000h
Core Central Processing Unit (CPU) features highly optimised instruction set, capable handling bit, byte (8-bit) word (16-bit) data, well Boolean formats; addressing modes available. Four independent buses controlled Core: 16-bit Memory bus, 8-bit Register data bus, 8-bit Register address 6-bit Interrupt/DMA which connects interrupt controllers on-chip peripherals with Core. This multiple architecture affords high degree pipelining parallel operation, thus making family devices highly efficient, both numerical calculation, data handling with regard communication with on-chip peripheral resources.
Data Pages
Code Segments
Mbytes
21FFFFh 210000h 20FFFFh
Reserved
02FFFFh 020000h 01FFFFh 010000h 00FFFFh 000000h
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MEMORY SPACES (Cont'd) Figure Register Groups
PAGES
Figure Page Pointer Group mapping
PAGE
PAGED REGISTERS SYSTEM REGISTERS
PAGE R255 PAGE
R240 R234 GENERAL PURPOSE REGISTERS R224 PAGE POINTER
VA00432
VA00433
Figure Addressing Register File
REGISTER FILE PAGED REGISTERS SYSTEM REGISTERS
VR000118
GROUP R195 (R0C3h) R207
(1100) (0011) GROUP
R195 R192 GROUP
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MEMORY SPACES (Cont'd) 2.2.2 Register Addressing Register File registers, including Group paged registers (but excluding Group addressed explicitly means decimal, hexadecimal binary address; thus R231, RE7h R11100111b represent same register (see Figure Group registers only addressed Working Register mode. Note that upper case used denote this direct addressing mode. Working Registers Certain types instruction require that registers specified form "rx", where range these known Working Registers. Note that lower case used denote this indirect addressing mode. addressing schemes available: single group working registers, separately mapped groups, each consisting working registers. These groups mapped starting byte boundary register file means dedicated pointer registers. This technique described more detail Section 1.3.3, illustrated Figure Figure System Registers registers Group (R224 R239) System registers addressed using register addressing modes. These registers described greater detail Section 1.3. Paged Registers pages, each containing registers, mapped Group These addressed using register addressing mode, conjunction with Page Pointer register, R234, which System registers. This register selects page mapped Group and, once set, does need changed more registers same page addressed succession.
Therefore Page Pointer, R234, instructions: R242, will load contents working register into third register page (R242). These paged registers hold data control information relating on-chip peripherals, each peripheral always being associated with same pages registers ensure code compatibility between devices. number these registers therefore depends peripherals which present specific family device. other words, pages only exist relevant peripheral present. Table Register File Organization
Hex. Address F0-FF E0-EF D0-DF C0-CF B0-BF A0-AF 90-9F 80-8F 70-7F 60-6F 50-5F 40-4F 30-3F 20-2F 10-1F 00-0F Decimal Address 240-255 224-239 208-223 192-207 176-191 160-175 144-159 128-143 112-127 96-111 80-95 64-79 48-63 32-47 16-31 00-15 General Purpose Registers Function Paged Registers System Registers Register File Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group Group
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SYSTEM REGISTERS System registers listed Table System Registers (Group They used perform important system settings. Their purpose described following pages. Refer chapter dealing with description PORT[5:0] Data registers. Table System Registers (Group
R239 (EFh) R238 (EEh) R237 (EDh) R236 (ECh) R235 (EBh) R234 (EAh) R233 (E9h) R232 (E8h) R231 (E7h) R230 (E6h) R229 (E5h) R228 (E4h) R227 (E3h) R226 (E2h) R225 (E1h) R224 (E0h) SSPLR SSPHR USPLR USPHR MODE REGISTER PAGE POINTER REGISTER REGISTER POINTER REGISTER POINTER FLAG REGISTER CENTRAL INT. CNTL PORT5 DATA REG. PORT4 DATA REG. PORT3 DATA REG. PORT2 DATA REG. PORT1 DATA REG. PORT0 DATA REG.
Note: included device, then this effect. TLIP: Level Interrupt Pending. This hardware when Level Interrupt Request recognized. This also software simulate Level Interrupt Request. Level Interrupt pending Level Interrupt pending TLI: Level Interrupt bit. Level Interrupt acknowledged depending TLNM NICR Register. Level Interrupt acknowledged depending TLNM bits NICR Register (described Interrupt chapter). IEN: Interrupt Enable This cleared interrupt acknowledgement, interrupt return (iret). modified implicitly iret, instructions interrupt acknowledge cycle. also explicitly written user, only when interrupt pending. Therefore, user should execute instruction guarantee other means that interrupt request arrive) before write operation CICR register. Disable interrupts except Level Interrupt. Enable Interrupts IAM: Interrupt Arbitration Mode. This cleared software select arbitration mode. Concurrent Mode Nested Mode. Bits CPL[2:0]: Current Priority Level. These three bits record priority level routine currently running (i.e. Current Priority Level, CPL). highest priority level represented 000, lowest 111. bits hardware software provide reference according which subsequent interrupts either left pending allowed interrupt current interrupt service routine. When current interrupt replaced higher priority, current priority value automatically stored until required NICR register.
2.3.1 Central Interrupt Control Register Please refer "INTERRUPT" chapter detailed description interrupt philosophy. CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 Read/Write Register Group: (System) Reset Value: 1000 0111 (87h)
GCEN TLIP CPL2 CPL1 CPL0
GCEN: Global Counter Enable. This Global Counter Enable Multifunction Timers. GCEN ANDed with Register (only devices featuring Multifunction Timer) order enable Timers when both bits set. This after Reset cycle.
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SYSTEM REGISTERS (Cont'd) 2.3.2 Flag Register Flag Register contains flags which indicate status. During interrupt, flag register automatically stored system stack area recalled interrupt service routine, thus returning original status. This occurs interrupts and, when operating nested mode, seven versions flag register stored. FLAG REGISTER (FLAGR) R231- Read/Write Register Group: (System) Reset value: 0000 0000 (00h)
decw), Test (tm, tmw, tcm, tcmw, btset). most cases, Zero flag when contents register being used accumulator become zero, following above operations. Sign Flag. Sign flag affected same instructions Zero flag. Sign flag when (for byte operation) (for word operation) register used accumulator one. Overflow Flag Overflow flag affected same instructions Zero Sign flags. When set, Overflow flag indicates that two'scomplement number, result register, error, since exceeded largest less than smallest), number that represented two's-complement notation. Decimal Adjust Flag. flag used arithmetic. Since algorithm correcting operations different addition subtraction, this flag used specify which type instruction executed last, that subsequent Decimal Adjust (da) operation perform function correctly. flag cannot normally used test condition programmer. Half Carry Flag. flag indicates carry borrow into) result adding subtracting 8-bit bytes, each representing digits. flag used Decimal Adjust (da) instruction convert binary result previous addition subtraction into correct result. Like flag, this flag normally accessed user. Reserved (must Data/Program Memory Flag This indicates memory area addressed. value affected Data Memory (sdm) Program Memory (spm) instructions. Refer Memory Management Unit further details.
Carry Flag carry flag affected Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply Divide (mul, div, divws). When set, generally indicates carry most significant position register being used accumulator (bit byte operations word operations). carry flag Carry Flag (scf) instruction, cleared Reset Carry Flag (rcf) instruction, complemented Complement Carry Flag (ccf) instruction. Zero Flag. Zero flag affected Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply Divide (mul, div, divws), Logical (and, andw, orw, xor, xorw, cpl), Increment Decrement (inc, incw, dec,
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SYSTEM REGISTERS (Cont'd) set, data accessed using Data Pointers (DPRs registers), otherwise pointed Code Pointer (CSR register); therefore, user initialization routine must include instruction. Note that code always pointed Code Pointer (CSR). Note: current devices, flag only compatibility with software developed first generation devices. With single memory addressing space, redundant. must kept with instruction beginning program ensure normal different memory pointers. 2.3.3 Register Pointing Techniques registers within System register group, used pointers working registers. Register Pointer (R232) used single pointer 16-register working space, conjunction with Register Pointer (R233), point separate 8-register spaces. purpose register pointing, register groups register file subdivided into 8register blocks. values specified with Register Pointer instructions refer blocks pointed twin 8-register mode, lower 8-register block location single 16-register mode. Register Pointer instructions srp, srp0 srp1 automatically inform whether Register File operate single 16-register mode twin 8-register mode. instruction selects single 16-register group mode
specifies location lower 8-register block, while srp0 srp1 instructions automatically select twin 8-register group mode specify locations each 8-register block. There limitation order position these register groups, other than that they must start 8-register boundary twin 8-register mode, 16-register boundary single 16register mode. block number should always even number single 16-register mode. 16-register group will always start block whose number nearest even number equal lower than block number specified instruction. Avoid using block numbers, since this confusing twin mode subsequently selected. Thus: will interpreted will allow using .R31 r15. single 16-register mode, working registers referred r15. twin 8-register mode, registers block pointed means srp0 instruction), while registers block pointed means srp1 instruction). Caution: Group registers only accessed working registers using Register Pointers, means Stack Pointers. They cannot addressed explicitly form "Rxxx".
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ST92163 DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont'd) POINTER REGISTER (RP0) R232 Read/Write Register Group: (System) Reset Value: xxxx xx00 (xxh)
POINTER REGISTER (RP1) R233 Read/Write Register Group: (System) Reset Value: xxxx xx00 (xxh)
Bits RG[4:0]: Register Group number. These bits contain number range register block specified srp0 instructions. single 16-register mode number indicates lower 8-register blocks which working registers mapped, while twin 8-register mode indicates 8-register block which mapped. RPS: Register Pointer Selector. This instructions srp0 srp1 indicate that twin register pointing mode selected. reset instruction indicate that single register pointing mode selected. Single register pointing mode Twin register pointing mode Bits 1:0: Reserved. Forced hardware zero.
This register only used twin register pointing mode. When using single register pointing mode, when using only twin register groups, register must considered RESERVED used general purpose register. Bits RG[4:0]: Register Group number. These bits contain number range 8-register block specified srp1 instruction, which mapped. RPS: Register Pointer Selector. This srp0 srp1 instructions indicate that twin register pointing mode selected. reset instruction indicate that single register pointing mode selected. Single register pointing mode Twin register pointing mode Bits 1:0: Reserved. Forced hardware zero.
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SYSTEM REGISTERS (Cont'd) Figure Pointing single group registers
REGISTER GROUP REGISTER FILE
Figure Pointing groups registers
REGISTER GROUP REGISTER FILE
BLOCK NUMBER
BLOCK NUMBER
points addressed BLOCK addressed BLOCK GROUP REGISTER POINTER
REGISTER POINTER REGISTER POINTER
instruction
srp0
srp1
instructions point
GROUP
GROUP addressed BLOCK
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SYSTEM REGISTERS (Cont'd) 2.3.4 Paged Registers pages, each containing registers, mapped Group These paged registers hold data control information relating on-chip peripherals, each peripheral always being associated with same pages registers ensure code compatibility between devices. number these registers depends peripherals present specific device. other words, pages only exist relevant peripheral present. paged registers addressed using normal register addressing modes, conjunction with Page Pointer register, R234, which System registers. This register selects page mapped Group and, once set, does need changed more registers same page addressed succession. Thus instructions: R242, will load contents working register into third register page (R242). Warning: During interrupt, register saved automatically stack. needed, should saved/restored user within interrupt routine. PAGE POINTER REGISTER (PPR) R234 Read/Write Register Group: (System) Reset value: xxxx xx00 (xxh)
Management clock frequency, Enabling request Wait signals when interfacing external memory. MODE REGISTER (MODER) R235 Read/Write Register Group: (System) Reset value: 1110 0000 (E0h)
DIV2 PRS2 PRS1
PRS0 BRQEN HIMP
SSP: System Stack Pointer. This selects internal external System Stack area. External system stack area, memory space. Internal system stack area, Register File (reset state). USP: User Stack Pointer. This selects internal external User Stack area. External user stack area, memory space. Internal user stack area, Register File (reset state). DIV2: Crystal Oscillator Clock Divided This controls divide-by-2 circuit operating crystal oscillator clock (CLOCK1). Clock divided Clock divided Bits PRS[2:0]: CPUCLK Prescaler. These bits load prescaler division factor internal clock (INTCLK). prescaler factor selects internal clock frequency, which divided factor from Refer Reset Clock Control chapter further information. BRQEN: Request Enable. External Memory Request disabled External Memory Request enabled BREQ (where available). Note: Disregard this BREQ available. HIMP: High Impedance Enable. When Ports depending device configuration, programmed Address Data lines interface external Memory, these lines Memory interface control lines (AS, R/W) forced into High Impedance
Bits PP[5:0]: Page Pointer. These bits contain number range page specified instruction. Once page pointer been set, there need refresh unless different page required. Bits 1:0: Reserved. Forced hardware 2.3.5 Mode Register Mode Register allows control following operating parameters: Selection internal external System User Stack areas,
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SYSTEM REGISTERS (Cont'd) state setting HIMP bit. When this reset, effect. Setting HIMP recommended noise reduction when only internal Memory used. Port and/or declared address port (for example: P10. Address, P15. I/O), HIMP effect lines. 2.3.6 Stack Pointers separate, double-register stack pointers available: System Stack Pointer User Stack Pointer, both which address registers memory. stack pointers point "bottom" stacks which filled using push commands emptied using commands. stack pointer automatically pre-decremented when data "pushed" post-incremented when data "popped" out. push commands used manage System Stack addressed User Stack adding suffix "u". stack instruction word, suffix added. These suffixes combined. When bytes words) "popped" from stack, contents stack locations unchanged until fresh data loaded. Thus, when data "popped" from stack area, stack contents remain unchanged. Note: Instructions such pushuw RR236 pushw RR238, well corresponding instructions (where R236 R237, R238 R239 themselves user system stack pointers respectively), must used, since pointer values themselves automatically changed push instruction, thus corrupting their value. System Stack System Stack used temporary storage system and/or control data, such Flag register Program counter. following automatically push data onto System Stack: Interrupts When entering interrupt, Flag Register pushed onto System Stack. ENCSR EMR2 register set, then
Code Segment Register also pushed onto System Stack. Subroutine Calls When call instruction executed, only pushed onto stack, whereas when calls instruction (call segment) executed, both Code Segment Register pushed onto System Stack. Link Instruction link linku instructions create language stack frame user-defined length System User Stack. above conditions associated with their counterparts, such return instructions, which stored data items stack. User Stack User Stack provides totally user-controlled stacking area. User Stack Pointer consists registers, R236 R237, which both used addressing stack memory. When stacking Register File, User Stack Pointer High Register, R236, becomes redundant must considered reserved. Stack Pointers Both System User stacks pointed double-byte stack pointers. Stacks Register File. Only lower byte will required stack Register File. upper byte must then considered reserved must used general purpose register. stack pointer registers located System Group Register File, this illustrated Table System Registers (Group Stack Location Care necessary when managing stacks there limit stack sizes apart from bottom address space which stack placed. Consequently programmers advised stack pointer value high possible, particularly when using Register File stacking area. Group good location stack Register File, since highest available area. stacks located anywhere first groups Register File (internal stacks) (external stacks). Note. Stacks must located Paged Register Group System Register Group.
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SYSTEM REGISTERS (Cont'd) USER STACK POINTER HIGH REGISTER (USPHR) R236 Read/Write Register Group: (System) Reset value: undefined
USP15 USP14 USP13 USP12 USP11 USP10 USP9 USP8
SYSTEM STACK POINTER HIGH REGISTER (SSPHR) R238 Read/Write Register Group: (System) Reset value: undefined
SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8
USER STACK POINTER REGISTER (USPLR) R237 Read/Write Register Group: (System) Reset value: undefined
USP7 USP6 USP5 USP4 USP3 USP2 USP1 USP0
SYSTEM STACK POINTER REGISTER (SSPLR) R239 Read/Write Register Group: (System) Reset value: undefined
SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Figure Internal Stack Mode
Figure External Stack Mode
REGISTER FILE STACK POINTER (LOW) points
REGISTER FILE
STACK POINTER (LOW) STACK POINTER (HIGH) point MEMORY
STACK
STACK
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MEMORY ORGANIZATION Code data accessed within same linear address space. physically separate memory areas, including internal ROM, internal external memory mapped common address space. provides total addressable memory space Mbytes. This address space arranged segments Kbytes; each segment again subdivided into four Kbyte pages. mapping various memory areas (internal ROM, external memory) differs from device device. Each 64-Kbyte physical memory segment mapped either internally externally; memory internal smaller than Kbytes, remaining locations 64-Kbyte segment used (reserved). Refer Register Memory Chapter more details memory map.
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MEMORY MANAGEMENT UNIT Core includes Memory Management Unit (MMU) which must programmed perform memory accesses (even external memory used). controlled registers bits (ENCSR DPRREM) present EMR2, which written read user program. These registers mapped within group Page Register File. registers Figure Page Registers sub-divided into main groups: first group four 8-bit registers (DPR[3:0]), second group three 6-bit registers (CSR, ISR, DMASR). first group used extend address during Data Memory access (DPR[3:0]). second used manage Program Data Memory accesses during Code execution (CSR), Interrupts Service Routines (ISR CSR), transfers (DMASR ISR).
Page EMR2 EMR1 DPR3 DPR2 DPR1 DPR0 DMASR R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240 SSPLR SSPHR USPLR USPHR MODER FLAGR CICR P5DR P4DR P3DR P2DR P1DR P0DR SSPLR SSPHR USPLR USPHR MODER FLAGR CICR P5DR P4DR DPR3 DPR2 DPR1 DPR0
Relocation P[3:0] DPR[3:0] Registers
DMASR EMR2 EMR1 DPR3 DPR2 DPR0
DMASR EMR2 EMR1 P3DR P2DR P1DR P0DR
DPRREM=0 (default setting)
DPRREM=1
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ADDRESS SPACE EXTENSION manage Mbytes addressing space, necessary have address bits. adds bits usual 16-bit address, thus translating 16-bit virtual address into 22-bit physical address. There different ways this depending memory involved operation being performed. 2.6.1 Addressing 16-Kbyte Pages This extension mode implicitly used address Data memory space being performed. Data memory space divided into pages Kbytes. Each four 8-bit registers (DPR[3:0], Data Page Registers) selects different 16-Kbyte page. registers allow access entire memory space which contains pages Kbytes. Data paging performed extending 16-bit address with contents register. MSBs 16-bit address interpreted identification number register used. Therefore, registers Figure Addressing DPR[3:0] involved following virtual address ranges: DPR0: from 0000h 3FFFh; DPR1: from 4000h 7FFFh; DPR2: from 8000h BFFFh; DPR3: from C000h FFFFh. contents selected register specify possible data memory pages. This 8-bit data page number, addition remaining 14-bit page offset address forms physical 22-bit address (see Figure 10). register cannot modified addressing mode that uses same register. instance, instruction "POPW DPR0" legal only stack kept either register file memory location above 8000h, where DPR2 DPR3 used. Otherwise, since DPR0 DPR1 modified instruction, unpredictable behaviour could result.
registers DPR0 DPR1 DPR2 DPR3
16-bit virtual address
bits
22-bit physical address
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ADDRESS SPACE EXTENSION (Cont'd) 2.6.2 Addressing 64-Kbyte Segments This extension mode used address Data memory space during Program memory space during code execution (normal code interrupt routines). Three registers used: CSR, ISR, DMASR. 6-bit contents registers CSR, ISR, DMASR define Memory segments Kbytes within Mbytes address space. register contents represent MSBs memory address, whereas LSBs address (intra-segment address) given virtual 16-bit address (see Figure 11). REGISTERS uses registers mapped into Group Page Register File bits EMR2 register.
Most these registers have default value after reset. 2.7.1 DPR[3:0]: Data Page Registers DPR[3:0] registers allow access entire Mbyte memory space composed pages Kbytes. 2.7.1.1 Data Page Register Relocation these registers used frequently, they relocated register group programming EMR2-R246 register page this set, DPR[3:0] registers located R224-227 place Port Data Registers, which re-mapped default DPR's locations: R240-243 page Data Page Register relocation illustrated Figure
Figure Addressing CSR, ISR, DMASR
registers DMASR
16-bit virtual address
Fetching program instruction Data Memory accessed Fetching interrupt instruction access Program Memory
bits
22-bit physical address
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ST92163 DEVICE ARCHITECTURE
REGISTERS (Cont'd) DATA PAGE REGISTER (DPR0) R240 Read/Write Register Page: Reset value: undefined This register relocated R224 EMR2.5 set.
DATA PAGE REGISTER (DPR2) R242 Read/Write Register Page: Reset value: undefined This register relocated R226 EMR2.5 set.
DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0
DPR2_7 DPR2_6 DPR2_5 DPR2_4 DPR2_3 DPR2_2 DPR2_1 DPR2_0
Bits DPR0_[7:0]: These bits define 16Kbyte Data Memory page number. They used most significant address bits (A21-14) extend address during Data Memory access. DPR0 register used when addressing virtual address range 0000h-3FFFh. DATA PAGE REGISTER (DPR1) R241 Read/Write Register Page: Reset value: undefined This register relocated R225 EMR2.5 set.
Bits DPR2_[7:0]: These bits define 16Kbyte Data memory page. They used most significant address bits (A21-14) extend address during Data memory access. DPR2 register involved when virtual address range 8000h-BFFFh. DATA PAGE REGISTER (DPR3) R243 Read/Write Register Page: Reset value: undefined This register relocated R227 EMR2.5 set.
DPR1_7 DPR1_6 DPR1_5 DPR1_4 DPR1_3 DPR1_2 DPR1_1 DPR1_0
DPR3_7 DPR3_6 DPR3_5 DPR3_4 DPR3_3 DPR3_2 DPR3_1 DPR3_0
Bits DPR1_[7:0]: These bits define 16Kbyte Data Memory page number. They used most significant address bits (A21-14) extend address during Data Memory access. DPR1 register used when addressing virtual address range 4000h-7FFFh.
Bits DPR3_[7:0]: These bits define 16Kbyte Data memory page. They used most significant address bits (A21-14) extend address during Data memory access. DPR3 register involved when virtual address range C000h-FFFFh.
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REGISTERS (Cont'd) 2.7.2 CSR: Code Segment Register This register selects 64-Kbyte code segment being used run-time access instructions. also used access data instruction been executed ldpp, ldpd, lddp). Only LSBs register implemented, bits reserved. register allows access entire memory space, divided into segments Kbytes. generate 22-bit Program memory address, contents register directly used MSBs, 16-bit virtual address LSBs. Note: register should only read written data operations (there some exceptions which documented following paragraph). however, modified either directly means calls instructions, indirectly stack, means rets instruction. CODE SEGMENT REGISTER (CSR) R244 Read/Write Register Page: Reset value: 0000 0000 (00h)
CSR_5 CSR_4 CSR_3 CSR_2 CSR_1 CSR_0
ENCSR (EMR2 register) also described chapter relating Interrupts, please refer this description further details. Bits Reserved, keep reset state. Bits ISR_[5:0]: These bits define 64Kbyte memory segment (among which contains interrupt vector table code interrupt service routines transfers (when DAPR register reset). These bits used most significant address bits (A21-16). used extend address space cases: Whenever interrupt occurs: points 64-Kbyte memory segment containing interrupt vector table interrupt service routine code. also Interrupts chapter. During transactions between peripheral memory when DAPR register reset points K-byte Memory segment that will involved transaction. 2.7.4 DMASR: Segment Register SEGMENT REGISTER (DMASR) R249 Read/Write Register Page: Reset value: undefined
SR_5 SR_4 SR_3 SR_2 SR_1 SR_0
Bits Reserved, keep reset state. Bits CSR_[5:0]: These bits define 64Kbyte memory segment (among which contains code being executed. These bits used most significant address bits (A21-16). 2.7.3 ISR: Interrupt Segment Register INTERRUPT SEGMENT REGISTER (ISR) R248 Read/Write Register Page: Reset value: undefined
ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0
Bits Reserved, keep reset state. Bits DMASR_[5:0]: These bits define 64Kbyte Memory segment (among used when transaction performed between peripheral's data register Memory, with DAPR register set. These bits used most significant address bits (A21-16). reset, register used extend address.
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REGISTERS (Cont'd) Figure Memory Addressing Scheme (example)
bytes
3FFFFFh
294000h
DPR3 DPR2 DPR1 DPR0 20C000h 200000h 1FFFFFh 240000h 23FFFFh
DMASR
040000h 03FFFFh 030000h 020000h
010000h 00C000h 000000h
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USAGE 2.8.1 Normal Program Execution Program memory organized 64Kbyte segments. program span many segments needed, procedure cannot stretch across segment boundaries. jps, calls rets instructions, which automatically modify CSR, must used jump across segment boundaries. Writing forbidden during normal program execution because synchronized with opcode fetch. This could result fetching first byte instruction from memory segment second byte from another. Writing allowed when being used, during interrupt service routine ENCSR reset. Note that routine must always called same way, i.e. either always with call always with calls, depending whether routine ends with rets. This means that routine written without prior knowledge location other routines which call program code does into single 64-Kbyte segment, then calls/rets should used. typical microcontroller applications, less than Kbytes used, four Data space pages normally sufficient, change DPR[3:0] needed during Program execution. useful however part into data space contains strings, tables, maps, etc. there frequent paging, user (DPRREM) register R246 (EMR2) Page This swaps location registers DPR[3:0] with that data registers Ports this way, registers accessed without need save/set/restore Page Pointer Register. Port registers therefore moved page Applications that require paging typically more than Kbytes external memory, ports required address their data registers unused. 2.8.2 Interrupts register been created that interrupt routines found means same vector table even after segment jump/call. When interrupt occurs, behaves ways, depending value ENCSR EMR2 register (R246 Page 21). this reset (default condition), works original compatibility mode. duration interrupt service routine, used instead CSR, interrupt stack frame kept exactly original (only flags pushed). This avoids need save stack case interrupt, ensuring fast interrupt response time. drawback that possible interrupt service routine perform segment calls/jps: these instructions would update CSR, which, this case, used (ISR used instead). code size interrupt service routines thus limited Kbytes. instead, EMR2 register set, used only point interrupt vector table initialize beginning interrupt service routine: pushed onto stack together with flags, then loaded with ISR. this case, iret will also restore from stack. This approach lets interrupt service routines access whole 4-Mbyte address space. drawback that interrupt response time slightly increased, because need also save stack. Compatibility with original also lost this case, because interrupt stack frame different; this difference, however, would noticeable vast majority programs. Data memory mapping independent value EMR2 register, remains same normal code execution: stack same that used main program, ST9. interrupt service routine needs access additional Data memory, must save more) DPRs, load with needed memory page restore before completion. 2.8.3 Depending DAPR register (see chapter) uses either DMASR memory accesses: this guarantees that will always find memory segment(s), matter what segment changes application performed. Unlike interrupts, transactions cannot save/restore paging registers, dedicated segment register (DMASR) been created. Having only register this kind means that accesses should programmed following segments: pointed (when DAPR register reset), referenced DMASR (when set).
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INTERRUPTS
INTRODUCTION responds peripheral external events through interrupt channels. Current program execution suspended allow execute specific response routine when such event occurs, providing that interrupts have been enabled, according priority mechanism. event generates valid interrupt request, current program status saved control passes appropriate Interrupt Service Routine. receive requests from following sources: On-chip peripherals External pins Top-Level Pseudo-non-maskable interrupt According on-chip peripheral features, event occurrence generate Interrupt request which depends selected mode. eight external interrupt channels, with programmable input trigger edge, available. addition, dedicated interrupt channel, Top-level priority, devoted either external (where available) provide NonMaskable Interrupt, Timer/Watchdog. Interrupt service routines addressed through vector table mapped Memory. Figure Interrupt Response
NORMAL PROGRAM FLOW
INTERRUPT SERVICE ROUTINE
INTERRUPT
CLEAR PENDING
IRET INSTRUCTION
VR001833
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INTERRUPTS (Cont'd) INTERRUPT VECTORING implements interrupt vectoring structure which allows on-chip peripheral identify location first instruction Interrupt Service Routine automatically. When interrupt request acknowledged, peripheral interrupt module provides, through Interrupt Vector Register (IVR), vector point into vector table locations containing start addresses Interrupt Service Routines (defined programmer). Each peripheral specific mapped within Register File pages. Interrupt Vector table, containing addresses Interrupt Service Routines, located first locations Memory pointed register, thus allowing 8-bit vector addressing. description register refer chapter describing MMU. user Power Reset vector stored first physical bytes memory, 000000h 000001h. Level Interrupt vector located addresses 0004h 0005h segment pointed Interrupt Segment Register (ISR). With Interrupt Vector register, possible address several interrupt service routines; fact, peripherals share same interrupt vector register among several interrupt channels. most significant bits vector user programmable define base vector address within vector table, least significant bits controlled interrupt module, hardware, select appropriate vector. Note: first locations memory segment pointed contain program code. 3.2.1 Divide Zero trap Divide Zero trap vector located addresses 0002h 0003h each code segment; should noted that each code segment Divide Zero service routine required. Important. Although Divide Zero Trap operates interrupt, FLAG Register pushed onto system Stack automatically. result must regarded subroutine, service routine must with instruction (not IRET).
PROGRAM MEMORY USER USER DIVIDE-BY-ZERO USER MAIN PROGRAM INT. VECTOR REGISTER USER LEVEL R240 R239
Figure Interrupt Vector Table
REGISTER FILE PAGE REGISTERS
0000FFh EVEN 000004h 000002h 000000h LEVEL INT. DIVIDE-BY-ZERO POWER-ON RESET ADDRESS VECTOR TABLE
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INTERRUPTS (Cont'd) 3.2.2 Segment Paging During Interrupt Routines ENCSR EMR2 register used select between original backward compatibility mode ST9+ interrupt management mode. backward compatibility mode (ENCSR ENCSR reset, works original compatibility mode. duration interrupt service routine, used instead CSR, interrupt stack frame identical that original ST9: only Flags pushed. This avoids saving stack event interrupt, thus ensuring faster interrupt response time. possible interrupt service routine perform inter-segment calls jumps: these instructions would update CSR, which, this case, used (ISR used instead). code segment size interrupt service routines thus limited bytes. ST9+ mode (ENCSR ENCSR set, only used point interrupt vector table initialize beginning interrupt service routine: pushed onto stack together with flags, then loaded with contents ISR. this case, iret will also restore from stack. This approach allows interrupt service routines access entire Mbytes address space. drawback that interrupt response time slightly increased, because need also save stack. Full compatibility with original lost this case, because interrupt stack frame different.
ENCSR Mode Compatible ST9+ Pushed/Popped FLAGR, FLAGR Registers Max. Code Size 64KB interrupt Within segment Across segments service routine
INTERRUPT PRIORITY LEVELS supports fully programmable interrupt priority structure. Nine priority levels available define channel priority relationships: on-chip peripheral channels eight external interrupt sources programmed within eight priority levels. Each channel 3bit field, (Priority Level), that defines priority level range from (highest priority) (lowest priority). level (Top Level Priority) reserved Timer/Watchdog External Pseudo Non-Maskable Interrupt. Interrupt service routine this level cannot interrupted arbitration mode. mask both maskable (TLI) non-maskable (TLNM). PRIORITY LEVEL ARBITRATION bits (Current Priority Level) Central Interrupt Control Register contain priority currently running program (CPU priority). (lowest priority) upon reset modified during program execution either software automatically hardware according selected Arbitration Mode. During every instruction, arbitration phase takes place, during which, every channel capable generating Interrupt, each priority level compared other requests (interrupts DMA). highest priority request interrupt, value must strictly lower (that higher priority) than value stored CICR register (R230) order acknowledged. Level Interrupt overrides every other priority. 3.4.1 Priority Level (Lowest) Interrupt requests level cannot acknowledged, this value (the lowest possible priority) cannot strictly lower than value. This fully polled interrupt environment. 3.4.2 Maximum Depth Nesting more than routines nested. interrupt routine level being serviced, other Interrupts located level interrupt This guarantees maximum number nested levels including Level Interrupt request. 3.4.3 Simultaneous Interrupts more requests occur same time same priority level, on-chip daisy chain, specific every version, selects channel
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with highest position chain, shown Table Table Daisy Chain Priority
Highest Position INTA0 INTA1 INTB0 INTB1 INTC0 INTC1 INTD0 INTD1 INT0/WDT INT1/ADC INT2 INT3 INT4/ INT5 INT6/RCCU INT7/WKUP
Lowest Position
3.4.4 Dynamic Priority Level Modification main program routines specifically prioritized. Since represented bits read/write register, possible modify dynamically current priority value during program execution. This means that critical section have higher priority with respect other interrupt requests. Furthermore possible prioritize even Main Program execution modifying during execution. Figure Figure Example Dynamic priority level modification Nested Mode
INTERRUPT PRIORITY LEVEL Priority Level MAIN program INT6 MAIN CPL6 CPL5: INT6 pending
CPL=6 MAIN CPL=7
ARBITRATION MODES provides interrupt arbitration modes: Concurrent mode Nested mode. Concurrent mode standard interrupt arbitration mode. Nested mode improves effective interrupt response time when service routine nesting required, depending request priority levels.
control CICR Register selects Concurrent Arbitration mode Nested Arbitration Mode. 3.5.1 Concurrent Mode This mode selected when cleared (reset condition). arbitration phase, performed during every instruction, selects request with highest priority level. value modified this mode. Start Interrupt Routine interrupt cycle performs following steps: maskable interrupt requests disabled clearing CICR.IEN. byte pushed onto system stack. high byte pushed onto system stack. ENCSR set, pushed onto system stack. Flag register pushed onto system stack. loaded with 16-bit vector stored Vector Table, pointed IVR. ENCSR set, loaded with contents; otherwise used place until iret instruction. Interrupt Routine Interrupt Service Routine must ended with iret instruction. iret instruction executes following operations: Flag register popped from system stack. ENCSR set, popped from system stack. high byte popped from system stack. byte popped from system stack. unmasked Interrupts enabled setting CICR.IEN bit. ENCSR reset, used instead ISR. Normal program execution thus resumes interrupted instruction. pending interrupts remain pending until next instruction (even executed during interrupt service routine). Note: Concurrent mode, source priority level only useful during arbitration phase, where compared with other priority levels with CPL. trace kept value during ISR. other requests issued during interrupt service routine, once global CICR.IEN re-enabled, they will acknowledged regardless interrupt service routine's priority. This cause undesirable interrupt response sequences.
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ARBITRATION MODES (Cont'd) Examples following examples, three interrupt requests with different priority levels occur simultaneously during interrupt service routine.
Example first example, (simplest case, Figure instruction used within interrupt service routines. This means that interrupt serviced middle current one. interrupt routines will thus serviced after another, order their priority, until main program eventually resumes.
Figure Simple Example Sequence Interrupt Requests with: Concurrent mode selected unchanged interrupt routines
Priority Level Interrupt Request
INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL
MAIN MAIN
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ARBITRATION MODES (Cont'd) Example second example, (more complex, Figure 23), each interrupt service routine sets Interrupt Enable with instruction beginning routine. Placed here, minimizes response time requests with higher priority than being serviced. level interrupt routine (with highest priority) will acknowledged first, then, when instruction executed, will interrupted level interrupt routine, which itself will interrupted level interrupt routine. When level interrupt routine completed, level interrupt routine resumes finally level interrupt routine. This results three interrupt serv-
routines being executed opposite order their priority. therefore recommended avoid inserting instruction interrupt service routine Concurrent mode. instruction only nested mode. IMPORTANT: Concurrent Mode, interrupts nested executing interrupt service routine), make sure that either ENCSR CSR=ISR, otherwise iret innermost interrupt will make instead before outermost interrupt service routine terminated, thus making outermost routine fail.
Figure Complex Example Sequence Interrupt Requests with: Concurrent mode selected during interrupt service routine execution
Priority Level Interrupt Request
INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL
MAIN
MAIN
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ARBITRATION MODES (Cont'd) 3.5.2 Nested Mode difference between Nested mode Concurrent mode, lies modification Current Priority Level (CPL) during interrupt processing. arbitration phase basically identical Concurrent mode, however, once request acknowledged, saved Nested Interrupt Control Register (NICR) setting NICR corresponding value (i.e. will set). then loaded with priority request just acknowledged; next arbitration cycle thus performed with reference priority interrupt service routine currently being executed. Start Interrupt Routine interrupt cycle performs following steps:
maskable interrupt requests disabled clearing CICR.IEN. saved special NICR stack hold priority level suspended routine. Priority level acknowledged routine stored CPL, that next request priority will compared with routine currently being serviced. byte pushed onto system stack. high byte pushed onto system stack. ENCSR set, pushed onto system stack. Flag register pushed onto system stack. loaded with 16-bit vector stored Vector Table, pointed IVR. ENCSR set, loaded with contents; otherwise used place until iret instruction.
Figure Simple Example Sequence Interrupt Requests with: Nested mode unchanged interrupt routines
Priority Level Interrupt Request CPL=0 CPL6 CPL3: INT6 pending
INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL
INT0 CPL=2
INT6 CPL=3
CPL=2
INT2 INT3 INT4 CPL=5
INT2 CPL=4
INT5
CPL2 CPL4: Serviced next
CPL=6 MAIN CPL=7
MAIN
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ARBITRATION MODES (Cont'd) Interrupt Routine iret Interrupt Return instruction executes following steps: Flag register popped from system stack. ENCSR set, popped from system stack. high byte popped from system stack. byte popped from system stack. unmasked Interrupts enabled setting CICR.IEN bit. priority level interrupted routine popped from special register (NICR) copied into CPL.
ENCSR reset, used instead ISR, unless program returns another nested routine. suspended routine thus resumes interrupted instruction. Figure contains simple example, showing that instruction used interrupt service routines, nested concurrent modes equivalent. Figure contains more complex example showing nested mode allows nested interrupt processing (enabled inside interrupt service routines using instruction) according their priority level.
Figure Complex Example Sequence Interrupt Requests with: Nested mode during interrupt routine execution
Priority Level Interrupt Request
INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL
CPL=0 CPL6 CPL3: INT6 pending CPL=2 CPL=2
INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL INTERRUPT PRIORITY LEVEL
INT0 CPL=2 INT2 INT3 INT4 CPL=5 INT5 MAIN
INT6 CPL=3 INT2
CPL2 CPL4: Serviced just after CPL=4 CPL=4 CPL=5 CPL=6 MAIN CPL=7
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EXTERNAL INTERRUPTS standard core contains external interrupts sources grouped into four pairs. INT7 connected different pins Port Once these pins programmed alternate function they able generate interrupt. Table External Interrupt Channel Grouping
External Interrupt INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 Channel INTD1 INTD0 INTC1 INTC0 INTB1 INTB0 INTA1 INTA0
Figure Priority Level Examples
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
SOURCE PRIORITY
EIPLR
SOURCE PRIORITY
INT.D0: 100=4 INT.D1: 101=5 INT.C0: 000=0 INT.C1: 001=1
INT.A0: 010=2 INT.A1: 011=3 INT.B0: 100=4 INT.B1: 101=5 VR000151
INT0 have trigger control TEA0,.TED1 (R242,EITR.0,.,7 Page select triggering rising falling edge external pin. Trigger control "1", corresponding pending IPA0,.,IPD1 (R243, EIPR.0,.,6 Page input rising edge, cleared, pending falling edge input pin. Each source individually masked through corresponding control IMA0,.,IMD1 (EIMR.6,.,0). Figure INT7 falling edge sensitive only, EIMR.7 must always cleared. priority level external interrupt sources programmed among eight priority levels with control register EIPLR (R245). priority level each pair software defined using bits PRL2, PRL1. each pair, even channel (A0,B0,C0,D0) group even priority level channel (A1,B1,C1,D1) (lower) priority level.
Figure shows example priority levels. Figure gives overview External interrupt control bits vectors. source interrupt channel selected between external INT0 (when IA0S "1", reset value) On-chip Timer/ Watchdog peripheral (when IA0S "0"). source interrupt channel selected between external INT1 (when AD-INT="0") on-chip peripheral (when AD-INT="1", reset value). source interrupt channel selected between external INT6 (when INT_SEL "0") on-chip RCCU. Important: When using channels shared both external interrupts peripherals, special care must taken configure their control registers both peripherals interrupts. Table Multiplexed Interrupt Sources
Channel INTA0 INTA1 INTD0 Internal Interrupt Source Timer/Watchdog RCCU External Interrupt Source INT0 INT1 INT6
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EXTERNAL INTERRUPTS (Cont'd) Figure External Interrupts Control Bits Vectors
Watchdog/Timer IA0S count VECTOR Priority level PL2A PL1A Mask IMA0 request
TEA0
Pending IPA0
AD-INT
TEA1 VECTOR Priority level PL2A PL1A Mask IMA1 TEB0 VECTOR PL2B PL1B Priority level Mask IMB0 TEB1 VECTOR Priority level PL2B PL1B Mask IMB1 TEC0 VECTOR PL2C PL1C Priority level Mask IMC0 TEC1 VECTOR PL2C PL1C Priority level Mask IMC1 INT_SEL TED0 RCCU TED1 VECTOR Priority level PL2D PL1D Mask IMD0 request request request request request request
Pending IPA1
Pending IPB0
Pending IPB1
Pending IPC0
Pending IPC1
Pending IPD0
ID1S VECTOR Priority level PL2D PL1D Mask IMD1 request
pins P3.[7:0] WKUP [13:0] pins WKUP14 pins P1.[7:0]
Pending IPD1
Wake-up Controller
Shared channels, warning
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MANAGEMENT WAKE-UP LINES EXTERNAL INTERRUPT LINES ST92163, fifteen Wake-up lines (WKUP[14:0]) available external pins. WKUP[15] line internally connected interface line. Figure shows connections External Interrupt Lines INT7[7:0] Wake-up/Interrupt Lines managed through WUIMU INTD1 interrupt channel.
Figure Wake-Up Lines External Interrupt Lines Management
USBISTR Register
ESUSP
WUIMU WKUP[7:0] WKUP[13:8] WKUP15 WKUP14 INT7[7:0] Trigger Registers Pending Registers WKUP14[7:0] Mask Registers
INTERFACE
Setting
WUCTRL Register ID1S
STOP RCCU)
External Interrupt INTD1 CPU)
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LEVEL INTERRUPT Level Interrupt channel assigned either external Timer/ Watchdog according status control EIVR.TLIS (R246.2, Page this high (the reset condition) source external NMI. low, source Timer/ Watchdog Count. When source external pin, control EIVR.TLTEV (R246.3; Page selects between rising set) falling reset) edge generating interrupt request. When selected event occurs, CICR.TLIP (R230.6) set. Depending mask situation, Level Interrupt request generated. kinds masks available, Maskable mask Non-Maskable mask. first mask CICR.TLI (R230.5): cleared enable disable respectively Level Interrupt request. enabled, global Enable Interrupt bit, CICR.IEN (R230.4; Page must also enabled order allow Level Request. second mask NICR.TLNM (R247.7; Page set-only mask. Once set, enables Level Interrupt request independently value CICR.IEN cannot cleared program. Only processor RESET cycle clear this bit. This does prevent user from ignoring some sources change TLIS. Level Interrupt Service Routine cannot interrupted other interrupt request, arbitration mode, even subsequent Level Interrupt request. Figure Level Interrupt Structure
WATCHDOG ENABLE WDEN CORE RESET TLIP PENDING MASK TLIS LEVEL INTERRUPT REQUEST
Warning. interrupt machine cycle Level Interrupt does clear CICR.IEN bit, corresponding iret does ON-CHIP PERIPHERAL INTERRUPTS general structure peripheral interrupt unit described here, however each on-chip peripheral specific interrupt unit containing more interrupt channels, channels. Please refer specific peripheral chapter description interrupt features control registers. on-chip peripheral interrupt channels provide following control bits: Interrupt Pending (IP). hardware when Trigger Event occurs. set/ cleared software generate/cancel pending interrupts give status Interrupt polling. Interrupt Mask (IM). "0", interrupt request generated. ="1" interrupt request generated whenever CICR.IEN "1". Priority Level (PRL, bits). These bits define current priority level, PRL=0: highest priority, PRL=7: lowest priority (the interrupt cannot acknowledged) Interrupt Vector Register (IVR, bits). points vector table which itself contains interrupt routine start address.
WATCHDOG TIMER COUNT
TLTEV TLNM
VA00294
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3.10 INTERRUPT RESPONSE TIME interrupt arbitration protocol functions completely asynchronously from instruction flow, requires CPUCLK cycles resolve request's priority. Requests sampled every CPUCLK cycles. interrupt request comes from external pin, trigger event must occur minimum INTCLK cycle before sampling time. When arbitration results interrupt request being generated, interrupt logic checks current instruction (which could stage execution) safely aborted; this case, instruction execution terminated immediately interrupt request serviced; not, waits until current instruction terminated then services request. Instruction execution normally aborted provided write operation been performed. interrupt deriving from external interrupt channel, response time between user event start interrupt service routine range from minimum clock cycles maximum clock cycles.
non-maskable Level interrupt, response time between user event start interrupt service routine range from minimum clock cycles maximum clock cycles. order guarantee edge detection, input signals must kept low/high minimum INTCLK cycle. interrupt machine cycle requires basic internal clock cycles (CPUCLK), which must added further clock cycles stack Register File. more clock cycles must further added pushed (ENCSR =1). interrupt machine cycle duration forms part examples interrupt response time previously quoted; includes time required push values stack, well interrupt vector handling. Wait Interrupt mode, further cycle required wake-up delay.
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3.11 INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 Read/Write Register Page: System Reset value: 1000 0111 (87h)
GCEN TLIP CPL2 CPL1 CPL0
ple, state known advance, value must restored from previous push CICR stack, sequence CICR make sure that interrupts being arbitrated when CICR modified. IAM: Interrupt Arbitration Mode. This cleared software. Concurrent Mode Nested Mode Bits CPL[2:0]: Current Priority Level. These bits define Current Priority Level. CPL=0 highest priority. CPL=7 lowest priority. These bits modified directly interrupt hardware when Nested Interrupt Mode used. EXTERNAL INTERRUPT TRIGGER REGISTER (EITR) R242 Read/Write Register Page: Reset value: 0000 0000 (00h)
GCEN: Global Counter Enable. This enables 16-bit Multifunction Timer peripheral. disabled enabled TLIP: Level Interrupt Pending. This hardware when Level Interrupt (TLI) trigger event occurs. cleared hardware when acknowledged. also software implement software TLI. pending pending TLI: Level Interrupt. This cleared software. Generate Level Interrupt only TLNM=1 Generate Level Interrupt request when TLIP bits=1. IEN: Interrupt Enable. This cleared interrupt machine cycle (except TLI). iret instruction (except return from TLI). instruction. cleared instruction. Maskable interrupts disabled Maskable Interrupts enabled Note: also changed software using instruction that operates register CICR, however this case, take care avoid spurious interrupts, since cannot cleared middle interrupt arbitration. Only modify when interrupts disabled when peripheral generate interrupts. exam-
TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0
TED1: INTD1 Trigger Event Must always stay cleared TED0: INTD0 Trigger Event TEC1: INTC1 Trigger Event TEC0: INTC0 Trigger Event TEB1: INTB1 Trigger Event TEB0: INTB0 Trigger Event TEA1: INTA1 Trigger Event TEA0: INTA0 Trigger Event These bits cleared software. Select falling edge interrupt trigger event Select rising edge interrupt trigger event
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INTERRUPT REGISTERS (Cont'd) EXTERNAL INTERRUPT PENDING REGISTER (EIPR) R243 Read/Write Register Page: Reset value: 0000 0000 (00h)
IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0
IMB1: INTB1 Interrupt Mask IMB0: INTB0 Interrupt Mask IMA1: INTA1 Interrupt Mask IMA0: INTA0 Interrupt Mask These bits cleared software. Interrupt masked Interrupt masked interrupt generated IPxx bits EXTERNAL INTERRUPT PRIORITY REGISTER (EIPLR) R245 Read/Write Register Page: Reset value: 1111 1111 (FFh)
IPD1: INTD1 Interrupt Pending IPD0: INTD0 Interrupt Pending IPC1: INTC1 Interrupt Pending IPC0: INTC0 Interrupt Pending IPB1: INTB1 Interrupt Pending IPB0: INTB0 Interrupt Pending IPA1: INTA1 Interrupt Pending IPA0: INTA0 Interrupt Pending These bits hardware occurrence trigger event specified EITR register) cleared hardware interrupt acknowledge. They also software implement software interrupt. interrupt pending Interrupt pending EXTERNAL INTERRUPT MASK-BIT REGISTER (EIMR) R244 Read/Write Register Page: Reset value: 0000 0000 (00h)
LEVEL
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
Bits PL2D, PL1D: INTD0, Priority Level. Bits PL2C, PL1C: INTC0, Priority Level. Bits PL2B, PL1B: INTB0, Priority Level. Bits PL2A, PL1A: INTA0, Priority Level. These bits cleared software. priority three-bit value. fixed hardware Channels Channels
PL2x PL1x Hardware Priority (Highest) (Lowest)
IMD1 IMD0 IMC1 IMC0 IMB1 IMB0 IMA1 IMA0
IMD1: INTD1 IMD0: INTD0 IMC1: INTC1 IMC0: INTC0
Interrupt Mask Interrupt Mask Interrupt Mask Interrupt Mask
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INTERRUPT REGISTERS (Cont'd) EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 Read/Write Register Page: Reset value: xxxx 0110 (x6h)
TLTEV TLIS IAOS EWEN
WAITN disabled WAITN enabled stretch external memory access cycle). Note: more details Wait mode refer section describing WAITN External Memory Chapter. NESTED INTERRUPT CONTROL (NICR) R247 Read/Write Register Page: Reset value: 0000 0000 (00h)
TLNM
Bits V[7:4]: Most significant nibble External Interrupt Vector. These bits initialized reset. representation full vector generated from V[7:4] selected external interrupt channel, refer Figure TLTEV: Level Trigger Event bit. This cleared software. Select falling edge trigger event Select rising edge trigger event TLIS: Level Input Selection. This cleared software. Watchdog Count interrupt source interrupt source IA0S: Interrupt Channel Selection. This cleared software. Watchdog Count INTA0 source External Interrupt INTA0 source EWEN: External Wait Enable. This cleared software.
TLNM: Level Maskable. This software cleared only hardware reset. Level Interrupt Maskable. level request generated IEN, TLIP bits Level Interrupt Maskable. level request generated TLIP Bits HL[6:0]: Hold Level These bits hardware when, Nested Mode, interrupt service routine level interrupted from request with higher priority (other than Level interrupt request). They cleared hardware iret execution when routine level recovered.
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INTERRUPT REGISTERS (Cont'd) EXTERNAL MEMORY REGISTER (EMR2) R246 Read/Write Register Page: Reset value: 0000 1111 (0Fh)
ENCSR
terrupt response time. drawback that possible interrupt service routine perform inter-segment calls jumps: these instructions would update CSR, which, this case, used (ISR used instead). code segment size interrupt service routines thus limited bytes. only used point interrupt vector table initialize beginning interrupt service routine: pushed onto stack together with flags, then loaded with contents ISR. this case, iret will also restore from stack. This approach allows interrupt service routines access entire Mbytes address space; drawback that interrupt response time slightly increased, because need also save stack. Full compatibility with original lost this case, because interrupt stack frame different; this difference, however, should affect vast majority programs.
Bits Reserved, keep reset state. Refer external Memory Interface Chapter. ENCSR: Enable Code Segment Register. This cleared software. affects behaviour whenever interrupt request issued. works original compatibility mode. duration interrupt service routine, used instead CSR, interrupt stack frame identical that original ST9: only Flags pushed. This avoids saving stack event interrupt, thus ensuring faster
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3.12 WAKE-UP INTERRUPT LINES MANAGEMENT UNIT (WUIMU) 3.12.1 Introduction 3.12.2 Main Features Supports additional external wake-up Wake-up/Interrupt Management Unit extends interrupt lines number external interrupt lines from (depending number external interrupt Wake-Up lines used wake-up lines mapped external pins device). alfrom STOP mode. lows source INTD1 external interrupt Programmable selection wake-up interrupt channel selected between INT7 Programmable wake-up trigger edge polarity additional external Wake-up/interrupt Wake-Up Lines maskable pins. Note: number available pins device deThese WKUP pins programmed expendent. Refer device pinout description. ternal interrupt lines wake-up lines, able exit microcontroller from power mode (STOP mode) (see Figure 30). Figure Wake-Up Lines Interrupt Management Unit Block Diagram
STOP WKUP[7:0] WKUP[15:8] INT7
WUTRL
WUTRH TRIGGERING LEVEL REGISTERS
WUPRL
WUPRH PENDING REQUEST REGISTERS
WUMRL
WUMRH MASK REGISTERS
Reset
Note: Reset Signal stop stronger than signal
SETTING
WUCTRL
STOP ID1S WKUP-INT
INTD1 External Interrupt Channel
RCCU Stop Mode Control
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ST92163 INTERRUPTS
WAKE-UP INTERRUPT LINES MANAGEMENT UNIT (Cont'd) only restart code execution. 3.12.3 Functional Description WKUP-INT WUCTRL register 3.12.3.1 Interrupt Mode select Wake-up Mode. configure wake-up lines interrupt ID1S WUCTRL register dissources, following procedure: able INT7 external interrupt source Configure mask bits wake-up lines enable wake-up lines external inter(WUMRL, WUMRH). rupt source lines. This mandatory Configure triggering edge registers wake-up event does require interrupt wake-up lines (WUTRL, WUTRH). response. EIMR (R244 Page EITR Write sequence 1,0,1 STOP (R242 Page registers CPU: WUCTRL register with three consecutive write interrupt coming from lines operations. This STOP setting correctly acknowledged. sequence. Reset WKUP-INT WUCTRL regisTo detect STOP Mode entered not, imter disable Wake-up Mode. mediately after STOP setting sequence, poll RCCU EX_STP (R242.7, Page ID1S WUCTRL register disthe STOP itself. able INT7 external interrupt source enable wake-up lines external interrupt source lines. 3.12.3.3 STOP Mode Entry Conditions return standard mode (INT7 external interAssuming mode: during rupt source enabled wake-up lines disaSTOP setting sequence following cases bled) sufficient reset ID1S bit. occur: Case Wrong STOP setting sequence 3.12.3.2 Wake-up Mode Selection This happen Interrupt/DMA request acTo configure lines wake-up sources, knowledged during STOP setting sethe following procedure: quence. this case polling STOP EX_STP bits will give: Configure mask bits wake-up lines (WUMRL, WUMRH). STOP EX_STP Configure triggering edge registers This means that enter STOP mode wake-up lines (WUTRL, WUTRH). STOP setting sequence: user must retry sequence. Set, Interrupt Mode selection, EIMR EITR registers only interrupt Case Correct STOP setting sequence routine executed after wake-up event. this case enters STOP mode. Otherwise, wake-up event only restarts exit STOP mode, wake-up interrupt must execution code from where acknowledged. That implies: stopped, INTD1 interrupt channel must masked external source must STOP EX_STP selected resetting ID1S bit. This means that entered exited STOP Since RCCU generate interrupt mode external wake-up line event. request when exiting from STOP mode, take care mask even wake-up event
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ST92163 INTERRUPTS
WAKE-UP INTERRUPT LINES MANAGEMENT UNIT (Cont'd) Case wake-up event external wakeIf really exits from STOP Mode, lines occurs during STOP setting seRCCU EX_STP still must reset quence software. Otherwise, Interrupt/DMA request acknowledged during STOP setting seThere possible cases: quence, RCCU EX_STP reset. This Interrupt requests disabled: means that filtered STOP Mode this case will enter STOP mode, entry request. interrupt service routine will executed WKUP-INT used interrupt program execution continues from routine detect distinguish events coming instruction following STOP setting from Interrupt Mode from Wake-up Mode, allowsequence. status STOP EX_STP code execute different procedures. bits will again: exit STOP mode, sufficient that STOP EX_STP wake-up lines (not masked) generates application determine event: clock restarts after delay needed enter STOP mode polling pending oscillator restart. bits external lines least must Note: After exiting from STOP Mode, software Interrupt requests enabled: this successfully reset pending bits (edge sencase will enter STOP mode sitive), even though corresponding wake-up interrupt service routine will executed. line still active (high low, depending status STOP EX_STP bits will again: Trigger Event register programming); user STOP EX_STP must poll external status detect distinguish short event from long (for example interrupt service routine determine keyboard input with keystrokes varying length). enter STOP mode polling pending bits external lines least must
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ST92163 INTERRUPTS
WAKE-UP INTERRUPT LINES MANAGEMENT UNIT (Cont'd) 3.12.4 Programming Considerations Poll wake-up pending bits determine which wake-up line caused exit from STOP following paragraphs give some guidelines mode. designing application program. 10.Clear wake-up pending that set. 3.12.4.1 Procedure Entering/Exiting STOP mode 3.12.4.2 Simultaneous Setting Pending Bits Program polarity trigger event possible that several simultaneous events external wake-up lines writing registers different pending bits. order accept subseWUTRH WUTRL. quent events external wake-up/interrupt lines, necessary clear least pending bit: this Check that least mask (registers operation allows rising edge generated WUMRH, WUMRL) equal least INTD1 line there least more pendone external wake-up line masked). masked) EIPR.7 Reset least unmasked pending bits: this again. further interrupt channel INTD1 will allows rising edge generated serviced depending status EIMR.7. INTD1 channel when trigger event occurs possible situations arise: interrupt channel INTD1 recognized user chooses reset pending bits: when rising edge occurs). further interrupt requests will generated Select interrupt source INTD1 chanchannel INTD1. this case user (see description ID1S WUCTRL Reset EIMR.7 avoid generating spuriregister) WKUP-INT bit. interrupt request during next reset op5. generate interrupt channel INTD1, bits eration WUPRH register) EITR.1 (R242.7, Page EIMR.1 (R244.7, Reset WUPRH register using read-modifyPage must EIPR.7 must write instruction (AND, BRES, BAND) reset. Bits register R245, Page Clear EIPR.7 must written with desired priority level interrupt channel INTD1. Reset WUPRL register using read-modify-write instruction (AND, BRES, BAND) Reset STOP register WUCTRL EX_STP CLK_FLAG register user chooses keep least pending (R242.7, Page 55). Refer RCCU chapter. active: least additional interrupt request will generated INTD1 chan7. enter STOP mode, write sequence nel. this case user reset STOP WUCTRL register with desired pending bits with read-modify-write three consecutive write operations. instruction (AND, BRES, BAND). This operation code executed just after STOP will generate rising edge INTD1 chansequence must check status STOP EIPR.7 will again. RCCU EX_STP bits determine interrupt INTD1 channel will serviced entered STOP mode (See "Wake-up depending status EIMR.7 bit. Mode Selection" page details). enter STOP mode necessary reloop procedure from beginning, otherwise procedure continues from next point.
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ST92163 INTERRUPTS
WAKE-UP INTERRUPT LINES MANAGEMENT UNIT (Cont'd) sequence. Interrupt requests (which al3.12.5 Register Description ways perform register write operations) acWAKE-UP CONTROL REGISTER (WUCTRL) knowledged during sequence, will R249 Read/Write enter STOP mode: user must re-enter seRegister Page: quence STOP bit. Reset Value: 0000 0000 (00h) WARNING: Whenever STOP request issued MCU, clock cycles needed enter STOP mode (see RCCU chapter further deSTOP ID1S WKUP-INT tails). Hence execution instruction following STOP setting sequence might start before entering STOP mode: such instruction STOP: Stop bit. performs register write operation, will enter STOP Mode, write sequence 1,0,1 enter STOP mode. order avoid exethis with three consecutive write operations. cute register write instructions after correct When correct sequence recognized, STOP setting sequence before entering STOP RCCU puts STOP mode, mandatory execute STOP Mode. software sequence succeeds instructions after STOP setting sequence. only following conditions true: WKUP-INT unmasked pending bits reset, least mask equal least external wake-up line masked). Otherwise cannot enter STOP mode, program code continues executing STOP remains cleared. reset hardware while STOP mode, wake-up interrupt comes from unmasked wake-up lines. STOP following cases (See "Wake-up Mode Selection" page details): After first write instruction sequence written STOP bit) successful sequence (i.e. after third write instruction sequence) Note: STOP request generated WUIMU (that allows enter STOP mode) ORed with external STOP (active low). This means that external STOP forced low, will enter STOP mode independently status STOP bit. WARNING: Writing sequence 1,0,1 STOP will enter STOP mode only other register write instructions executed during ID1S: Interrupt Channel INTD1 Source. This cleared software. INT7 external interrupt source selected, excluding wake-up line interrupt requests external wake-up lines enabled interrupt sources, replacing INT7 external function WARNING: avoid spurious interrupt requests INTD1 channel changing interrupt source, following before modifying ID1S bit: Mask INTD1 interrupt channel (bit register EIMR R244, Page reset Program ID1S needed. Clear IPD1 interrupt pending (bit register EIPR R243, Page Remove mask INTD1 (bit EIMR.7=1). WKUP-INT: Wakeup Interrupt. This cleared software. external wakeup lines used generate interrupt requests external wake-up lines work wakeup sources exiting from STOP mode
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ST92163 INTERRUPTS
WAKE-UP INTERRUPT LINES MANAGEMENT UNIT (Cont'd) WAKE-UP MASK REGISTER (WUMRL) WAKE-UP MASK REGISTER HIGH (WUMRH) R251 Read/Write R250 Read/Write Register Page: Register Page: Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h)
WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9
WUM8
WUM7 WUM6 WUM5 WUM4 WUM3 WUM2 WUM1
WUM0
WUM[15:8]: Wake-Up Mask bits. WUMx set, interrupt channel INTD1 and/or wake-up event (depending ID1S WKUP-INT bits) generated corresponding WUPx pending set. More precisely, WUMx=1 WUPx=1 then: ID1S=1 WKUP-INT=1 then interrupt channel INTD1 wake-up event generated. ID1S=1 WKUP-INT=0 only interrupt channel INTD1 generated. ID1S=0 WKUP-INT=1 only wake-up event generated. ID1S=0 WKUP-INT=0 neither interrupts channel INTD1 wake-up events generated. Interrupt requests channel INTD1 generated only from external interrupt source INT7. WUMx reset, wake-up events generated. Interrupt requests channel INTD1 generated only from external interrupt source INT7 (resetting ID1S
WUM[7:0]: Wake-Up Mask bits. WUMx set, interrupt channel INTD1 and/or wake-up event (depending ID1S WKUP-INT bits) generated corresponding WUPx pending set. More precisely, WUMx=1 WUPx=1 then: ID1S=1 WKUP-INT=1 then interrupt channel INTD1 wake-up event generated. ID1S=1 WKUP-INT=0 only interrupt channel INTD1 generated. ID1S=0 WKUP-INT=1 only wake-up event generated. ID1S=0 WKUP-INT=0 neither interrupts channel INTD1 wake-up events generated. Interrupt requests channel INTD1 generated only from external interrupt source INT7. WUMx reset, wake-up events generated. Interrupt requests channel INTD1 generated only from external interrupt source INT7 (resetting ID1S
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ST92163 INTERRUPTS
WAKE-UP INTERRUPT LINES MANAGEMENT UNIT (Cont'd) WAKE-UP TRIGGER REGISTER HIGH (WUTRH) WAKE-UP PENDING REGISTER HIGH R252 Read/Write (WUPRH) Register Page: R254 Read/Write Reset Value: 0000 0000 (00h) Register Page: Reset Value: 0000 0000 (00h)
WUT15 WUT14 WUT13 WUT12 WUT11 WUT10 WUT9 WUT8
WUP15 WUP14 WUP13 WUP12 WUP11 WUP10 WUP9
WUP8
WUT[15:8]: Wake-Up Trigger Polarity Bits These bits cleared software. corresponding WUPx pending will falling edge input wake-up line. corresponding WUPx pending will rising edge input wake-up line. WAKE-UP TRIGGER REGISTER (WUTRL) R253 Read/Write Register Page: Reset Value: 0000 0000 (00h)
WUT7 WUT6 WUT5 WUT4 WUT3 WUT2 WUT1
WUP[15:8]: Wake-Up Pending Bits These bits hardware occurrence trigger event corresponding wake-up line. They must cleared software. They software implement software interrupt. Wake-up Trigger event occurred Wake-up Trigger event occured
WUT0
WAKE-UP PENDING REGISTER (WUPRL) R255 Read/Write Register Page: Reset Value: 0000 0000 (00h)
WUP6 WUP5 WUP4 WUP3 WUP2 WUP1 WUP0
WUT[7:0]: Wake-Up Trigger Polarity Bits These bits cleared software. corresponding WUPx pending will falling edge input wake-up line. corresponding WUPx pending will rising edge input wake-up line. WARNING external wake-up lines edge triggered, glitches must generated these lines. either rising falling edge external wake-up lines occurs while writing WUTRH WUTRL registers, pending will set.
WUP7
WUP[7:0]: Wake-Up Pending Bits These bits hardware occurrence trigger event corresponding wake-up line. They must cleared software. They software implement software interrupt. Wake-up Trigger event occurred Wake-up Trigger event occured Note: avoid losing trigger event while clearing pending bits, recommended read-modify-write instructions (AND, BRES, BAND) clear them.
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ST92163 ON-CHIP DIRECT MEMORY ACCESS (DMA)
ON-CHIP DIRECT MEMORY ACCESS (DMA)
INTRODUCTION includes on-chip Direct Memory Access (DMA) order provide high-speed data transfer between peripherals memory Register File. Multi-channel fully supported peripherals having their controller channel(s). Each channel transfers data from contiguous locations Register File, Memory. maximum number bytes that transferred transaction each channel with Register File, 65536 with Memory. controller Peripheral uses indirect addressing mechanism Pointers Counter Registers stored Register File. This reason maximum number transactions Register File 222, since Registers allocated Pointer Counter. Register pairs used memory pointers counters order offer full 65536 byte count capability. Figure Data Transfer
REGISTER FILE REGISTER FILE MEMORY
PRIORITY LEVELS priority levels used interrupts also used prioritize requests, which arbitrated same arbitration phase interrupt requests. event occurrence requires transaction, this will take place current instruction execution. When interrupt request occur simultaneously, same priority level, request serviced before interrupt. interrupt priority request must strictly higher than value order acknowledged, whereas, transaction request, must equal higher than value order executed. Thus only transaction requests acknowledged when CPL=0. requests modify value, since transaction interruptable.
REGISTER FILE
GROUP PERIPHERAL PAGED REGISTERS
PERIPHERAL
COUNTER ADDRESS
DATA
COUNTER VALUE
TRANSFERRED DATA
START ADDRESS
VR001834
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ST92163 ON-CHIP DIRECT MEMORY ACCESS (DMA)
TRANSACTIONS purpose on-chip channel transfer block data
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