8-BIT WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, INTER
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ST72104G, ST72215G, ST72216G, ST72254G
8-BIT WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, INTERFACES
Memories bytes Program memory (ROM single voltage FLASH) with read-out protection in-situ programming (remote ISP) bytes Clock, Reset Supply Management Enhanced reset system Enhanced voltage supply supervisor with programmable levels Clock sources: crystal/ceramic resonator oscillators oscillators, external clock, backup Clock Security System Clock-out capability Power Saving Modes: Halt, Wait Slow Interrupt Management interrupt vectors plus TRAP RESET external interrupt lines vectors) Ports multifunctional bidirectional lines alternate function lines high sink outputs Timers Configurable watchdog timer 16-bit timers with: input captures, output compares, external clock input timer, Pulse generator modes (one only ST72104Gx ST72216G1) Communications Interfaces synchronous serial interface multimaster interface (only ST72254Gx) Analog peripheral 8-bit with input channels (except ST72104Gx)
SDIP32
SO28
Instruction 8-bit data manipulation basic instructions main addressing modes unsigned multiply instruction True manipulation Development Tools Full hardware/software development package
Device Summary
Features Program memory bytes (stack) bytes Peripherals Operating Supply Frequency Operating Temperature Packages ST72104G1 ST72104G2 ST72216G1 ST72215G2 ST72254G1 ST72254G2 (128) Watchdog timer, Watchdog timer, Watchdog timer, Watchdog timer, 16-bit timer, 16-bit timer, 16-bit timers, 16-bit timers, SPI, SPI, SPI, 3.2V 5.5V (with oscillator MHz) 70°C -10°C +85°C (-40°C +85°C -40°C to105°C -40°C 125°C optional) SO28 SDIP32
Rev.
November 2000
This preliminary information product development undergoing evaluation. Details subject change without notice.
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Table Content1 INTRODUCTION DESCRIPTION REGISTER MEMORY FLASH PROGRAM MEMORY INTRODUCTION MAIN FEATURES STRUCTURAL ORGANISATION IN-SITU PROGRAMMING (ISP) MODE MEMORY READ-OUT PROTECTION
CENTRAL PROCESSING UNIT INTRODUCTION MAIN FEATURES REGISTERS
CENTRAL PROCESSING UNIT (Cont'd) SUPPLY, RESET CLOCK MANAGEMENT VOLTAGE DETECTOR (LVD) RESET SEQUENCE MANAGER (RSM) 7.2.1 Introduction 7.2.2 Asynchronous External RESET 7.2.3 Internal Voltage Detection RESET 7.2.4 Internal Watchdog RESET MULTI-OSCILLATOR (MO) 7.4.1 Clock Filter Control 7.4.2 Safe Oscillator Control 7.4.3 Power Modes 7.4.4 Interrupts CLOCK RESET SUPPLY REGISTER DESCRIPTION (CRSR)
CLOCK SECURITY SYSTEM (CSS)
MAIN CLOCK CONTROLLER (MCC)
INTERRUPTS MASKABLE SOFTWARE INTERRUPT EXTERNAL INTERRUPTS PERIPHERAL INTERRUPTS
POWER SAVING MODES INTRODUCTION SLOW MODE WAIT MODE HALT MODE
PORTS 10.1 INTRODUCTION 10.2 FUNCTIONAL DESCRIPTION 10.2.1Input Modes 10.2.2Output Modes
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Table Content10.2.3Alternate Functions 10.3 PORT IMPLEMENTATION 10.4 POWER MODES 10.5 INTERRUPTS 10.6 REGISTER DESCRIPTION MISCELLANEOUS REGISTERS 11.1 PORT INTERRUPT SENSITIVITY 11.2 PORT ALTERNATE FUNCTIONS 11.3 MISCELLANEOUS REGISTER DESCRIPTION ON-CHIP PERIPHERALS 12.1 WATCHDOG TIMER (WDG) 12.1.1Introduction 12.1.2Main Features 12.1.3Functional Description 12.1.4Hardware Watchdog Option 12.1.5Low Power Modes 12.1.6Interrupts 12.1.7Register Description 12.2 16-BIT TIMER 12.2.1Introduction 12.2.2Main Features 12.2.3Functional Description 12.2.4Low Power Modes 12.2.5Interrupts 12.2.6Summary Timer modes 12.2.7Register Description 12.3 SERIAL PERIPHERAL INTERFACE (SPI) 12.3.1Introduction 12.3.2Main Features 12.3.3General description 12.3.4Functional Description 12.3.5Low Power Modes 12.3.6Interrupts 12.3.7Register Description 12.4 INTERFACE (I2C) 12.4.1Introduction 12.4.2Main Features 12.4.3General Description 12.4.4Functional Description 12.4.5Low Power Modes 12.4.6Interrupts 12.4.7Register Description 12.5 8-BIT CONVERTER (ADC)
12.5.1Introduction 12.5.2Main Features 12.5.3Functional Description
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Table Content12.5.4Low Power Modes 12.5.5Interrupts 12.5.6Register Description INSTRUCTION 13.1 ADDRESSING MODES 13.1.1Inherent 13.1.2Immediate 13.1.3Direct 13.1.4Indexed Offset, Short, Long) 13.1.5Indirect (Short, Long) 13.1.6Indirect Indexed (Short, Long) 13.1.7Relative Mode (Direct, Indirect) 13.2 INSTRUCTION GROUPS
ELECTRICAL CHARACTERISTICS 14.1 PARAMETER CONDITIONS 14.1.1Minimum Maximum values 14.1.2Typical values 14.1.3Typical curves 14.1.4Loading capacitor 14.1.5Pin input voltage 14.2 ABSOLUTE MAXIMUM RATINGS 14.2.1Voltage Characteristics 14.2.2Current Characteristics 14.2.3Thermal Characteristics 14.3 OPERATING CONDITIONS
14.3.1General Operating Conditions 14.3.2Operating Conditions with Voltage Detector (LVD) 14.4 SUPPLY CURRENT CHARACTERISTICS 14.4.1RUN SLOW Modes 14.4.2WAIT SLOW WAIT Modes 14.4.3HALT Mode 14.4.4Supply Clock Managers 14.4.5On-Chip Peripherals 14.5 CLOCK TIMING CHARACTERISTICS 14.5.1General Timings 14.5.2External Clock Source 14.5.3Crystal Ceramic Resonator Oscillators 14.5.4RC Oscillators 14.5.5Clock Security System (CSS) 14.6 MEMORY CHARACTERISTICS
14.6.1RAM Hardware Registers 14.6.2FLASH Program Memory 14.7 CHARACTERISTICS 14.7.1Functional 14.7.2Absolute Electrical Sensitivity 14.7.3ESD Protection Strategy 14.8 PORT CHARACTERISTICS
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Table Content14.8.1General Characteristics 14.8.2Output Driving Current 14.9 CONTROL CHARACTERISTICS 14.9.1Asynchronous RESET 14.9.2ISPSEL 14.10 TIMER PERIPHERAL CHARACTERISTICS 14.10.1Watchdog Timer 14.10.216-Bit Timer 14.11 COMMUNICATION INTERFACE CHARACTERISTICS 14.11.1SPI Serial Peripheral Interface 14.11.2I2C Inter Control Interface 14.12 8-BIT CHARACTERISTICS PACKAGE CHARACTERISTICS 15.1 PACKAGE MECHANICAL DATA 15.2 THERMAL CHARACTERISTICS 15.3 SOLDERING GLUEABILITY INFORMATION DEVICE CONFIGURATION ORDERING INFORMATION 16.1 OPTION BYTES 16.2 DEVICE ORDERING INFORMATION TRANSFER CUSTOMER CODE 16.3 DEVELOPMENT TOOLS 16.3.1PACKAGE/SOCKET FOOTPRINT PROPOSAL 16.4 APPLICATION NOTES 16.5 MORE INFORMATION SUMMARY CHANGES
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INTRODUCTION
ST72104G, ST72215G, ST72216G ST72254G devices members microcontroller family. They grouped follows: ST72254G devices designed mid-range applications with interface capabilities. ST72215/6G devices target same range applications without interface. ST72104G devices applications that need peripherals. devices based common industrystandard 8-bit core, featuring enhanced instruction set. ST72C104G, ST72C215G, ST72C216G ST72C254G versions feature single-voltage FLASH memory with byte-by-byte In-Situ Programming (ISP) capability. Figure General Block Diagram Under software control, devices placed WAIT, SLOW, HALT mode, reducing power consumption when application idle stand-by state. enhanced instruction addressing modes offer both power flexibility software developers, enabling design highly efficient compact application code. addition standard 8-bit data management, microcontrollers feature true manipulation, unsigned multiplication indirect addressing modes. easy reference, parametric data located Section page
OSC1 OSC2
MULTI CLOCK FILTER
Internal CLOCK PORT PA7:0 bits)
RESET
POWER SUPPLY
ADDRESS DATA
PORT 16-BIT TIMER PORT 8-BIT 16-BIT TIMER PB7:0 bits)
CONTROL 8-BIT CORE PROGRAM MEMORY Bytes)
PC5:0 bits)
(256 Bytes)
WATCHDOG
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DESCRIPTION
Figure 28-Pin Package Pinout
RESET OSC1 OSC2 SS/PB7 ISPCLK/SCK/PB6 ISPDATA/MISO/PB5 MOSI/PB4 OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 AIN4/OCMP2_B/PC4 AIN3/ICAP2_B/PC3 ISPSEL (HS) (HS) (HS) (HS) (HS)/SCLI (HS) (HS)/SDAI (HS) PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1 PC2/MCO/AIN2
(HS) 20mA high sink capability associated external interrupt vector
Figure 32-Pin SDIP Package Pinout
RESET OSC1 OSC2 SS/PB7 ISPCLK/SCK/PB6 ISPDATA/MISO/PB5 MOSI/PB4 OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 AIN4/OCMP2_B/PC4 AIN3/ICAP2_B/PC3 ISPSEL (HS) (HS) (HS) (HS) (HS)/SCLI (HS) (HS)/SDAI (HS) PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1 PC2/MCO/AIN2
(HS) 20mA high sink capability associated external interrupt vector
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DESCRIPTION (Cont'd) external connection guidelines, refer Section "ELECTRICAL CHARACTERISTICS" page Legend Abbreviations Table Type: input, output, supply Input level: Dedicated analog input In/Output level: CMOS 0.3VDD/0.7VDD, CMOS 0.3VDD/0.7VDD with input trigger Output level: 20mA high sink N-buffer only) Port control configuration: Input: float floating, weak pull-up, interrupt analog Output: open drain push-pull Refer Section "I/O PORTS" page more details software configuration ports. RESET configuration each shown bold. This configuration valid long device reset state. Table Device Description
Type SDIP32 SO28 Name Level Output Input Port Control Input float Output Main Function (after reset) Alternate Function
RESET OSC1 OSC2 PB7/SS PB6/SCK/ISPCLK PB5/MISO/ISPDATA PB4/MOSI
priority maskable interrupt (active low) External clock input Resonator oscillator inverter input resistor input oscillator Resonator oscillator inverter output capacitor input oscillator
Port Port Port Port
Slave Select (active low) Serial Clock Clock Master Slave Data Data Master Slave Data
Connected PB3/OCMP2_A PB2/ICAP2_A ei0/ei1 ei0/ei1 ei0/ei1 Port Port Port Port Port Port Port Timer Output Compare Timer Input Capture Timer Output Compare Timer Input Capture Timer Input Clock Analog Input Timer Output Compare Analog Input Timer Input Capture Analog Input
/OCMP1_A /ICAP1_A
PC5/EXTCLK_A/AIN5 PC4/OCMP2_B/AIN4 PC3/ ICAP2_B/AIN3
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Type SDIP32 SO28 Name
Level Output Input
Port Control Input float Output Main Function (after reset) Alternate Function
PC2/MCO/AIN2 PC1/OCMP1_B/AIN1 PC0/ICAP1_B/AIN0 /SDAI /SCLI
ei0/ei1 ei0/ei1 ei0/ei1
Port Port Port Port Port
Main clock output (fCPU) Analog Input Timer Output Compare Analog Input Timer Input Capture Analog Input Data
Port Port Clock
Connected Port Port Port Port situ programming selection (Should tied standard user mode). Ground Main power supply ISPSEL
Notes: interrupt input column, "eiX" defines associated external interrupt vector. weak pull-up column (wpu) merged with interrupt column (int), then configuration pull-up interrupt input, else configuration floating interrupt input. open drain output column, defines true open drain (P-Buffer protection diode implemented). Section "I/O PORTS" page Section 14.8 "I/O PORT CHARACTERISTICS" page more details. OSC1 OSC2 pins connect crystal ceramic resonator, external external source on-chip oscillator Section "PIN DESCRIPTION" page Section 14.5 "CLOCK TIMING CHARACTERISTICS" page more details.
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REGISTER MEMORY
shown Figure capable addressing bytes memories registers. available memory locations consist bytes register location, bytes 8Kbytes user program memory. space includes bytes stack from 0100h 017Fh. highest address bytes contain user reset interrupt vectors. Figure Memory IMPORTANT: Memory locations marked "Reserved" must never accessed. Accessing reserved area have unpredictable effects device.
0000h 007Fh 0080h
Registers (see Table
0080h
Bytes
017Fh 0180h
00FFh 0100h
Short Addressing Zero page (128 Bytes) Stack 16-bit Addressing (128 Bytes)
Reserved
DFFFh E000h
017Fh
Program Memory (4K, KBytes)
FFDFh FFE0h FFFFh
E000h
KByteF000h
Interrupt Reset Vectors (see Table page
KByteFFFFh
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Table Hardware Register
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR WATCHDOG MISCR1 SPIDR SPICR SPISR WDGCR CRSR PADR PADDR PAOR Port PBDR PBDDR PBOR Block Register Label PCDR PCDDR PCOR Register Name Port Data Register Port Data Direction Register Port Option Register Reserved Byte) Port Data Register Port Data Direction Register Port Option Register Reserved Byte) Port Data Register Port Data Direction Register Port Option Register R/W. Reset Status Remarks
Port
Port
Reserved Bytes) Miscellaneous Register Data Register Control Register Status Register Watchdog Control Register Read Only
Clock, Reset, Supply Control Status Register 000x 000x Reserved bytes) Control Register Status Register Status Register Clock Control Register Address Register Address Register Data Register Reserved Bytes) Read Only Read Only
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Address 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 006Fh 0070h 0071h 0072h 007Fh
Block
Register Label TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR MISCR2 TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer
Register Name Control Register Control Register Status Register Input Capture High Register Input Capture Register Output Compare High Register Output Compare Register Counter High Register Counter Register Alternate Counter High Register Alternate Counter Register Input Capture High Register Input Capture Register Output Compare High Register Output Compare Register
Reset Status
Remarks Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only
TIMER
Miscellaneous Register Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Control Register Control Register Status Register Input Capture High Register Input Capture Register Output Compare High Register Output Compare Register Counter High Register Counter Register Alternate Counter High Register Alternate Counter Register Input Capture High Register Input Capture Register Output Compare High Register Output Compare Register Reserved Bytes)
TIMER
ADCDR ADCCSR
Data Register Control/Status Register Reserved Bytes)
Read Only
Legend: x=undefined, R/W=read/write Notes: contents port registers readable only output configuration. input configuration, values pins returned instead register contents. bits associated with unavailable pins must always keep their reset value.
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FLASH PROGRAM MEMORY
INTRODUCTION FLASH devices have single voltage non-volatile FLASH memory that programmed in-situ plugged programming tool) byte-bybyte basis. MAIN FEATURES
Remote In-Situ Programming (ISP) mode bytes programmed same cycle memory (Multiple Time Programmable) Read-out memory protection against piracy
STRUCTURAL ORGANISATION FLASH program memory organised single 8-bit wide memory block which used storing both code data constants. FLASH program memory mapped upper part addressing space includes reset interrupt user vector area IN-SITU PROGRAMMING (ISP) MODE FLASH program memory programmed using Remote mode. This mode allows contents program memory updated using standard programming tools after device mounted application board. This feature implemented with minimum number added components board area impact. example Remote hardware interface standard programming tool described below. more details programming, refer Programming Specification. Remote Overview Remote mode initiated specific sequence dedicated ISPSEL pin. Remote performed three steps: Selection execution mode Download Remote code Execution Remote code program user program into FLASH Remote hardware configuration Remote mode, supplied with power VSS) clock signal (oscillator application crystal circuit example).
This mode needs five signals (plus signal necessary) connected programming tool. This signals are: RESET: device reset VSS: device ground power supply ISPCLK: output serial clock ISPDATA: input serial data ISPSEL: Remote mode selection. This must connected application board through pull-down resistor. these pins used other purposes application, serial resistor implemented avoid conflict other device forces signal level. Figure shows typical hardware interface standard programming tool. more details locations, refer device pinout description. Figure Typical Remote Interface XTAL
HE10 CONNECTOR TYPE PROGRAMMING TOOL
OSC2
OSC1
ISPSEL RESET
ISPCLK ISPDATA
APPLICATION
MEMORY READ-OUT PROTECTION read-out protection enabled through option bit. FLASH devices, when this option selected, program data stored FLASH memory protected against read-out piracy (including re-write protection). When this protection option removed entire FLASH program memory first automatically erased. However, E2PROM data memory (when available) protected only with devices.
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CENTRAL PROCESSING UNIT
INTRODUCTION This full 8-bit architecture contains internal registers allowing efficient 8-bit data manipulation. MAIN FEATURES
basic instructions Fast 8-bit 8-bit multiply main addressing modes 8-bit index registers 16-bit stack pointer power modes Maskable hardware interrupts Non-maskable software interrupt
REGISTERS registers shown Figure present memory mapping accessed specific instructions. Figure Register7 RESET VALUE RESET VALUE RESET VALUE
Accumulator Accumulator 8-bit general purpose register used hold operands results arithmetic logic calculations manipulate data. Index Registers indexed addressing modes, these 8-bit registers used create either effective addresses temporary storage areas data manipulation. (The Cross-Assembler generates precede instruction (PRE) indicate that following instruction refers register.) register affected interrupt automatic procedures (not pushed popped from stack). Program Counter (PC) program counter 16-bit register containing address next instruction executed CPU. made 8-bit registers (Program Counter which LSB) (Program Counter High which MSB).
ACCUMULATOR
INDEX REGISTER
INDEX REGISTER
PROGRAM COUNTER RESET VALUE RESET VECTOR FFFEh-FFFFh CONDITION CODE REGISTER
RESET VALUE STACK POINTER RESET VALUE STACK HIGHER ADDRESS Undefined Value
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REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
because hardware start routine reset IRET instruction routine. cleared software interrupt routine, pending interrupts serviced regardless priority level current interrupt routine. Negative. This cleared hardware. representative result sign last arithmetic, logical data manipulation. copy result. result last operation positive null. result last operation negative (i.e. most significant logic This accessed JRMI JRPL instructions. Zero. This cleared hardware. This indicates that result last arithmetic, logical data manipulation zero. result last operation different from zero. result last operation zero. This accessed JREQ JRNE test instructions.
8-bit Condition Code register contains interrupt mask four flags representative result instruction just executed. This register also handled PUSH instructions. These bits individually tested and/or controlled specific instructions. Half carry. This hardware when carry occurs between bits during instruction. reset hardware during same instructions. half carry occurred. half carry occurred. This tested using JRNH instruction. useful arithmetic subroutines. Interrupt mask. This hardware when entering interrupt software disable interrupts except TRAP software interrupt. This cleared software. Interrupts enabled. Interrupts disabled. This controlled RIM, IRET instructions tested JRNM instructions. Note: Interrupts requested while latched processed when cleared. default interrupt routine interruptable
Carry/borrow. This cleared hardware software. indicates overflow underflow occurred during last arithmetic operation. overflow underflow occurred. overflow underflow occurred. This driven instructions tested JRNC instructions. also affected "bit test branch", shift rotate instructions.
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CENTRAL PROCESSING UNIT (Cont'd)
Stack Pointer (SP) Read/Write Reset Value:
Stack Pointer 16-bit register which always pointing next free location stack. then decremented after data been pushed onto stack incremented before data popped from stack (see Figure Since stack bytes deep, most significant bits forced hardware. Following Reset, after Reset Stack Pointer instruction (RSP), Stack Pointer contains reset value (the bits set) which stack higher address. Figure Stack Manipulation Example
CALL Subroutine 0100h Interrupt Event PUSH
least significant byte Stack Pointer (called directly accessed instruction. Note: When lower limit exceeded, Stack Pointer wraps around stack upper limit, without indicating stack overflow. previously stored information then overwritten therefore lost. stack also wraps case underflow. stack used save return address during subroutine call context during interrupt. user also directly manipulate stack means PUSH instructions. case interrupt, stored first location pointed Then other registers stored next locations shown Figure When interrupt received, decremented context pushed stack. return from interrupt, incremented context popped from stack. subroutine call occupies locations interrupt five locations stack area.
IRET
017Fh
Stack Higher Address 017Fh Stack Lower Address 0100h
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SUPPLY, RESET CLOCK MANAGEMENT
ST72104G, ST72215G, ST72216G ST72254G microcontrollers include range utility features securing application critical situations (for example case power brownout), reducing number external components. overview shown Figure Section "ELECTRICAL CHARACTERISTICS" page more details. Main Features Supply Manager with main supply voltage detection (LVD) Reset Sequence Manager (RSM) Multi-Oscillator (MO) Crystal/Ceramic resonator oscillators External oscillator Internal oscillator Clock Security System (CSS) Clock Filter Backup Safe Oscillator
Figure Clock, Reset Supply Block Diagram
CLOCK SECURITY SYSTEM (CSS) OSC2 OSC1 MULTIOSCILLATOR (MO) FILTER CLOCK SAFE fOSC MAIN CLOCK CONTROLLER (MCC) fCPU
RESET SEQUENCE RESET MANAGER (RSM) FROM WATCHDOG PERIPHERAL
VOLTAGE DETECTOR (LVD) CRSR
INTERRUPT
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VOLTAGE DETECTOR (LVD) allow integration power management features application, Voltage Detector function (LVD) generates static reset when supply voltage below VIT- reference value. This means that secures power-up well power-down keeping reset. VIT- reference value voltage drop lower than VIT+ reference value power-on order avoid parasitic reset when starts running sinks current supply (hysteresis). Reset circuitry generates reset when below: VIT+ when rising VIT- when falling function illustrated Figure Provided minimum value (guaranteed oscillator frequency) above VIT-, only modes: under full software control static safe reset Figure Voltage Detector Reset these conditions, secure operation always ensured application without need external reset hardware. During Voltage Detector Reset, RESET held low, thus permitting reset other devices. Notes: allows device used without external RESET circuitry. Three different reference levels selectable through option byte according application requirement. application note Application software detect reset caused reading LVDRF CRSR register. This hardware when reset generated cleared software (writing zero).
Vhyst VIT+ VIT-
RESET
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RESET SEQUENCE MANAGER (RSM) 7.2.1 Introduction reset sequence manager includes three RESET sources shown Figure External RESET source pulse Internal RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources RESET always kept during delay phase. RESET service routine vector fixed addresses FFFEh-FFFFh memory map. basic RESET sequence consists phases shown Figure Delay depending RESET source 4096 clock cycle delay RESET vector fetch Figure Reset Block Diagram 4096 clock cycle delay allows oscillator stabilise ensures that recovery taken place from Reset state. RESET vector fetch phase duration clock cycles. Figure RESET Sequence Phase
RESET
DELAY INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR
fCPU
COUNTER
INTERNAL RESET
RESET
WATCHDOG RESET RESET
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RESET SEQUENCE MANAGER (Cont'd) 7.2.2 Asynchronous External RESET RESET both input open-drain output with integrated weak pull-up resistor. This pull-up fixed value varies accordance with input voltage. pulled external circuitry reset device. electrical characteristics section more details. RESET signal originating from external source must have duration least h(RSTL)in order recognized. This detection asynchronous therefore enter reset state even HALT mode. RESET asynchronous signal which plays major role performance. noisy environment, recommended follow guidelines mentioned electrical characteristics section. RESET sequences associated with this RESET source: short long external reset pulse (see Figure 12). Starting from external RESET pulse recognition, device RESET acts output that pulled during least tw(RSTL)out. Figure RESET Sequences
VIT+ VIT-
7.2.3 Internal Voltage Detection RESET different RESET sequences caused internal circuitry distinguished: Power-On RESET Voltage Drop RESET device RESET acts output that pulled when VDD<VIT+ (rising edge) VDD<VIT- (falling edge) shown Figure filters spikes larger than tg(VDD) avoid parasitic resets. 7.2.4 Internal Watchdog RESET RESET sequence generated internal Watchdog counter overflow shown Figure Starting from Watchdog counter underflow, device RESET acts output that pulled during least tw(RSTL)out.
RESET
SHORT EXT. RESET
LONG EXT. RESET
WATCHDOG RESET
DELAY
DELAY
DELAY
DELAY
tw(RSTL)out th(RSTL)in
EXTERNAL RESET SOURCE
th(RSTL)in
tw(RSTL)out
RESET
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (4096 TCPU) FETCH VECTOR
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MULTI-OSCILLATOR (MO) main clock generated four different source types coming from multioscillator block: external source crystal ceramic resonator oscillators external oscillator internal high frequency oscillator Each oscillator optimized given frequency range terms consumption selectable through option byte. associated hardware configuration shown Table Refer electrical characteristics section more details. External Clock Source this external clock mode, clock signal (square, sinus triangle) with ~50% duty cycle drive OSC1 while OSC2 tied ground. Crystal/Ceramic Oscillators This family oscillators advantage producing very accurate rate main clock ST7. selection within list oscillators with different frequency ranges done option byte order reduce consumption. this mode multi-oscillator, resonator load capacitors have placed close possible oscillator pins order minimize output distortion start-up stabilization time. loading capacitance values must adjusted according selected oscillator. These oscillators stopped during RESET phase avoid losing time oscillator start-up phase. External Oscillator This oscillator allows cost solution main clock using only external resistor external capacitor. frequency external oscillator range some MHz.) fixed resistor capacitor values. Consequently this mode, accuracy clock directly linked accuracy discrete components. Internal Oscillator internal oscillator mode based same principle external oscillator including resistance capacitance device. This mode most cost effective with drawback lower frequency accuracy. frequency range several MHz. this mode, oscillator pins have tied ground. Table Clock SourceHardware Configuration
External Clock
OSC1 OSC2
EXTERNAL SOURCE
Crystal/Ceramic Resonator
OSC1 OSC2
LOAD CAPACITORS
OSC1 OSC2
External Oscillator
Internal Oscillator
OSC1 OSC2
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CLOCK SECURITY SYSTEM (CSS) Clock Security System (CSS) protects against main clock problems. allow integration security features applications, based clock filter control Internal safe oscillator. enabled disabled option byte. 7.4.1 Clock Filter Control clock filter based clock frequency limitation function. This filter function able detect filter high frequency spikes main clock. oscillator working properly (e.g. working harmonic frequency resonator), current active oscillator clock totally filtered, then clock signal available from this oscillator anymore. original clock source recovers, filtering stopped automatically oscillator supplies clock. 7.4.2 Safe Oscillator Control safe oscillator block frequency back-up clock source (see Figure 13). clock signal disappears (due broken disconnected resonator.) during safe oscillator period, safe oscillator delivers frequency clock signal which allows perform some rescue operations. Automatically, clock source switches back from safe oscillator original clock source recovers. Limitation detection automatic safe oscillator selection notified hardware setting CSSD CRSR register. interrupt generated CSSIE been previously set. These bits described CRSR register description. 7.4.3 Power ModeMode WAIT Description effect CSS. interrupt cause device exit from Wait mode. CRSR register frozen. (including safe oscillator) disabled until HALT mode exited. previous configuration resumes when woken interrupt with "exit from HALT mode" capability from counter reset value when woken RESET.
HALT
7.4.4 Interrupts interrupt event generates interrupt corresponding Enable Control (CSSIE) interrupt mask register reset (RIM instruction).
Interrupt Event Enable Event Control Flag CSSIE Exit from Wait Exit from Halt1)
event detection (safe oscillator acti- CSSD vated main clock)
Note This interrupt allows exit from active-halt mode this mode available MCU. Figure Clock Filter Function Safe Oscillator Function
CLOCK FILTER FUNCTION
fOSC/2 fCPU
SAFE OSCILLATOR FUNCTION
fOSC/2 fSFOSC fCPU
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CLOCK RESET SUPPLY REGISTER DESCRIPTION (CRSR) Read /Write Reset Value: 000x 000x (XXh)
Reserved, always read LVDRF reset flag This indicates that last RESET generated block. hardware (LVD reset) cleared software (writing zero). WDGRF flag description more details. When disabled option byte, LVDRF value undefined. Reserved, always read CSSIE Clock security syst interrupt enable This enables interrupt when disturbance detected clock security system (CSSD set). cleared software. Clock security system interrupt disabled Clock security system interrupt enabled Refer Table "Interrupt Mapping," page more details interrupt vector. When disabled option byte, CSSIE effect.
CSSD Clock security system detection This indicates that safe oscillator clock security system block been selected hardware disturbance main clock signal (fOSC). hardware cleared reading CRSR register when original oscillator recovers. Safe oscillator active Safe oscillator been activated When disabled option byte, CSSD value forced WDGRF Watchdog reset flag This indicates that last RESET generated watchdog peripheral. hardware (Watchdog RESET) cleared software (writing zero) RESET ensure stable cleared state WDGRF flag when starts). Combined with LVDRF flag information, flag description given following table.
RESET Sources External RESET Watchdog LVDRF WDGRF
Application notes LVDRF flag cleared when another RESET type occurs (external watchdog), LVDRF flag remains keep trace original failure. this case, watchdog reset detected software while external reset not.
Table Clock, Reset Supply Register Reset ValueAddress (Hex.) 0025h Register Label CRSR Reset Value LVDRF CSSIE CSSD WDGRF
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MAIN CLOCK CONTROLLER (MCC) Main Clock Controller (MCC) supplies clock internal peripherals. allows SLOW power saving mode managed application. functions managed Miscellaneous register (MISCR1). block consists programmable clock prescaler clock-out signal supply external devices prescaler allows selection main clock frequency controlled three bits MISCR1: CP1, SMS. clock-out capability consists dedicated port configurable fCPU clock output drive external devices. controlled MISCR1 register. Section "MISCELLANEOUS REGISTERS" page more details.
Figure Main Clock Controller (MCC) Block Diagram
CLOCK PERIPHERAL PORT ALTERNATE FUNCTION fOSC/2 MISCR1
fOSC
fCPU
CLOCK PERIPHERALS
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INTERRUPTS
core interrupted different methods: maskable hardware interrupts listed Interrupt Mapping Table nonmaskable software interrupt (TRAP). Interrupt processing flowchart shown Figure maskable interrupts must enabled clearing order serviced. However, disabled interrupts latched processed when they enabled (see external interrupts subsection). When interrupt serviced: Normal processing suspended current instruction execution. registers saved onto stack. register prevent additional interrupts. then loaded with interrupt vector interrupt service first instruction interrupt service routine fetched (refer Interrupt Mapping Table vector addresses). interrupt service routine should finish with IRET instruction which causes contents saved registers recovered from stack. Note: consequence IRET instruction, will cleared main program will resume. Priority Management default, servicing interrupt cannot interrupted because hardware entering interrupt routine. case when several interrupts simultaneously pending, hardware priority defines which will serviced first (see Interrupt Mapping Table). Interrupts Power Mode interrupts allow processor leave WAIT power mode. Only external specifically mentioned interrupts allow processor leave HALT power mode (refer "Exit from HALT" column Interrupt Mapping Table). MASKABLE SOFTWARE INTERRUPT This interrupt entered when TRAP instruction executed regardless state bit. will serviced according flowchart Figure EXTERNAL INTERRUPTS External interrupt vectors loaded into register corresponding external interrupt occurred cleared. These interrupts allow processor leave Halt power mode. external interrupt polarity selected through miscellaneous register interrupt register available). external interrupt triggered edge will latched interrupt request automatically cleared upon entering interrupt service routine. several input pins, connected same interrupt vector, configured interrupts, their signals logically ANDed before entering edge/ level detection block. Caution: type sensitivity defined Miscellaneous Interrupt register available) applies source. case ANDed source described ports section), level configured input with interrupt, masks interrupt request even case risingedge sensitivity. PERIPHERAL INTERRUPTS Different peripheral interrupt flags status register able cause interrupt when they active both: register cleared. corresponding enable control register. these conditions false, interrupt latched thus remains pending. Clearing interrupt request done Writing corresponding status register Access status register while flag followed read write associated register. Note: clearing sequence resets internal latch. pending interrupt (i.e. waiting being enabled) will therefore lost clear sequence executed.
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INTERRUPTS (Cont'd) Figure Interrupt Processing Flowchart
FROM RESET SET?
INTERRUPT PENDING?
FETCH NEXT INSTRUCTION
IRET?
STACK LOAD FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE FROM STACK THIS CLEARS DEFAULT
Table Interrupt Mapping
Source Block RESET TRAP TIMER TIMER Reset Software Interrupt External Interrupt Port A7.0 (C5.01) External Interrupt Port B7.0 Peripheral Interrupts TIMER Peripheral Interrupts used TIMER Peripheral Interrupts used used used used Peripheral Interrupt Used Used I2CSRx Lowest Priority TBSR (C5.01) CRSR SPISR TASR Clock Security System Interrupt Description Register Label Priority Order Highest Priority Exit from HALT Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
Note Configurable option byte.
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POWER SAVING MODES
INTRODUCTION give large measure flexibility application terms power consumption, three main power saving modes implemented (see Figure 16). After RESET normal operating mode selected default (RUN mode). This mode drives device (CPU embedded peripherals) means master clock which based main oscillator frequency divided CPU). From mode, different power saving modes selected setting relevant register bits calling specific software instruction whose action depends oscillator status. Figure Power Saving Mode TransitionHigh
fCPU
SLOW MODE This mode targets: reduce power consumption decreasing internal clock device, adapt internal clock frequency (fCPU) available supply voltage. SLOW mode controlled three bits MISCR1 register: which enables disables Slow mode bits which select internal slow frequency (fCPU). this mode, oscillator frequency divided instead normal operating mode. peripherals clocked this lower frequency. Note: SLOW-WAIT mode activated when entering WAIT mode while device already SLOW mode. Figure SLOW Mode Clock TransitionfOSC/4 fOSC/8 fOSC/2
SLOW
fOSC/2 MISCR1
WAIT SLOW WAIT HALT POWER CONSUMPTION
CP1:0
SLOW FREQUENCY REQUEST
NORMAL MODE REQUEST
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POWER SAVING MODES (Cont'd) WAIT MODE WAIT mode places power consumption mode stopping CPU. This power saving mode selected calling "WFI" software instruction. peripherals remain active. During WAIT mode, register forced enable interrupts. other registers memory remain unchanged. remains WAIT mode until interrupt Reset occurs, whereupon Program Counter branches starting address interrupt Reset service routine. will remain WAIT mode until Reset Interrupt occurs, causing wake Refer Figure Figure WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS
INSTRUCTION
RESET INTERRUPT OSCILLATOR PERIPHERALS
4096 CLOCK CYCLE DELAY
OSCILLATOR PERIPHERALS
FETCH RESET VECTOR SERVICE INTERRUPT
Note: Before servicing interrupt, register pushed stack. register during interrupt routine cleared when register popped.
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POWER SAVING MODES (Cont'd) HALT MODE HALT mode lowest power consumption mode MCU. entered executing HALT instruction (see Figure 20). exit HALT mode reception either specific interrupt (see Table "Interrupt Mapping," page RESET. When exiting HALT mode means RESET interrupt, oscillator immediately turned 4096 cycle delay used stabilize oscillator. After start delay, resumes operation servicing interrupt fetching reset vector which woke (see Figure 19). When entering HALT mode, register forced enable interrupts. Therefore, interrupt pending, wakes immediately. HALT mode main oscillator turned causing internal processing stopped, including operation on-chip peripherals. peripherals clocked except ones which their clock supply from another clock generator (such external auxiliary oscillator). compatibility Watchdog operation with HALT mode configured "WDGHALT" option option byte. HALT instruction when executed while Watchdog system enabled, generate Watchdog RESET (see Section 16.1 "OPTION BYTES" page more details). Figure HALT Mode Timing Overview
HALT 4096 CYCLE DELAY
FETCH RESET VECTOR SERVICE INTERRUPT
Figure HALT Mode Flow-chart
HALT INSTRUCTION ENABLE WDGHALT WATCHDOG RESET OSCILLATOR PERIPHERALS WATCHDOG DISABLE
RESET INTERRUPT OSCILLATOR PERIPHERALS
4096 CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS
HALT INSTRUCTION
RESET INTERRUPT
FETCH VECTOR
Notes: WDGHALT option bit. option byte section more details. Peripheral clocked with external clock source still active. Only some specific interrupts exit from HALT mode (such external interrupt). Refer Table "Interrupt Mapping," page more details. Before servicing interrupt, register pushed stack. register during interrupt routine cleared when register popped.
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PORTS
10.1 INTRODUCTION ports offer different functional modes: transfer data through digital inputs outputs specific pins: external interrupt generation alternate signal input/output on-chip peripherals. port contains pins. Each programmed independently digital input (with without interrupt generation) digital output. 10.2 FUNCTIONAL DESCRIPTION Each port main registers: Data Register (DR) Data Direction Register (DDR) optional register: Option Register (OR) Each programmed using corresponding register bits registers: corresponding port. same correspondence used register. following description takes into account register, (for specific ports which provide this register refer Port Implementation section). generic block diagram shown Figure 10.2.1 Input Modes input configuration selected clearing corresponding register bit. this case, reading register returns digital value applied external pin. Different input modes selected software through register. Notes: Writing register modifies latch value does affect status. When switching from input output mode, register written first drive correct level soon port configured output. External interrupt function When configured Input with Interrupt, event this generate external interrupt request CPU. Each independently generate interrupt request. interrupt sensitivity independently programmable using sensitivity bits Miscellaneous register. Each external interrupt vector linked dedicated group port pins (see pinout description interrupt section). several input pins selected simultaneously interrupt source, these logically ANDed. this reason interrupt pins tied low, masks other ones. case floating input with interrupt configuration, special care must taken when changing configuration (see Figure 22). external interrupts hardware interrupts, which means that request latch (not accessible directly application) automatically cleared when corresponding interrupt vector fetched. clear unwanted pending interrupt software, sensitivity bits Miscellaneous register must modified. 10.2.2 Output Modes output configuration selected setting corresponding register bit. this case, writing register applies this digital value through latch. Then reading register returns previously stored value. different output modes selected software through register: Output push-pull open-drain. register value output status:
Push-pull Open-drain Floating
10.2.3 Alternate Functions When on-chip peripheral configured pin, alternate function automatically selected. This alternate function takes priority over standard programming. When signal coming from on-chip peripheral, automatically configured output mode (push-pull open drain according peripheral). When signal going on-chip peripheral, must configured input mode. this case, state also digitally readable addressing register. Note: Input pull-up configuration cause unexpected value input alternate peripheral input. When on-chip peripheral input output, this configured input floating mode.
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PORTS (Cont'd) Figure Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT ALTERNATE ENABLE
P-BUFFER (see table below) PULL-UP (see table below)
PULL-UP CONFIGURATION implemented N-BUFFER CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below)
EXTERNAL INTERRUPT SOURCE (eix)
Table Port Mode OptionConfiguration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up P-Buffer Diodes
Output
Legend: implemented implemented activated implemented activated
DATA
ALTERNATE INPUT FROM OTHER BITS
POLARITY SELECTION
(see note)
Note: diode implemented true open drain pads. local protection between implemented protect device against positive stress.
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PORTS (Cont'd) Table Port ConfigurationHardware Configuration
IMPLEMENTED TRUE OPEN DRAIN PORTS PULL-UP CONFIGURATION REGISTER ACCESS
REGISTER
DATA
INPUT
ALTERNATE INPUT FROM OTHER PINS INTERRUPT CONFIGURATION POLARITY SELECTION ANALOG INPUT IMPLEMENTED TRUE OPEN DRAIN PORTS
EXTERNAL INTERRUPT SOURCE (eix)
OPEN-DRAIN OUTPUT
REGISTER ACCESS
REGISTER
DATA
ALTERNATE ENABLE
ALTERNATE OUTPUT
PUSH-PULL OUTPUT
IMPLEMENTED TRUE OPEN DRAIN PORTS
REGISTER ACCESS
REGISTER
DATA
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: When port input configuration associated alternate function enabled output, reading register will read alternate function output status. When port output configuration associated alternate function enabled input, alternate function reads status given register content.
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PORTS (Cont'd) CAUTION: alternate function must activated long configured input with interrupt, order avoid generating spurious interrupts. Analog alternate function When used input, must configured floating input. analog multiplexer (controlled registers) switches analog voltage present selected common analog rail which connected input. recommended change voltage level loading port while conversion progress. Furthermore recommended have clocking pins located close selected analog pin. WARNING: analog input voltage level must within limits stated absolute maximum ratings. 10.3 PORT IMPLEMENTATION hardware implementation each port depends settings registers specific feature port such Input true open drain. Switching these ports from state another should done sequence that prevents unwanted side effects. Recommended safe transitions illustrated Figure Other transitions potentially risky should avoided, since they likely present unwanted side-effects such spurious interrupt generation. Table Port Configuration
Input (DDR Port name PA3:0 PB7:0 PC7:0 floating floating floating floating floating floating floating
Figure Interrupt Port State Transition01
INPUT floating/pull-up interrupt
INPUT floating (reset state)
OUTPUT open-drain
OUTPUT push-pull
DDR,
port register configurations summarized follows. Interrupt Ports PA7, PA5, PA3:0, PB7:0, PC5:0 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output
True Open Drain Interrupt Ports PA6, (without pull-up)
MODE floating input floating interrupt input open drain (high sink ports)
Output (DDR High-Sink
Port
Port Port
pull-up interrupt floating interrupt pull-up interrupt floating interrupt pull-up interrupt pull-up interrupt pull-up interrupt
open drain push-pull true open-drain open drain push-pull true open-drain open drain push-pull open drain push-pull open drain push-pull
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PORTS (Cont'd) 10.4 POWER MODES
Mode WAIT HALT Description effect ports. External interrupts cause device exit from WAIT mode. effect ports. External interrupts cause device exit from HALT mode.
DATA DIRECTION REGISTER (DDR) Port Data Direction Register PxDDR with Read /Write Reset Value: 0000 0000 (00h)
10.5 INTERRUPTS external interrupt event generates interrupt corresponding configuration selected with registers I-bit register reset (RIM instruction).
Interrupt Event External interrupt selected external event Enable Event Control Flag DDRx Exit from Wait Exit from Halt
DD[7:0] Data direction register bits. register gives input/output direction configuration pins. Each cleared software. Input mode Output mode OPTION REGISTER (OR) Port Option Register PxOR with Read /Write Reset Value: 0000 0000 (00h)
10.6 REGISTER DESCRIPTION DATA REGISTER (DR) Port Data Register PxDR with Read /Write Reset Value: 0000 0000 (00h)
D[7:0] Data register bits. register specific behaviour according selected input/output configuration. Writing register always taken into account even configured input; this allows always having expected level when toggling output mode. Reading register returns either register latch content (pin configured output) digital value applied (pin configured input).
O[7:0] Option register bits. specific pins, this register implemented. this case register enough select configuration. register allows distinguish: input mode pull-up with interrupt capability basic pull-up configuration selected, output mode push-pull open drain configuration selected. Each cleared software. Input mode: Floating input Pull-up input with without interrupt Output mode: Output open drain (with P-Buffer deactivated) Output push-pull (when available)
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PORTS (Cont'd) Table Port Register Reset ValueAddress (Hex.) Register Label
Reset Value port registers 0000h 0001h 0002h 0004h 0005h 0006h 0008h 0009h 000Ah PCDR PCDDR PCOR PBDR PBDDR PBOR PADR PADDR PAOR
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MISCELLANEOUS REGISTERS
miscellaneous registers allow control over several different features such external interrupts alternate functions. 11.1 PORT INTERRUPT SENSITIVITY external interrupt sensitivity controlled ISxx bits Miscellaneous register OPTION BYTE. This control allows having fully independent external interrupt source sensitivities with configurable sources (using EXTIT option bit) shown Figure Figure Each external interrupt source generated four different events pin: Falling edge Rising edge Falling rising edge Falling edge level guarantee correct functionality, sensitivity bits MISCR1 register must modified only when register (interrupt masked). port register Miscellaneous register descriptions more details programming.
Figure Ext. Interrupt Sensitivity (EXTIT=0)
MISCR1 INTERRUPT SOURCE IS00 IS01
SENSITIVITY CONTROL
MISCR1 INTERRUPT SOURCE IS10 IS11
SENSITIVITY CONTROL
Figure Ext. Interrupt Sensitivity (EXTIT=1)
MISCR1 INTERRUPT SOURCE IS00 IS01
SENSITIVITY CONTROL
11.2 PORT ALTERNATE FUNCTIONS MISCR registers manage four port miscellaneous alternate functions: Main clock signal (fCPU) output configuration: internal control port function while active. Master output capability MOSI (PB4) deactivated while active. Slave output capability MISO (PB5) deactivated while active. These functions described detail Section 11.3 "MISCELLANEOUS REGISTER DESCRIPTION" page
INTERRUPT SOURCE
MISCR1 IS10 IS11
SENSITIVITY CONTROL
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MISCELLANEOUS REGISTERS (Cont'd) 11.3 MISCELLANEOUS REGISTER DESCRIPTION MISCELLANEOUS REGISTER (MISCR1) Read /Write Reset Value: 0000 0000 (00h)
IS11 IS10 IS01 IS00 fCPU SLOW mode fOSC fOSC fOSC
CP[1:0] clock prescaler These bits select clock prescaler which applied different slow modes. Their action conditioned setting bit. These bits cleared software
IS1[1:0] sensitivity interrupt sensitivity, defined using IS1[1:0] bits, applied external interrupts. These bits written only when register (interrupt masked). ei1: Port optional)
External Interrupt Sensitivity Falling edge level Rising edge only Falling edge only Rising falling edge IS11 IS10
fOSC
Slow mode select This cleared software. Normal mode. fCPU fOSC Slow mode. fCPU given CP1, power consumption mode chapters more details.
Main clock selection This enables alternate function port. cleared software. alternate function disabled (I/O free general-purpose I/O) alternate function enabled port) IS0[1:0] sensitivity interrupt sensitivity, defined using IS0[1:0] bits, applied external interrupts. These bits written only when register (interrupt masked). ei0: Port optional)
External Interrupt Sensitivity Falling edge level Rising edge only Falling edge only Rising falling edge IS01 IS00
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MISCELLANEOUS REGISTERS (Cont'd) MISCELLANEOUS REGISTER (MISCR2) Read /Write Reset Value: 0000 0000 (00h)
Reserved always read Master Output Disable This cleared software. When set, disables Master (MOSI) output signal. Master Output enabled. Master Output disabled. Slave Output Disable This cleared software. When disable Slave (MISO) output signal. Slave Output enabled. Slave Output disabled. mode selection This cleared software. Normal mode level signal input from external pin. mode, level signal read from bit. internal mode This replaces when (see description). cleared software.
Table Miscellaneous Register Reset ValueAddress (Hex.) 0020h 0040h Register Label MISCR1 Reset Value MISCR2 Reset Value IS11 IS10 IS01 IS00
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ON-CHIP PERIPHERALS
12.1 WATCHDOG TIMER (WDG) 12.1.1 Introduction Watchdog timer used detect occurrence software fault, usually generated external interference unforeseen logical conditions, which causes application program abandon normal sequence. Watchdog circuit generates reset expiry programmed time period, unless program refreshes counter's contents before becomes cleared. 12.1.2 Main Features Programmable timer increments 12288 cycles) Programmable reset Reset watchdog activated) when reaches zero Optional reset HALT instruction (configurable option byte) Hardware Watchdog selectable option byte. 12.1.3 Functional Description counter value stored register (bits T6:T0), decremented every 12,288 machine cyFigure Watchdog Block Diagram cles, length timeout period programmed user increments. watchdog activated (the WDGA set) when 7-bit timer (bits T6:T0) rolls over from becomes cleared), initiates reset cycle pulling reset typically 500ns. application program must write register regular intervals during normal operation prevent reset. value stored register must between (see Table Watchdog Timing (fCPU MHz)): WDGA (watchdog enabled) prevent generating immediate reset T5:T0 bits contain number increments which represents time delay before watchdog produces reset.
RESET
WATCHDOG CONTROL REGISTER (CR) WDGA
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER ÷12288
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WATCHDOG TIMER (Cont'd) Table Watchdog Timing (fCPU MHz)
Register initial value timeout period (ms) 98.304 1.536
Notes: Following reset, watchdog disabled. Once activated cannot disabled, except reset. used generate software reset (the WDGA cleared). 12.1.4 Hardware Watchdog Option Hardware Watchdog selected option byte, watchdog always active WDGA used. Refer device-specific Option Byte description. 12.1.5 Power Modes WAIT Instruction effect Watchdog. HALT Instruction Watchdog reset HALT option selected option byte, HALT instruction causes immediate reset generation Watchdog activated (WDGA set). 12.1.5.1 Using Halt Mode with (option) Watchdog reset HALT option selected option byte, Halt mode used when watchdog enabled. this case, HALT instruction stops oscillator. When oscillator stopped, stops counting longer able generate reset until microcontroller receives external interrupt reset. external interrupt received, restarts counting after 4096 clocks. reset generated, disabled (reset state). Recommendations Make sure that external event available wake microcontroller from Halt mode. Before executing HALT instruction, refresh counter, avoid unexpected
reset immediately after waking microcontroller. When using external interrupt wake microcontroller, reinitialize corresponding "Input Pull-up with Interrupt" before executing HALT instruction. main reason this that wrongly configured external interference unforeseen logical condition. same reason, reinitialize level sensitiveness each external interrupt precautionary measure. opcode HALT instruction 0x8E. avoid unexpected HALT instruction program counter failure, advised clear occurrences data value 0x8E from memory. example, avoid defining constant with value 0x8E. HALT instruction clears register allow interrupts, user choose clear pending interrupt bits before executing HALT instruction. This avoids entering other peripheral interrupt routines after executing external interrupt routine corresponding wake-up event (reset external interrupt). 12.1.6 Interrupts None. 12.1.7 Register Description CONTROL REGISTER (CR) Read /Write Reset Value: 0111 1111 (7Fh)
WDGA
WDGA Activation bit. This software only cleared hardware after reset. When WDGA watchdog generate reset. Watchdog disabled Watchdog enabled T[6:0] 7-bit timer (MSB LSB). These bits contain decremented value. reset produced when rolls over from becomes cleared).
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WATCHDOG TIMER (Cont'd) Table Watchdog Timer Register Reset ValueAddress (Hex.) 0024h Register Label WDGCR Reset Value WDGA
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12.2 16-BIT TIMER 12.2.1 Introduction timer consists 16-bit free-running counter driven programmable prescaler. used variety purposes, including measuring pulse lengths input signals input capture) generating output waveforms (output compare Pulse lengths waveform periods modulated from microseconds several milliseconds using timer prescaler clock prescaler. Some devices have on-chip 16-bit timers. They completely independent, share resources. They synchronized after reset long timer clock frequencies modified. This description covers 16-bit timers. devices with timers, register names prefixed with (Timer (Timer 12.2.2 Main Features Programmable prescaler: fCPU divided Overflow status flag maskable interrupt External clock input (must least times slower than clock speed) with choice active edge Output compare functions with: dedicated 16-bit registers dedicated programmable signals dedicated status flags dedicated maskable interrupt Input capture functions with: dedicated 16-bit registers dedicated active edge selection signals dedicated status flags dedicated maskable interrupt Pulse Width Modulation mode (PWM) Pulse mode alternate functions ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* Block Diagram shown Figure *Note: Some timer pins available (not bonded) some devices. Refer device description. When reading input signal non-bonded pin, value will always `1'. 12.2.3 Functional Description 12.2.3.1 Counter main block Programmable Timer 16-bit free running upcounter associated 16-bit registers. 16-bit registers made 8-bit registers called high low. Counter Register (CR): Counter High Register (CHR) most significant byte Byte). Counter Register (CLR) least significant byte Byte). Alternate Counter Register (ACR) Alternate Counter High Register (ACHR) most significant byte Byte). Alternate Counter Register (ACLR) least significant byte Byte). These read-only 16-bit registers contain same value with difference that reading ACLR register does clear (Timer overflow flag), located Status register (SR). (See note paragraph titled 16-bit read sequence). Writing register ACLR register resets free running counter FFFCh value. Both counters have reset value FFFCh (this only value which reloaded 16-bit timer). reset value both counters also FFFCh Pulse mode mode. timer clock depends clock control bits register, illustrated Table Clock Control Bits. value counter register repeats every 131.072, 262.144 524.288 clock cycles depending CC[1:0] bits. timer frequency fCPU/2, fCPU/4, fCPU/8 external frequency.
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16-BIT TIMER (Cont'd) Figure Timer Block Diagram
INTERNAL fCPU MCU-PERIPHERAL INTERFACE
high
8-bit buffer
high
high
high
high
EXEDG
EXTCLK COUNTER REGISTER ALTERNATE COUNTER REGISTER OUTPUT COMPARE REGISTER OUTPUT COMPARE REGISTER INPUT CAPTURE REGISTER INPUT CAPTURE REGISTER
CC[1:0] TIMER INTERNAL OVERFLOW DETECT CIRCUIT
OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT1
ICAP1
EDGE DETECT CIRCUIT2
ICAP2
LATCH1
ICF1 OCF1 ICF2 OCF2
OCMP1 OCMP2
LATCH2
(Status Register)
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E
IEDG2 EXEDG
(Control Register
(Control Register
(See note) TIMER INTERRUPT
Note: interrupt requests have separate vectors then last present (See device Interrupt Vector Table)
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16-BIT TIMER (Cont'd) 16-bit Read Sequence: (from either Counter Register Alternate Counter Register).
Beginning sequence
Read Byte Other instructions Read Byte
Returns buffered
Byte buffered
Byte value
Sequence completed
user must read Byte first, then Byte value buffered automatically. This buffered value remains unchanged until 16-bit read sequence completed, even user reads Byte several times. After complete reading sequence, only register ACLR register read, they return Byte count value time read. Whatever timer mode used (input capture, output compare, Pulse mode mode) overflow occurs when counter rolls over from FFFFh 0000h then: register set. timer interrupt generated TOIE register register cleared. these conditions false, interrupt remains pending issued soon they both true.
Clearing overflow interrupt request done steps: Reading register while set. access (read write) register. Note: cleared accessing ACLR register. advantage accessing ACLR register rather than register that allows simultaneous overflow function reading free running counter random times (for example, measure elapsed time) without risk clearing erroneously. timer affected WAIT mode. HALT mode, counter stops counting until mode exited. Counting then resumes from previous count (MCU awakened interrupt) from reset count (MCU awakened Reset). 12.2.3.2 External Clock external clock (where available) selected CC0=1 CC1=1 register. status EXEDG register determines type level transition external clock EXTCLK that will trigger free running counter. counter synchronised with falling edge internal clock. minimum four falling edges clock must occur between consecutive active edges external clock; thus external clock frequency must less than quarter clock frequency.
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16-BIT TIMER (Cont'd) Figure Counter Timing Diagram, internal clock divided
CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure Counter Timing Diagram, internal clock divided
CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure Counter Timing Diagram, internal clock divided
CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000
TIMER OVERFLOW FLAG (TOF)
Note: reset state when internal reset signal high. When low, running.
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16-BIT TIMER (Cont'd) 12.2.3.3 Input Capture this section, index, because there input capture functions 16-bit timer. input capture 16-bit registers (IC1R IC2R) used latch value free running counter after transition detected ICAP (see figure
ICiR Byte ICiHR Byte ICiLR
ICiR register read-only register. active transition software programmable through IEDGi Control Registers (CRi). Timing resolution count free running counter: (fCPU/CC[1:0]). Procedure: input capture function, select following register: Select timer clock (CC[1:0]) (see Table Clock Control Bits). Select edge active transition ICAP2 with IEDG2 (the ICAP2 must configured floating input). select following register: ICIE generate interrupt after input capture coming from either ICAP1 ICAP2 Select edge active transition ICAP1 with IEDG1 (the ICAP1pin must configured floating input).
When input capture occurs: ICFi set. ICiR register contains value free running counter active transition ICAPi (see Figure 31). timer interrupt generated ICIE cleared register. Otherwise, interrupt remains pending until both conditions become true. Clearing Input Capture interrupt request (i.e. clearing ICFi bit) done steps: Reading register while ICFi set. access (read write) ICiLR register. Notes: After reading ICiHR register, transfer input capture data inhibited ICFi will never until ICiLR register also read. ICiR register contains free running counter value which corresponds most recent input capture. input capture functions used together even timer also uses output compare functions. Pulse mode mode only input capture function used. alternate inputs (ICAP1 ICAP2) always directly connected timer. transitions these pins activate input capture function. Moreover ICAPi configured input second output, interrupt generated user toggles output ICIE set. This avoided input capture function disabled reading (see note used with interrupt order measure events that exceed timer range (FFFFh).
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16-BIT TIMER (Cont'd) Figure Input Capture Block Diagram
ICAP1 ICAP2 EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register
IEDG1
(Status Register) IC2R Register IC1R Register
ICF1 ICF2
16-BIT
(Control Register
IEDG2
16-BIT FREE RUNNING
COUNTER
Figure Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi ICAPi FLAG ICAPi REGISTER Note: Active edge rising edge. FF03 FF01 FF02 FF03
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16-BIT TIMER (Cont'd) 12.2.3.4 Output Compare this section, index, because there output compare functions 16-bit timer. This function used control output waveform indicate when period time elapsed. When match found between Output Compare register free running counter, output compare function: Assigns pins with programmable value OCIE Sets flag status register Generates interrupt enabled 16-bit registers Output Compare Register (OC1R) Output Compare Register (OC2R) contain value compared counter register each timer clock cycle.
OCiR Byte OCiHR Byte OCiLR
OCMP takes OLVLi value (OCMPi latch forced during reset). timer interrupt generated OCIE register cleared register (CC). OCiR register value required specific timing application calculated using following formula:
OCiR
fCPU
PRESC
Where: Output compare period seconds) fCPU clock frequency hertz) PRESC Timer prescaler factor depending CC[1:0] bits, Table Clock Control Bits) timer clock external clock, formula
These registers readable writable affected timer hardware. reset event changes OCiR value 8000h. Timing resolution count free running counter: (fCPU/CC[1:0]). Procedure: output compare function, select following register: OCiE output needed then OCMPi dedicated output compare signal. Select timer clock (CC[1:0]) (see Table Clock Control Bits). select following register: Select OLVLi applied OCMP pins after match occurs. OCIE generate interrupt needed. When match found between OCRi register register: OCFi set.
OCiR fEXT
Where: Output compare period seconds) fEXT External timer clock frequency hertz) Clearing output compare interrupt request (i.e. clearing OCFi bit) done Reading register while OCFi set. access (read write) OCiLR register. following procedure recommended prevent OCFi from being between time read write OCiR register: Write OCiHR register (further compares inhibited). Read register (first step clearance OCFi bit, which already set). Write OCiLR register (enables output compare function clears OCFi bit).
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16-BIT TIMER (Cont'd) Notes: After processor write cycle OCiHR register, output compare function inhibited until OCiLR register also written. OCiE set, OCMPi general port OLVLi will appear when match found interrupt could generated OCIE set. When timer clock fCPU/2, OCFi OCMPi while counter value equals OCiR register value (see Figure page 53). This behaviour same mode. When timer clock fCPU/4, fCPU/8 external clock mode, OCFi OCMPi while counter value equals OCiR register value plus (see Figure page 53). output compare functions used both generating external events OCMPi pins even input capture mode also used. value 16-bit OCiR register OLVi should changed after each successful comparison order control output waveform establish elapsed timeout. Figure Output Compare Block Diagram
Forced Compare Output capability When FOLVi software, OLVLi copied OCMPi pin. OLVi toggled order toggle OCMPi when enabled (OCiE bit=1). OCFi then hardware, thus interrupt request generated. FOLVLi bits have effect either One-Pulse mode mode.
FREE RUNNING COUNTER
OC1E OC2E
16-bit
OUTPUT COMPARE CIRCUIT
(Control Register (Control Register
OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch
OCMP1 OCMP2
16-bit
16-bit
OC1R Register
OCF1 OCF2
Latch
OC2R Register (Status Register)
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16-BIT TIMER (Cont'd) Figure Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER (OCRi) OUTPUT COMPARE FLAG (OCFi) OCMPi (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER (OCRi) COMPARE REGISTER LATCH OUTPUT COMPARE FLAG (OCFi) OCMPi (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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16-BIT TIMER (Cont'd) 12.2.3.5 Pulse Mode Pulse mode enables generation pulse when external event occurs. This mode selected register. Pulse mode uses Input Capture1 function Output Compare1 function. Procedure: Pulse mode: Load OC1R register with value corresponding length pulse (see formula opposite column). Select following register: Using OLVL1 bit, select level applied OCMP1 after pulse. Using OLVL2 bit, select level applied OCMP1 during pulse. Select edge active transition ICAP1 with IEDG1 (the ICAP1 must configured floating input). Select following register: OC1E bit, OCMP1 then dedicated Output Compare function. bit. Select timer clock CC[1:0] (see Table Clock Control Bits).
Clearing Input Capture interrupt request (i.e. clearing ICFi bit) done steps: Reading register while ICFi set. access (read write) ICiLR register. OC1R register value required specific timing application calculated using following formula: OCiR Value
fCPU
PRESC
Where: Pulse period seconds) fCPU clock frequency hertz) PRESC Timer prescaler factor depending CC[1:0] bits, Table Clock Control Bits) timer clock external clock formula OCiR fEXT Where: Pulse period seconds) fEXT External timer clock frequency hertz) When value counter equal value contents OC1R register, OLVL1 output OCMP1 (see Figure 35). Notes: OCF1 cannot hardware Pulse mode OCF2 generate Output Compare interrupt. When Pulse Width Modulation (PWM) Pulse mode (OPM) bits both set, mode only active one. OLVL1=OLVL2 continuous signal will seen OCMP1 pin. ICAP1 used perform input capture. ICAP2 used perform input capture (ICF2 IC2R loaded) user must take care that counter reset each time valid edge occurs ICAP1 ICF1 also generates interrupt ICIE set. When Pulse mode used OC1R dedicated this mode. Nevertheless OC2R OCF2 used indicate that period time elapsed cannot generate output waveform because OLVL2 level dedicated Pulse mode.
Pulse mode cycle
When event occurs ICAP1 OCMP1 OLVL2 Counter reset FFFCh ICF1 When Counter OC1R
OCMP1 OLVL1
Then, valid event ICAP1 pin, counter initialized FFFCh OLVL2 loaded OCMP1 pin, ICF1 value FFFDh loaded IC1R register. Because ICF1 when active edge occurs, interrupt generated ICIE set.
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16-BIT TIMER (Cont'd) Figure Pulse Mode Timing Example
COUNTER ICAP1 OCMP1
FFFC FFFD FFFE
2ED0 2ED1 2ED2 2ED3
FFFC FFFD
OLVL2
OLVL1
OLVL2
compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE OCMP1
2ED0 2ED1 2ED2
34E2
FFFC
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2=
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16-BIT TIMER (Cont'd) 12.2.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables generation signal with frequency pulse length determined value OC1R OC2R registers. Pulse Width Modulation mode uses complete Output Compare function plus OC2R register, these functions cannot used when mode activated. Procedure Pulse Width Modulation mode: Load OC2R register with value corresponding period signal using formula opposite column. Load OC1R register with value corresponding period pulse OLVL1=0 OLVL2=1, using formula opposite column. Select following register: Using OLVL1 bit, select level applied OCMP1 after successful comparison with OC1R register. Using OLVL2 bit, select level applied OCMP1 after successful comparison with OC2R register. Select following register: OC1E bit: OCMP1 then dedicated output compare function. bit. Select timer clock (CC[1:0]) (see Table Clock Control Bits). OLVL1=1 OLVL2=0, length positive pulse difference between OC2R OC1R registers. OLVL1=OLVL2 continuous signal will seen OCMP1 pin.
OCiR register value required specific timing application calculated using following formula: OCiR Value
fCPU
PRESC
Where: Signal pulse period seconds) fCPU clock frequency hertz) PRESC Timer prescaler factor depending CC[1:0] bits, Table Clock Control Bits) timer clock external clock formula OCiR fEXT Where: Signal pulse period seconds) fEXT External timer clock frequency hertz) Output Compare event causes counter initialized FFFCh (See Figure Notes: After write instruction OCiHR register, output compare function inhibited until OCiLR register also written. OCF1 OCF2 bits cannot hardware mode, therefore Output Compare interrupt inhibited. ICF1 hardware when counter reaches OC2R value produce timer interrupt ICIE cleared. mode ICAP1 used perform input capture because disconnected from timer. ICAP2 used perform input capture (ICF2 IC2R loaded) user must take care that counter reset after each period ICF1 also generate interrupt ICIE set. When Pulse Width Modulation (PWM) Pulse mode (OPM) bits both set, mode only active one.
Pulse Width Modulation cycle
When Counter OC1R
OCMP1 OLVL1
When Counter OC2R
OCMP1 OLVL2 Counter reset FFFCh ICF1
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16-BIT TIMER (Cont'd) 12.2.4 Power ModeMode WAIT Description effect 16-bit Timer. Timer interrupts cause device exit from WAIT mode. 16-bit Timer registers frozen. HALT mode, counter stops counting until Halt mode exited. Counting resumes from previous count when woken interrupt with "exit from HALT mode" capability from counter reset value when woken RESET. input capture event occurs ICAPi pin, input capture detection circuitry armed. Consequently, when woken interrupt with "exit from HALT mode" capability, ICFi set, counter value present when exiting from HALT mode captured into ICiR register.
HALT
12.2.5 InterruptInterrupt Event Input Capture event/Counter reset mode Input Capture event Output Compare event (not available mode) Output Compare event (not available mode) Timer Overflow event Event Flag ICF1 ICF2 OCF1 OCF2 Enable Control ICIE OCIE TOIE Exit from Wait Exit from Halt
Note: 16-bit Timer interrupt events connected same interrupt vector (see Interrupts chapter). These events generate interrupt corresponding Enable Control interrupt mask register reset (RIM instruction). 12.2.6 Summary Timer modeMODES Input Capture and/or Output Compare and/or Pulse mode Mode
Input Capture
AVAILABLE RESOURCES Input Capture Output Compare Output Compare Partially Recommended Recommended
note Section 12.2.3.5 "One Pulse Mode" page note Section 12.2.3.5 "One Pulse Mode" page note Section 12.2.3.6 "Pulse Width Modulation Mode" page
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16-BIT TIMER (Cont'd) 12.2.7 Register Description Each Timer associated with three control status registers, with pairs data registers (16-bit values) relating input captures, output compares, counter alternate counter. CONTROL REGISTER (CR1) Read/Write Reset Value: 0000 0000 (00h)
FOLV2 Forced Output Compare This cleared software. effect OCMP2 pin. Forces OLVL2 copied OCMP2 pin, OC2E even there successful comparison. FOLV1 Forced Output Compare This cleared software. effect OCMP1 pin. Forces OLVL1 copied OCMP1 pin, OC1E even there successful comparison. OLVL2 Output Level This copied OCMP2 whenever successful comparison occurs with OC2R register OCxE register. This value copied OCMP1 Pulse mode Pulse Width Modulation mode. IEDG1 Input Edge This determines which type level transition ICAP1 will trigger capture. falling edge triggers capture. rising edge triggers capture. OLVL1 Output Level OLVL1 copied OCMP1 whenever successful comparison occurs with OC1R register OC1E register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
ICIE Input Capture Interrupt Enable. Interrupt inhibited. timer interrupt generated whenever ICF1 ICF2 register set. OCIE Output Compare Interrupt Enable. Interrupt inhibited. timer interrupt generated whenever OCF1 OCF2 register set. TOIE Timer Overflow Interrupt Enable. Interrupt inhibited. timer interrupt enabled whenever register set.
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16-BIT TIMER (Cont'd) CONTROL REGISTER (CR2) Read/Write Reset Value: 0000 0000 (00h)
OC1E OC2E IEDG2 EXEDG
Pulse Width Modulation. mode active. mode active, OCMP1 outputs programmable cyclic signal; length pulse depends value OC1R register; period depends value OC2R register. Bits CC[1:0] Clock Control. timer clock mode depends these bits: Table Clock Control BitTimer Clock fCPU fCPU fCPU External Clock (where available)
OC1E Output Compare Enable. This used only output signal from timer OCMP1 (OLV1 Output Compare mode, both OLV1 OLV2 one-pulse mode). Whatever value OC1E bit, internal Output Compare function timer remains active. OCMP1 alternate function disabled (I/O free general-purpose I/O). OCMP1 alternate function enabled. OC2E Output Compare Enable. This used only output signal from timer OCMP2 (OLV2 Output Compare mode). Whatever value OC2E bit, internal Output Compare function timer remains active. OCMP2 alternate function disabled (I/O free general-purpose I/O). OCMP2 alternate function enabled. Pulse mode. Pulse mode active. Pulse mode active, ICAP1 used trigger pulse OCMP1 pin; active transition given IEDG1 bit. length generated pulse depends contents OC1R register.
Note: external clock available, programming external clock configuration stops counter. IEDG2 Input Edge This determines which type level transition ICAP2 will trigger capture. falling edge triggers capture. rising edge triggers capture. EXEDG External Clock Edge. This determines which type level transition external clock (EXTCLK) will trigger counter register. falling edge triggers counter register. rising edge triggers counter register.
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16-BIT TIMER (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) three least significant bits used.
ICF1 OCF1 ICF2 OCF2
INPUT CAPTURE HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This 8-bit read only register that contains high part counter value (transferred input capture event).
ICF1 Input Capture Flag input capture (reset value). input capture occurred ICAP1 counter reached OC2R value mode. clear this bit, first read register, then read write byte IC1R (IC1LR) register. OCF1 Output Compare Flag match (reset value). content free running counter matches content OC1R register. clear this bit, first read register, then read write byte OC1R (OC1LR) register. Timer Overflow Flag. timer overflow (reset value). free running counter rolled over from FFFFh 0000h. clear this bit, first read register, then read write byte (CLR) register. Note: Reading writing ACLR register does clear TOF. ICF2 Input Capture Flag input capture (reset value). input capture occurred ICAP2 pin. clear this bit, first read register, then read write byte IC2R (IC2LR) register. OCF2 Output Compare Flag match (reset value). content free running counter matches content OC2R register. clear this bit, first read register, then read write byte OC2R (OC2LR) register. Reserved, forced hardware
INPUT CAPTURE REGISTER (IC1LR) Read Only Reset Value: Undefined This 8-bit read only register that contains part counter value (transferred input capture event).
OUTPUT COMPARE HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This 8-bit register that contains high part value compared register.
OUTPUT COMPARE REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This 8-bit register that contains part value compared register.
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16-BIT TIMER (Cont'd) OUTPUT COMPARE HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This 8-bit register that contains high part value compared register.
ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This 8-bit register that contains high part counter value.
OUTPUT COMPARE REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This 8-bit register that contains part value compared register.
ALTERNATE COUNTER REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This 8-bit register that contains part counter value. write this register resets counter. access this register after access register does clear register.
COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This 8-bit register that contains high part counter value.
INPUT CAPTURE HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This 8-bit read only register that contains high part counter value (transferred Input Capture event).
COUNTER REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This 8-bit register that contains part counter value. write this register resets counter. access this register after accessing register clears bit.
INPUT CAPTURE REGISTER (IC2LR) Read Only Reset Value: Undefined This 8-bit read only register that contains part counter value (transferred Input Capture event).
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16-BIT TIMER (Cont'd) Table 16-Bit Timer Register Reset ValueAddress (Hex.) Register Label ICIE OC1E ICF1 OCIE OC2E OCF1 TOIE FOLV2 ICF2 FOLV1 OCF2 OLVL2 IEDG1 IEDG2 OLVL1 EXEDG
Timer Timer Reset Value Timer Timer Reset Value Timer Timer Reset Value Timer ICHR1 Timer Reset Value Timer ICLR1 Timer Reset Value Timer OCHR1 Timer Reset Value Timer OCLR1 Timer Reset Value Timer OCHR2 Timer Reset Value Timer OCLR2 Timer Reset Value Timer Timer Reset Value Timer Timer Reset Value Timer ACHR Timer Reset Value Timer ACLR Timer Reset Value Timer ICHR2 Timer Reset Value Timer ICLR2 Timer Reset Value
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12.3 SERIAL PERIPHERAL INTERFACE (SPI) 12.3.1 Introduction Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. system consist master more slaves system which devices either masters slaves. normally used communication between microcontroller external peripherals another microcontroller. Refer Description chapter devicespecific pin-out. 12.3.2 Main Features Full duplex, three-wire synchronous transfers Master slave operation Four master mode frequencies Maximum slave mode frequency fCPU/2. Four programmable master rates Programmable clock polarity phase transfer interrupt flag Write collision flag protection Master mode fault protection capability. 12.3.3 General description connected external devices through alternate pins: MISO: Master Slave MOSI: Master Slave SCK: Serial Clock Slave select basic example interconnections between single master single slave illustrated Figure MOSI pins connected together MISO pins. this data transferred serially between master slave (most significant first). When master device transmits data slave device MOSI pin, slave device responds sending data master device MISO pin. This implies full duplex transmission with both data data synchronized with same clock signal (which provided master device pin). Thus, byte transmitted replaced byte received eliminates need separate transmit-empty receiver-full bits. status flag used indicate that operation complete. Four possible data/clock timing relationships chosen (see Figure master slave must programmed with same timing mode.
Figure Serial Peripheral Interface Master/Slave
MASTER MSBit LSBit MISO MISO MSBit SLAVE LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
CLOCK GENERATOR
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure Serial Peripheral Interface Block Diagram
Internal Read Read Buffer
request
MOSI MISO
8-Bit Shift Register
SPIF WCOL MODF
Write STATE CONTROL
SPIE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL
SERIAL CLOCK GENERATOR
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SERIAL PERIPHERAL INTERFACE (Cont'd) 12.3.4 Functional Description Figure shows serial peripheral interface (SPI) block diagram. This interface contains dedicated registers: Control Register (CR) Status Register (SR) Data Register (DR) Refer registers Section 12.3.7for definitions. 12.3.4.1 Master Configuration master configuration, serial clock generated pin. Procedure Select SPR0 SPR1 bits define serial clock baud rate (see register). Select CPOL CPHA bits define four relationships between data transfer serial clock (see Figure 40). must connected high level signal during complete byte transmit sequence. MSTR bits must (they remain only connected high level signal).
this configuration MOSI data output MISO data input. Transmit sequence transmit sequence begins when byte written register. data byte parallel loaded into 8-bit shift register (from internal bus) during write cycle then shifted serially MOSI most significant first. When data transfer complete: SPIF hardware interrupt generated SPIE register cleared. During last clock cycle SPIF set, copy data byte received shift register moved buffer. When register read, peripheral returns this buffered value. Clearing SPIF performed following software sequence: access register while SPIF read register. Note: While SPIF set, writes register inhibited until register read.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 12.3.4.2 Slave Configuration slave configuration, serial clock received from master device. value SPR0 SPR1 bits used data transfer. Procedure correct data transfer, slave device must same timing mode master device (CPOL CPHA bits). Figure must connected level signal during complete byte transmit sequence. Clear MSTR assign pins alternate function. this configuration MOSI data input MISO data output. Transmit Sequence data byte parallel loaded into 8-bit shift register (from internal bus) during write cycle then shifted serially MISO most significant first. transmit sequence begins when slave device receives clock signal most significant data MOSI pin.
When data transfer complete: SPIF hardware interrupt generated SPIE register cleared. During last clock cycle SPIF set, copy data byte received shift register moved buffer. When register read, peripheral returns this buffered value. Clearing SPIF performed following software sequence: access register while SPIF set. read register. Notes: While SPIF set, writes register inhibited until register read. SPIF cleared during second transmission; however, must cleared before second SPIF order prevent overrun condition (see Section 12.3.4.6). Depending CPHA bit, write register between each data byte transfer avoid write collision (see Section 12.3.4.4).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 12.3.4.3 Data Transfer Format During transfer, data simultaneously transmitted (shifted serially) received (shifted serially). serial clock used synchronize data transfer during sequence eight clock pulses. allows individual selection slave device; other slave devices that selected interfere with transfer. Clock Phase Clock Polarity Four possible timing relationships chosen software, using CPOL CPHA bits. CPOL (clock polarity) controls steady state value clock when data being transferred. This affects both master slave modes. combination between CPOL CPHA (clock phase) bits selects data capture clock edge. Figure shows transfer with four combinations CPHA CPOL bits. diagram interpreted master slave timing diagram where pin, MISO pin, MOSI directly connected between master slave device. slave device select input driven master device.
master device applies data MOSI pinclock edge before capture clock edge. CPHA second edge (falling edge CPOL reset, rising edge CPOL set) MSBit capture strobe. Data latched occurrence second clock transition. write collision should occur even stays during transfer several bytes (see Figure 39). CPHA reset first edge (falling edge CPOL set, rising edge CPOL reset) MSBit capture strobe. Data latched occurrence first clock transition. must toggled high between each byte transmitted (see Figure 39). protect transmission from write collision value slave device freezes data register does allow altered. Therefore must high write data byte without producing write collision.
Figure CPHA Timing Diagram
MOSI/MISO Master Slave (CPHA=0) Slave (CPHA=1)
Byte
Byte
Byte
VR02131A
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure Data Clock Timing Diagram
CPHA
SCLK (with CPOL SCLK (with CPOL
MISO (from master) MOSI (from slave) slave)
CAPTURE STROBE
MSBit
Bit3
LSBit
MSBit
Bit3
LSBit
CPHA
CPOL
CPOL
MISO (from master) MOSI (from slave) slave)
CAPTURE STROBE
MSBit
Bit3
LSBit
MSBit
Bit3
LSBit
Note: This figure should used replacement parametric information. Refer Electrical Characteristics chapter.
VR02131B
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SERIAL PERIPHERAL INTERFACE (Cont'd) 12.3.4.4 Write Collision Error write collision occurs when software tries write register while data transfer taking place with external device. When this happens, transfer continues uninterrupted; software write will unsuccessful. Write collisions occur both master slave mode. Note: "read collision" will never occur since received data byte placed buffer which access always synchronous with operation. Slave mode When CPHA set: slave device will receive clock (SCK) edge prior latch first data transfer. This first clock edge will freeze data slave device register output MSBit external MISO slave device. state enables slave device output MSBit onto MISO does take place until first data transfer clock edge.
When CPHA reset: Data latched occurrence first clock transition. slave device does have knowing when that transition will occur; therefore, slave device collision occurs when software attempts write register after been pulled low. this reason, must high, between each data byte transfer, allow write register without generating write collision. Master mode Collision master device defined write register while internal serial clock (SCK) process transfer. signal must always high master device. WCOL WCOL register write collision occurs. interrupt generated when WCOL (the WCOL status flag only). Clearing WCOL done through software sequence (see Figure 41).
Figure Clearing WCOL (Write Collision Flag) Software Sequence Clearing sequence after SPIF (end data byte transfer) Step Read
THEN
Read
THEN
Step
Read
SPIF WCOL=0
Write
SPIF WCOL=0 transfer started WCOL=1 transfer started
before step
Clearing sequence before SPIF (during data byte transfer) Step Read
THEN
Step
Read
WCOL=0
Note: Writing register instead reading reset WCOL
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SERIAL PERIPHERAL INTERFACE (Cont'd) 12.3.4.5 Master Mode Fault Master mode fault occurs when master device pulled low, then MODF set. Master mode fault affects peripheral following ways: MODF interrupt generated SPIE set. reset. This blocks output from device disables peripheral. MSTR reset, thus forcing device into slave mode. Clearing MODF done through software sequence: read write access register while MODF set. write register. Notes: avoid multiple slave conflicts case system comprising several MCUs, must pulled high during clearing sequence MODF bit. MSTR
restored their original state during after this clearing sequence. Hardware does allow user MSTR bits while MODF except MODF clearing sequence. slave device MODF set, multi master configuration device slave mode with this MODF set. MODF indicates that there might have been multi-master conflict system control allows proper exit from system operation reset default system state using interrupt routine. 12.3.4.6 Overrun Condition overrun condition occurs when master device sent several data bytes slave device cleared SPIF issuing from previous data byte transmitted. this case, receiver buffer contains byte sent after SPIF last cleared. read register returns this byte. other bytes lost. This condition detected peripheral.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 12.3.4.7 Single Master Multimaster Configurations more security, slave device respond There types systems: master with received data byte. Then Single Master System master will receive previous byte back from Multimaster System slave device MISO MOSI pins connected slave written register. Single Master System Other transmission security methods typical single master system configured, ports handshake lines data bytes with comusing master four MCUs mand fields. slaves (see Figure 42). Multi-master System master device selects individual slave multi-master system also configured vices using four pins parallel port control user. Transfer master control could imthe four pins slave devices. plemented using handshake method through pins pulled high during reset since ports exchange code messages master device ports will forced inputs through serial peripheral interface system. that time, thus disabling slave devices. multi-master system principally handled MSTR register MODF Note: prevent conflict MISO line register. master allows only active slave device during transmission. Figure Single Master Configuration
Slave MOSI MISO Slave
Slave
Slave
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO Master Port
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SERIAL PERIPHERAL INTERFACE (Cont'd) 12.3.5 Power ModeMode WAIT HALT Description effect SPI. interrupt events cause device exit from WAIT mode. registers frozen. HALT mode, inactive. operation resumes when woken interrupt with "exit from HALT mode" capability.
12.3.6 InterruptInterrupt Event Transfer Event Master Mode Fault Event Event Flag SPIF MODF Enable Control SPIE Exit from Wait Exit from Halt
Note: interrupt events connected same interrupt vector (see Interrupts chapter). They generate interrupt corresponding Enable Control interrupt mask register reset (RIM instruction).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 12.3.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh)
SPIE SPR2 MSTR CPOL CPHA SPR1
SPR0
CPOL Clock polarity. This cleared software. This determines steady state serial Clock. CPOL affects both master slave modes. steady state value pin. steady state high value pin. CPHA Clock phase. This cleared software. first clock transition first data capture edge. second clock transition first capture edge. SPR[1:0] Serial peripheral rate. These bits cleared software.Used with SPR2 bit, they select baud rates used serial clock when device master. These bits have effect slave mode. Table Serial Peripheral Baud Rate
SPIE Serial peripheral interrupt enable. This cleared software. Interrupt inhibited interrupt generated whenever SPIF=1 MODF=1 register Serial peripheral output enable. This cleared software. also cleared hardware when, master mode, SS=0 (see Section 12.3.4.5 "Master Mode Fault" page 70). port connected pins alternate functions connected pins cleared reset, peripheral initially connected external pins. SPR2 Divider Enable. this cleared software cleared reset. used with SPR[1:0] bits baud rate. Refer Table Divider enabled Divider disabled MSTR Master. This cleared software. also cleared hardware when, master mode, SS=0 (see Section 12.3.4.5 "Master Mode Fault" page 70). Slave mode selected Master mode selected, function changes from input output functions MISO MOSI pins reversed.
Serial Clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128
SPR2
SPR1
SPR0
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SERIAL PERIPHERAL INTERFACE (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h)
SPIF WCOL MODF
DATA REGISTER (DR) Read/Write Reset Value: Undefined
SPIF Serial Peripheral data transfer flag. This hardware when transfer been completed. interrupt generated SPIE=1 register. cleared software sequence access register followed read write register). Data transfer progress been approved clearing sequence. Data transfer between device external device been completed. Note: While SPIF set, writes register inhibited. WCOL Write Collision status. This hardware when write register done during transmit sequence. cleared software sequence (see Figure 41). write collision occurred write collision been detected Unused. MODF Mode Fault flag. This hardware when pulled master mode (see Section 12.3.4.5 "Master Mode Fault" page 70). interrupt generated SPIE=1 register. This cleared software sequence access register while MODF=1 followed write register). master mode fault detected fault master mode been detected Bits Unused.
register used transmit receive data serial bus. master device only write this register will initiate transmission/reception another byte. Notes: During last clock cycle SPIF set, copy received data byte shift register moved buffer. When user reads serial peripheral data register, buffer actually being read. Warning: write register places data directly into shift register transmission. write register returns value located buffer contents shift register (See Figure
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ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont'd) Table Register Reset ValueAddress (Hex.) 0021h 0022h 0023h Register Label SPIDR Reset Value SPICR Reset Value SPISR Reset Value SPIE SPIF SPR0
WCOL
SPR2
MSTR MODF
CPOL
CPHA
SPR1
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ST72104G, ST72215G, ST72216G, ST72254G
12.4 INTERFACE (I2C) 12.4.1 Introduction Interface serves interface between microcontroller serial bus. provides both multimaster slave functions, controls bus-specific sequencing, protocol, arbitration timing. supports fast mode (400kHz). 12.4.2 Main Features Parallel-bus/I protocol converter Multi-master capability 7-bit/10-bit Addressing Transmitter/Receiver flag End-of-byte transmission flag Transfer problem detection Master Features: Clock generation busy flag Arbitration Lost Flag byte transmission flag Transmitter/Receiver Flag Start detection flag Start Stop generation Slave Features: Stop detection busy flag Detection misplaced start stop condition Programmable Address detection Transfer problem detection End-of-byte transmission flag Transmitter/Receiver flag 12.4.3 General Description addition receiving transmitting data, this interface converts from serial parallel format vice versa, using either interrupt polled Figure Protocol START CONDITION STOP CONDITION
VR02119B
handshake. interrupts enabled disabled software. interface connected data (SDAI) clock (SCLI). connected both with standard Fast bus. This selection made software. Mode Selection interface operate four following modes: Slave transmitter/receiver Master transmitter/receiver default, operates slave mode. interface automatically switches from slave master after generates START condition from master slave case arbitration loss STOP generation, allowing then Multi-Master capability. Communication Flow Master mode, initiates data transfer generates clock signal. serial data transfer always begins with start condition ends with stop condition. Both start stop conditions generated master mode software. Slave mode, interface capable recognising address 10-bit), General Call address. General Call address detection enabled disabled software. Data addresses transferred 8-bit bytes, first. first byte(s) following start condition contain address (one 7-bit mode, 10-bit mode). address always transmitted Master mode. clock pulse follows clock cycles byte transfer, during which receiver must send acknowledge transmitter. Refer Figure
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ST72104G, ST72215G, ST72216G, ST72254G
INTERFACE (Cont'd) Acknowledge enabled disabled software. interface address and/or general call address selected software. speed interface selected between Standard (0-100KHz) Fast (100400KHz). SDA/SCL Line Control Transmitter mode: interface holds clock line before transmission wait microcontroller write byte Data Register. Receiver mode: interface holds clock line after reception wait microcontroller read byte Data Register. Figure Interface Block Diagram
frequency (Fscl) controlled programmable clock divider which depends mode. When cell enabled, ports must configured floating inputs. this case, value external pull-up resistor used depends application. When cell disabled, ports revert being standard port pins.
DATA REGISTER (DR)
SDAI
DATA CONTROL DATA SHIFT REGISTER
COMPARATOR
ADDRESS REGISTER (OAR1) ADDRESS REGISTER (OAR2)
SCLI
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR) STATUS REGISTER (SR1) STATUS REGISTER (SR2) CONTROL LOGIC
INTERRUPT
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ST72104G, ST72215G, ST72216G, ST72254G
INTERFACE (Cont'd) 12.4.4 Functional Description Refer registers Section 12.4.7. definitions. default interface operates Slave mode (M/SL cleared) except when initiates transmit receive sequence. First interface frequency must configured using bits OAR2 register. 12.4.4.1 Slave Mode soon start condition detected, address received from line sent shift register; then compared with address interface General Call address selected software). Note: 10-bit addressing mode, comparision includes header sequence (11110xx0) most significant bits address. Header matched (10-bit mode only): interface generates acknowledge pulse set. Address matched: interface ignores waits another Start condition. Address matched: interface generates sequence: Acknowledge pulse set. ADSL bits with interrupt set. Then interface waits read register, holding line (see Figure Transfer sequencing EV1). Next, 7-bit mode read register determine from least significant (Data Direction Bit) slave must enter Receiver Transmitter mode. 10-bit mode, after receiving address sequence slave always receive mode. will enter transmit mode receiving repeated Start condition followed header sequence with matching address bits least significant (11110xx1) Slave Receiver Following address reception after register been read, slave receives bytes from line into register internal shift register. After each byte interface generates sequence: Acknowledge pulse
bits with interrupt set. Then interface waits read register followed read register, holding line (see Figure Transfer sequencing EV2). Slave Transmitter Following address reception after register been read, slave sends bytes from register line internal shift register. slave waits read register followed write register, holding line (see Figure Transfer sequencing EV3). When acknowledge pulse received: bits hardware with interrupt set. Closing slave communication After last data byte transferred Stop Condition generated master. interface detects this condition sets: STOPF bits with interrupt set. Then interface waits read register (see Figure Transfer sequencing EV4). Error Cases BERR: Detection Stop Start condition during byte transfer. this case, BERR bits with interrupt set. Stop then interface discards data, released lines waits another Start condition. Start then interface discards data waits next slave address bus. Detection non-acknowledge bit. this case, bits with interrupt set. Note: both cases, line held low; however, line remain possible bits transmitted last. then necessary release both lines software.
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ST72104G, ST72215G, ST72216G, ST72254G
INTERFACE (Cont'd) release lines subsequently clear STOP while set. SDA/SCL lines released after transfer current byte. 12.4.4.2 Master Mode switch from default Slave mode Master mode Start condition generation needed. Start condition Setting START while BUSY cleared causes interface switch Master mode (M/SL set) generates Start condition. Once Start condition sent: bits hardware with interrupt set. Then master waits read register followed write register with Slave address, holding line (see Figure Transfer sequencing EV5). Slave address transmission Then slave address sent line internal shift register. 7-bit addressing mode, address byte sent. 10-bit addressing mode, sending first byte including header sequence causes following event: hardware with interrupt generation set. Then master waits read register followed write register, holding line (see Figure Transfer sequencing EV9). Then second address byte sent interface.
After completion this transfer (and acknowledge from slave set): hardware with interrupt generation set. Then master waits read register followed write register (for example bit), holding line (see Figure Transfer sequencing EV6). Next master must enter Receiver Transmitter mode. Note: 10-bit addressing mode, switch master Receiver mode, software must generate repeated Start condition resend header sequence with least significant (11110xx1). Master Receiver Following address transmission after registers have been accessed, master receives bytes from line into register internal shift register. After each byte interface generates sequence: Acknowledge pulse bits hardware with interrupt set. Then interface waits read register followed read register, holding line (see Figure Transfer sequencing EV7). close communication: before reading last byte from register, STOP generate Stop condition. interface goes automatically back slave mode (M/SL cleared). Note: order generate non-acknowledge pulse after last received data byte, must cleared just before reading second last data byte.
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ST72104G, ST72215G, ST72216G, ST72254G
INTERFACE (Cont'd) Master Transmitter Following address transmission after register been read, master sends bytes from register line internal shift register. master waits read register followed write register, holding line (see Figure Transfer sequencing EV8). When acknowledge received, interface sets: bits with interrupt set. close communication: after writing last byte register, STOP generate Stop condition. interface goes automatically back slave mode (M/SL cleared). Error Cases BERR: Detection Stop Start condition during byte transfer. this case,
BERR bits hardware with interrupt set. Detection non-acknowledge bit. this case, bits hardware with interrupt set. resume, START STOP bit. ARLO: Detection arbitration lost condition. this case ARLO hardware (with interrupt interface goes automatically back slave mode (the M/SL cleared). Note: these cases, line held low; however, line remain possible bits transmitted last. then necessary release both lines s
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