CMOS Very Power, MSPS 10-Bit Analog-to-Digital Converter with 4-Channe

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CMOS Very Power, MSPS 10-Bit Analog-to-Digital Converter with 4-Channe

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MP8798
CMOS Very Power, MSPS 10-Bit Analog-to-Digital Converter with 4-Channel
10-Bit Resolution 4-Channel Sampling Rates from Very Power CMOS (typ) Power Down; Lower Consumption (typ) Input Range between Required Analog Signals less than Required Signals less than Single Power Supply Volts) Latch-Up Free High Protection: 4000 Volts Minimum Version: MP87L98
BENEFITS
Reduced Board Space (Small Package) Reduced External Parts, Sample/Hold Needed Suitable Battery Power Critical Applications Designer Adapt Input Range Scaling µP/DSP Interface Control Applications High Resolution Imaging Scanners Copiers Wireless Digital Communications Multiplexed Data Acquisition
APPLICATIONS
GENERAL DESCRIPTION
MP8798 flexible, easy use, precision 10-bit Analog-to-Digital Converter with 4-channel that operates over wide range input sampling conditions. MP8798 operate with pulsed demand" conversion operation continuous "pipeline" operation sampling rates MHz. elimination S/H, requirements, very power, small package size offer designer cost solution. sample hold required charge couple device applications, MHz, multiplexed input applications when signal source bandwidth limited kHz. input architecture MP8798 allows direct interface analog input range between AGND AVDD etc.). user simply sets VREF(+) VREF(-) encompass desired input range. Scaled reference resistor allows customizing transfer curve well providing span reference voltage. Digital outputs CMOS compatible. MP8798 uses two-step flash technique. first segment converts MSBs consists autobalanced comparators, latches, encoder, buffer storage registers. second segment converts remaining LSBs. When power down input "high", data outputs hold current values VREF(-) disconnected from VREF1(-). power consumption during power down mode approximately 3mW. Specified operation over commercial industrial (-40 +85°C) temperature range, MP8798 available plastic dual-in-line (PDIP), surface mount (SOIC), shrink small outline (SSOP) packages.
ORDERING INFORMATION
Package Type
SOIC PDIP SSOP
Temperature Range
+85°C +85°C +85°C
Part
MP8798AS MP8798AN MP8798AQ
(LSB)
(LSB)
Rev. 3.00
MP8798
SIMPLIFIED BLOCK TIMING DIAGRAM
AVDD DVDD
Coarse Comparators VREF(+) VREF(-) VREF1(-) Ladder
Adder
DB9-DB0
Fine Resolution Comparators
DB9-DB0
AIN1 AIN2 AIN3 AIN4 Decoder Latch
AGND DGND
CONFIGURATIONS
Packaging Section Package Dimensions
DGND DVDD
AVDD AGND AIN4 AIN3 AIN2 AIN1 VREF1(-) VREF(-) VREF(+)
DGND DVDD
AVDD AGND AIN4 AIN3 AIN2 AIN1 VREF1(-) VREF(-) VREF(+)
PDIP (0.300") NN28
SOIC (Jedec, 0.300") SSOP
Rev. 3.00
MP8798
DEFINITIONS
NAME DGND DVDD DESCRIPTION Data Output Data Output Data Output Data Output Data Output Digital Ground Digital Write (Active Low) Address Input Address Input Clock Input Data Output Data Output (MSB) Overflow Output NAME VREF(+) VREF(-) VREF1(-) AIN1 AIN2 AIN3 AIN4 AGND AVDD DESCRIPTION Upper Reference Voltage Lower Reference Voltage Lower Reference Voltage Reference Ladder Analog Signal Input Analog Signal Input Analog Signal Input Analog Signal Input Analog Ground Analog Power Down Data Output (LSB) Data Output Data Output
TRUTH TABLE INPUT CHANNEL SELECTION
SELECTED ANALOG INPUT AIN1 AIN2 AIN3 AIN4 Previous selection
Note: internally connected through 500k resistance.
Rev. 3.00
MP8798
ELECTRICAL CHARACTERISTICS TABLE
Unless Otherwise Specified: AVDD DVDD (50% Duty Cycle), VREF(+) 4.6, VREF(-) AGND, 25°C
Parameter FEATURES Resolution Sampling Rate ACCURACY2 Differential Non-Linearity Integral Non-Linearity Zero Scale Error Full Scale Error REFERENCE VOLTAGES Positive Ref. Voltage Negative Ref. Voltage Differential Ref. Voltage5 Ladder Resistance Ladder Temp. Coefficient1 Ladder Switch Resistance1 Ladder Switch Leakage1 ANALOG INPUT1 Input Bandwidth Input Voltage Range7 Input Capacitance3 Aperture Delay DIGITAL INPUTS Logical Voltage Logical Voltage Leakage Currents (Internal DGND) Input Capacitance Clock Timing (See TAG)1 Clock Period Rise Fall Time4 "High" Time6 "Low" Time6 1000 500,000 500,000 VIN=DGND DVDD VREF(-) VREF(+) VREF(+) VREF(-) DVREF RTCO ILKG-SW AVDD AGND AVDD ppm/°C .001 Bits Symbol 25°C Units Test Conditions/Comments
Rated Performance
+0.50 -2.5
Best Line (Max INL)/2 Reference from VREF(+) VREF(-)
2000
Rev. 3.00
MP8798
ELECTRICAL CHARACTERISTICS TABLE (CONT'D)
Parameter DIGITAL OUTPUTS Logical Voltage Logical Voltage Tristate Leakage Data Hold Time (See TAG)1 Data Valid Delay1 Write Pulse Width1 Multiplexer Address Setup Time1 Multiplexer Address Hold Time1 Delay from Multiplexer1 Enable Power Down Time1 Power Time1 POWER SUPPLIES8 Power Down (IDD) Operating Voltage (AVDD, DVDD) Current (AVDD DVDD) IPD-DD tHLD tMUXEN1 DVDD-0.5 Symbol 25°C Units Test Conditions/Comments COUT=15 ILOAD ILOAD VOUT DVDD
NOTES: Guaranteed. tested. Tester measures code transition voltages dithering voltage analog input (VIN). difference between measured code width ideal value (VREF/1024) error (see TAG). error maximum distance LSBs) from best line transition voltage (See Figure 7.). input equivalent circuit (see Figure 9.). Clock specification meet aperture specification (tAP). Actual rise/fall time less stringent with loss accuracy. Specified values guarantee functional device. Refer other parameters accuracy. System clock MP8798 with duty cycle long timing conditions met. Input range where input converted correctly into binary code. Input voltage outside specified range converts zero full scale output. DVDD AVDD connected through silicon substrate. Connect together package.
Specifications subject change without notice
ABSOLUTE MAXIMUM RATINGS +25°C unless otherwise noted)1,
GND) VREF(+) VREF(-) -0.5 +0.5 -0.5 +0.5 Inputs -0.5 +0.5 Outputs -0.5 +0.5 Storage Temperature +150°C Lead Temperature (Soldering seconds) +300°C Package Power Dissipation Rating 75°C SOIC, PDIP 1000mW Derates above 75°C 14mW/°C
NOTES: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation above this specification implied. Exposure maximum rating conditions extended periods affect device reliability. input which value outside absolute maximum ratings should protected Schottky diode clamps (HP5082-2835) from input supplies. inputs have protection diodes which will protect device from short transients outside supplies less than 100mA less than 100µs. refers AVDD DVDD. refers AGND DGND. Rev. 3.00
MP8798
CLOCK
SAMPLE AUTO BALANCE SAMPLE AUTO BALANCE SAMPLE
when disconnects latches from comparators. This delay called aperture delay (tAP). coarse comparators make first pass conversion selects ladder range fine comparators. fine comparators connected selected range during next phase.
ANALOG INPUT DATA
Latch
VTAP tHLD Ladder
COARSE COMPARATOR
Latch
Figure MP8798 Timing Diagram
VTAP
THEORY OPERATION
Analog-to-Digital Conversion
MP8798 converts analog voltages into 1024 digital codes encoding outputs coarse fine comparators. Digital logic used generate overflow bit. conversion synchronous with clock accomplished clock periods. reference resistance ladder series 1025 resistors. first last resistor ladder half value others that following relations apply: RREF 1024 VREF VREF(+) VREF(-) 1024 clock signal generates internal phases, (CLK high) (CLK sample) (See Figure 2.). rising edge input marks sampling phase (S). Internal delay clock circuitry will delay actual instant
Selected Range
FINE COMPARATOR
Figure MP8798 Comparators
Sampling, Ladder Sampling, Conversion Timing
Figure shows this relationship timing chart. sampling, ladder sampling output data relationships shown general case where levels which drive ladder need change each sampled time point. ladder referenced both last sample next sample same time. ladder's levels change more than LSB, samples must discarded. Also note that clock period discarded reduced minimum time
Hold Reference Value Past Clock Change Time
Short Cycle Sample will discarded
External Update References Clock Internal Sample Window Ladder Sample Window (MSB Bank) Ladder Compare (LSB Bank) External DATA
Settle Clock Update Time Reference Stable Time Sample AIN2 Reference Stable Time Sample AIN1 AINX1
Sample AIN1
Sample AIN2
AINX0 Sample Ladder AIN1
Sample AIN1
Used
Sample AIN2
AINX1 Sample Ladder AINX1 Sample Ladder AIN2
Sample Ladder AINX2
Compare Ladder AINX0
Compare Ladder AIN1
Compare Ladder AINX1
Compare Ladder AIN2
DATA AIN0
DATA AINX0 Used
DATA AIN1
DATA AINX1 Used
Figure Sampling, Ladder Sampling Conversion Timing
Rev. 3.00
MP8798
Accuracy Conversion:
V(N+1) Analog Input V(N) DIGITAL CODES Output Codes VREF(-) V001 V002 V3FE V3FF V0FW VREF(+) (N+1) Code Width V(N+1) V(N) VREF(+) VREF(-) 1024 DNL(N) V(N+1) V(N)
transfer function ideal converter shown Figure
Figure Measurement Production Tester
formulas Differential Non-linearity (DNL), Integral Non-Linearity (INL) zero full scale errors (EZS, EFS) are:
Figure Ideal Transfer Function
overflow transition (VOFW) takes place VOFW VREF(+) first last transitions data bits take place V001 VREF(-) V3FF VREF(+) VREF 1024 (V3FF V001) 1022 Note that overflow transition flag impact data bits. "real" converter code-to-code transitions don't fall exactly every VREF/1024 volts. positive (Differential Non-Linearity) error means that real width particular code larger than LSB. This error measured fractions LSBs. specification guarantees that code widths (DNL errors) within stated value. specification means that code widths within LSB. VREF 4.608 then every code width within 2.25 6.75
(001) V002 V001 (3FE) V3FF V3FE (full scale error) V3FF [VREF(+) -1.5 LSB] (zero scale error) V001 [VREF(-) LSB]
DIGITAL CODES VREF(-) V001 V002 V3FE V3FF VREF(+)
Figure Real Transfer Curve
Figure shows zero scale full scale error terms.
Rev. 3.00
MP8798
Figure gives visual definition error. chart shows 3-bit converter transfer curve with greatly exaggerated errors show deviation real transfer curve from ideal one.
After tester measured transition voltages, computer draws line parallel ideal transfer line. definition best line makes equal positive negative errors. example, error LSB's relative Ideal Line would +1.5 LSB's relative best line.
Output Codes Real Transfer Line Ideal Transfer Line DATA Single sampling
system will clock MP8798 continuously will give clock pulses intermittently when conversion desired. timing Figure shows normal operation, while timing Figure keeps MP8798 balance ready sample analog input.
CLOCK DATA Continuous sampling
Best Line CLOCK BALANCE
Figure Relationship Data Clock Analog Input
MP8798 very flexible input range characteristics. user VREF(+) VREF(-) fixed voltages then vary input levels match VREF range. Another method first design analog input circuitry then adjust reference voltages analog input range. advantage that this approach eliminate need external gain offset adjust circuitry which required fixed input range A/Ds. MP8798's performance optimized using analog input circuitry that capable driving input. Figure shows equivalent circuit AIN.
Series Control Channel Selection
Analog Input (Volt)
Figure Error Calculation
Clock Conversion Timing
VREF(+) VREF(-)
Figure Analog Input Equivalent Circuit
Rev. 3.00
MP8798
Analog Input Multiplexer
MP8798 includes 4-channel analog input multiplexer. relationship between clock, multiplexer address, output data shown Figure
Digital Interfaces
logic encodes outputs comparators into binary code latches data D-type flip-flop output.
Clock
Sample Address
Sample Address
Sample
functional equivalent MP8798 (Figure 12.) composed Delay stage (tAP) from clock sampling phase (S). ideal analog switch which samples VIN. ideal which tracks converts with delay. series DFF's with specified hold (tHLD) delay (tDL) times. tAP, tHLD specified Electrical Characteristics table.
tCLKS2
tCLKH2
Address
DB0-DB9
MUXEN (Internal Signal)
Reference Voltages
input/output relationship function VREF: VREF(-) VREF VREF(+) VREF(-) DATA 1023 (AIN/VREF) system increase total gain reducing VREF.
Rev. 3.00
Valid Valid Address Valid Address Valid Address
tCLKS2 tCLKH2
Figure Address Timing
tMUXEN1
DB9-DB0
MP8798 tHLD DB9-DB0
Figure Analog Timing
Figure MP8798 Functional Equivalent Circuit Interface Timing
MP8798
Power Down
Figure shows relationship between clock, sampled output data relationship effect power down.
SAMPLE SAMPLE SAMPLE
DB0-DB9
Valid Valid tCLKS1 Valid tCLKH1
IDD, IVREF(+)
Figure Power Down Timing Diagram
Rev. 3.00
Valid
MP8798
APPLICATION NOTES
10µF Tantalum 0.1µF Chip inductance capacitor Clock Transmission Line Termination
Buffer
C1A, AVDD 100W AIN1 (Substrate)
C1D, DVDD
AIN4
Resistive Isolation 100W
MP8798
Reference Voltage Source
VREF(+) VREF(-)
VREF1(-) AGND DGND
Figure Typical Circuit Connections
following information will useful maximizing performance MP8798. signals should exceed AVDD +0.5 AGND -0.5 DVDD +0.5 DGND -0.5 input which value outside absolute maximum ratings (AVDD DVDD+0.5 AGND -0.5 should protected diode clamps (HP5082-2835) from input supplies. MP8798 inputs have input protection diodes which will protect device from short transients outside supply ranges. design board will affect accuracy MP8798. wire wrap recommended. analog input signal (VIN) quite sensitive should properly routed terminated. should shielded from clock digital outputs minimize cross coupling noise pickup. analog input should driven impedance (less than 50). Analog digital ground planes should substantial common point only. ground plane should Rev. 3.00
shield parasitics return path signals. reduce noise levels, separate impedance ground paths. DGND should shared with other digital circuitry. separate impedance paths cannot provided, DGND should connected AGND next MP8798. DVDD should shared with other digital circuitry avoid conversion errors caused digital supply transients. DVDD MP8798 should connected AVDD next MP8798. DVDD AVDD connected inside MP8798 through doped silicon substrate. voltage difference between DVDD AVDD will cause undesirable internal currents. Each power supply reference voltage should decoupled with ceramic (0.1µF) tantalum (10µF) capacitor close device possible. digital output should drive long wires. capacitive coupling reflection will contribute noise conversion. When driving distant loads, buffers should used. resistors series with digital outputs some applications reduces digital output disruption AIN.
MP8798
0.1µF
100k
MP5010
Figure Example Reference Voltage Source
VREF(+) AVDD
AIN1 AIN4
VREF(-)
AGND
Beckman Instruments #694-3-R10k resistor array equivalent. NOTE: High values affect input ADC) time constant. Therefore, different applications value needs selected tradeoff between settling time power dissipation.
Figure Analog Input
VREF(+) AVDD
AIN1 AIN4
VREF(-)
AGND
Beckman Instruments #694-3-R10k resistor array equivalent. NOTE: High values affect input ADC) time constant. Therefore, different applications value needs selected tradeoff between settling time power dissipation.
Figure Analog Input
Rev. 3.00
MP8798
MP8798
DAC8
AIN1 AIN2 AIN3 AIN4
Power Down write values minimize power consumption.
Figure Ladder with Programmed Control VREF(+), VREF(-), TAP.)
Only Ladder detail shown.
DAC7
DAC6
DAC5
DAC4
VREF(+) VREF(+)
DAC3
DAC1
MP7641
VREF1(-)
Rev. 3.00
MP8798
PERFORMANCE CHARACTERISTICS
Graph Sampling Frequency
Graph Sampling Frequency
Graph Supply Current Sampling Frequency
Graph Power Down Current Sampling Frequency
Graph Reference Voltage
Rev. 3.00
Graph Temperature
MP8798
Graph Supply Current Temperature
Graph Power Down Current Temperature
Graph Reference Resistance Temperature
Rev. 3.00
MP8798
LEAD PLASTIC DUAL-IN-LINE (300 PDIP) NN28
Seating Plane
INCHES SYMBOL 0.130 0.015 0.014 0.038 0.008 1.340 0.290 0.240 0.230 0.023 0.065 0.015 1.485 0.325 0.310
MILLIMETERS 3.30 0.381 0.356 0.965 0.203 34.04 7.37 6.10 5.84 0.584 1.65 0.381 37.72 8.26 7.87
0.100 0.115 0.055 0.020 0.150 0.070 0.100
2.54 2.92 1.40 0.508 3.81 1.78 2.54
Note:
minimum limit dimensions 0.023" (0.58 four corner leads only.
Rev. 3.00
MP8798
LEAD SMALL OUTLINE (300 JEDEC SOIC)
Seating Plane
INCHES SYMBOL 0.097 0.0050 0.014 0.0091 0.701 0.292 0.104 0.0115 0.019 0.0125 0.711 0.299
MILLIMETERS 2.464 0.127 0.356 0.231 17.81 7.42 2.642 0.292 0.483 0.318 18.06 7.59
0.050 0.400 0.010 0.016 0.410 0.016 0.035
1.27 10.16 0.254 0.406 10.41 0.406 0.889
Rev. 3.00
MP8798
LEAD SHRINK SMALL OUTLINE PACKAGE (SSOP)
Seating Plane
MILLIMETERS SYMBOL 1.73 0.05 0.20 0.13 10.07 5.20 2.05 0.21 0.40 0.25 10.40 5.38
INCHES 0.081 0.008 0.016 0.010 0.409 0.212
0.068 0.002 0.008 0.005 0.397 0.205
0.65 7.65 0.45 0.95
0.0256 0.301 0.018 0.319 0.037
Rev. 3.00
MP8798 Notes
Rev. 3.00
MP8798
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contains here only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed inaccuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, part whole, without prior written consent EXAR Corporation prohibited.
Rev. 3.00

CMOS Very Power, MSPS 10-Bit Analog-to-Digital Converter with 4-Channe

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