Memories bytes Program memory (OTP, EPROM, FASTROM ROM) with read-out
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ST6215C/ST6225C
Memories bytes Program memory (OTP, EPROM, FASTROM ROM) with read-out protection bytes Clock, Reset Supply Management Enhanced reset system Voltage Detector (LVD) Safe Reset Clock sources: crystal/ceramic resonator network, external clock, backup oscillator (LFAO) Oscillator Safeguard (OSG) Power Saving Modes: Wait Stop Interrupt Management interrupt vectors plus RESET external interrupt lines vectors) external non-interrupt line Ports multifunctional bidirectional lines alternate function lines high sink outputs (20mA) Timers Configurable watchdog timer 8-bit timer/counter with 7-bit prescaler Analog Peripheral 8-bit with input channels Instruction 8-bit data manipulation basic instructions addressing modes manipulation
PDIP28
S028
SS0P28
CDIP28W
(See Section 12.5 Ordering Information)
Development Tools Full hardware/software development package
Device Summary
Features Program memory bytes bytes Operating Supply Clock Frequency Operating Temperature Packages ST62T15C(OTP) ST6215C(ROM) ST62P15C(FASTROM) 3.0V 8MHz -40°C +125°C PDIP28 SO28 SSOP28 ST62T25C(OTP) ST6225C(ROM) ST62P25C(FASTROM ST62E25C(EPROM)
CDIP28W
Rev.
July 2001 1/105
Table Content1 INTRODUCTION DESCRIPTION MEMORY MAPS, PROGRAMMING MODES OPTION BYTES MEMORY REGISTER MAPS 3.1.1 Introduction 3.1.2 Program Space 3.1.3 Readout Protection 3.1.4 Data Space 3.1.5 Stack Space 3.1.6 Data Window Mechanism PROGRAMMING MODES 3.2.1 Program Memory 3.2.2 EPROM Erasing OPTION BYTES CENTRAL PROCESSING UNIT INTRODUCTION MAIN FEATURES REGISTERS
CLOCKS, SUPPLY RESET CLOCK SYSTEM 5.1.1 Main Oscillator 5.1.2 Oscillator Safeguard (OSG) 5.1.3 Frequency Auxiliary Oscillator (LFAO) 5.1.4 Register Description VOLTAGE DETECTOR (LVD) 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 Introduction RESET Sequence RESET Watchdog Reset Reset
RESET
INTERRUPTS INTERRUPT RULES PRIORITY MANAGEMENT INTERRUPTS POWER MODES MASKABLE INTERRUPT PERIPHERAL INTERRUPTS EXTERNAL INTERRUPTS (I/O PORTS)
6.5.1 Notes using External Interrupts INTERRUPT HANDLING PROCEDURE 6.6.1 Interrupt Response Time REGISTER DESCRIPTION
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Table Content7 POWER SAVING MODES INTRODUCTION WAIT MODE STOP MODE NOTES RELATED WAIT STOP MODES 7.4.1 Exit from Wait Stop Modes 7.4.2 Recommended Configuration PORTS INTRODUCTION FUNCTIONAL DESCRIPTION 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 Digital Input Modes Analog Inputs Output Modes Alternate Functions Instructions used access Port Data registers (SET, RES, DEC) 8.2.6 Recommendations POWER MODES INTERRUPTS REGISTER DESCRIPTION
ON-CHIP PERIPHERALS WATCHDOG TIMER (WDG) 9.1.1 Introduction 9.1.2 Main Features 9.1.3 Functional Description 9.1.4 Recommendations 9.1.5 Power Modes 9.1.6 Interrupts 9.1.7 Register Description 8-BIT TIMER 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 Introduction Main Features Counter/Prescaler Description Functional Description Power Modes Interrupts Register Description CONVERTER (ADC) Introduction Main Features Functional Description Recommendations Power Modes Interrupts Register Description
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Table Content10 INSTRUCTION 10.1 ARCHITECTURE 10.2 ADDRESSING MODES 10.3 INSTRUCTION ELECTRICAL CHARACTERISTICS 11.1 PARAMETER CONDITIONS 11.1.1Minimum Maximum Values 11.1.2Typical Values 11.1.3Typical Curves 11.1.4Loading Capacitor 11.1.5Pin Input Voltage 11.2 ABSOLUTE MAXIMUM RATINGS 11.2.1Voltage Characteristics 11.2.2Current Characteristics 11.2.3Thermal Characteristics 11.3 OPERATING CONDITIONS
11.3.1General Operating Conditions 11.3.2Operating Conditions with Voltage Detector (LVD) 11.4 SUPPLY CURRENT CHARACTERISTICS 11.4.1RUN Modes 11.4.2WAIT Modes 11.4.3STOP Mode 11.4.4Supply Clock System 11.4.5On-Chip Peripherals 11.5 CLOCK TIMING CHARACTERISTICS 11.5.1General Timings 11.5.2External Clock Source 11.5.3Crystal Ceramic Resonator Oscillators 11.5.4RC Oscillator 11.5.5Oscillator Safeguard (OSG) Frequency Auxiliary Oscillator (LFAO) 11.6 MEMORY CHARACTERISTICS
11.6.1RAM Hardware Registers 11.6.2EPROM Program Memory 11.7 CHARACTERISTICS 11.7.1Functional 11.7.2Absolute Electrical Sensitivity 11.7.3ESD Protection Strategy 11.8 PORT CHARACTERISTICS
11.8.1General Characteristics 11.8.2Output Driving Current 11.9 CONTROL CHARACTERISTICS 11.9.1Asynchronous RESET 11.9.2NMI 11.10 TIMER PERIPHERAL CHARACTERISTICS 11.10.1Watchdog Timer 11.10.28-Bit Timer
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Table Content11.11 8-BIT CHARACTERISTICS GENERAL INFORMATION 12.1 PACKAGE MECHANICAL DATA 12.2 THERMAL CHARACTERISTICS 12.3 SOLDERING GLUEABILITY INFORMATION 12.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL 12.5 ORDERING INFORMATION 12.6 TRANSFER CUSTOMER CODE 12.6.1FASTROM Version 12.6.2ROM Version DEVELOPMENT TOOLS APPLICATION NOTES SUMMARY CHANGES MORE INFORMATION
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INTRODUCTION
ST6215C, devices cost members ST62xx 8-bit HCMOS family microcontrollers, which targeted medium complexity applications. ST62xx devices based building block approach: common core surrounded number on-chip peripherals. ST62E25C erasable EPROM version ST62T15C, T25C devices, which used during development phase ST62T15C, T25C target devices, well respective ST6215C, devices. EPROM devices functionally identical. devices offer advantages user programmability cost, which make them ideal choice wide range applications where frequent code changes, multiple code versions last minute programmability required. based versions offer same functionality, selecting options defined programFigure Block Diagram
8-BIT CONVERTER PORT INTERRUPTS PORT DATA USER SELECTABLE TIMER DATA Bytes TIMER PC4.PC7 PB0.PB7 PA0.PA3 (20mA Sink) PA4.PA7
mable option bytes OTP/EPROM versions option list (See Section 12.6 page 97). ST62P15C/P25C Factory Advanced Service Technique (FASTROM) versions ST62T15C,T25C devices. They offer same functionality devices, they have programmed customer (See Section page 91). These compact low-cost devices feature Timer comprising 8-bit counter with 7-bit programmable prescaler, 8-bit Converter with analog inputs Digital Watchdog timer, making them well suited wide range automotive, appliance industrial applications. easy reference, parametric data located Section page
PORT
PROGRAM MEMORY Bytes)
WATCHDOG TIMER STACK LEVEL STACK LEVEL STACK LEVEL STACK LEVEL STACK LEVEL STACK LEVEL POWER SUPPLY 8-BIT CORE
OSCILLATOR
RESET
OSCin OSCout
RESET
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DESCRIPTION
Figure 28-Pin Package Pinout
TIMER OSCin OSCout Ain/PC7 Ain/PC6 Ain/PC5 Ain/PC4 RESET Ain/PB7 Ain/PB6 Ain/PB5
PA0/20mA Sink PA1/20mA Sink PA2/20mA Sink PA3/20mA Sink PA4/Ain PA5/Ain PA6/Ain PA7/Ain PB0/Ain PB1/Ain PB2/Ain PB3/Ain PB4/Ain
associated interrupt vector
Table Device Description
Type
TIMER
Name
Main Function (after Reset) Main power supply Timer input output External clock input resonator oscillator inverter input
Alternate Function
OSCin OSCout PC7/Ain PC6/Ain PC5/Ain PC4/Ain RESET PB7/Ain PB6/Ain
Resonator oscillator inverter output resistor input oscillator maskable interrupt (falling edge sensitive) (IPU) (IPU) (IPU) (IPU) Analog input Analog input Analog input Analog input
Must held normal operation, 12.5V level applied during reset phase, device enters EPROM programming mode. priority maskable interrupt (active low) (IPU) (IPU) Analog input Analog input
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Type
Name PB5/Ain PB4/Ain PB3/Ain PB2/Ain PB1/Ain PB0/Ain PA7/Ain PA6/Ain PA5/Ain PA4/Ain PA3/ 20mA Sink PA2/ 20mA Sink PA1/ 20mA Sink PA0/ 20mA Sink
Main Function (after Reset) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) Ground
Alternate Function Analog input Analog input Analog input Analog input Analog input Analog input Analog input Analog input Analog input Analog input
Legend Abbreviations Table input, output, supply, input pull-up input with pull-up configuration (reset state) valid long user software does change Refer Section "I/O PORTS" page more details software configuration ports.
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MEMORY MAPS, PROGRAMMING MODES OPTION BYTES
MEMORY REGISTER MAPS 3.1.1 Introduction operates three separate memory spaces: Program space, Data space, Stack space. Operation these three memory spaces described following paragraphs. Figure Memory Addressing Diagram Briefly, Program space contains user program code user vectors; Data space contains user data OTP, Stack space accommodates levels stack subroutine interrupt service routine nesting.
PROGRAM SPACE 000h 000h
DATA SPACE
RESERVED
03Fh 040h PROGRAM MEMORY (see Figure page DATA READ-ONLY MEMORY WINDOW 07Fh 080h 081h 082h 083h 084h 0BFh 0C0h 0FF0h INTERRUPT RESET VECTORS 0FFFh 0FFh REGISTER REGISTER REGISTER REGISTER HARDWARE CONTROL REGISTERS (see Table ACCUMULATOR
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MEMORY (Cont'd) Figure Program Memory
ST6215C
0000h 0000h
ST6225C
RESERVED
07Fh 080h
IMPLEMENTED
07FFh 0800h
RESERVED*
087Fh 0880h
USER PROGRAM MEMORY USER PROGRAM MEMORY 1824 BYTES 3872 BYTES
0F9Fh 0FA0h 0FEFh 0FF0h 0FF7h 0FF8h 0FFBh 0FFCh 0FFDh 0FFEh 0FFFh
RESERVED
INTERRUPT VECTORS RESERVED* VECTOR USER RESET VECTOR
0F9Fh 0FA0h 0FEFh 0FF0h 0FF7h 0FF8h 0FFBh 0FFCh 0FFDh 0FFEh 0FFFh
RESERVED* INTERRUPT VECTORS RESERVED* VECTOR USER RESET VECTOR
Reserved areas should filled with 0FFh
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MEMORY (Cont'd) 3.1.2 Program Space Program Space comprises instructions executed, data required immediate addressing mode instructions, reserved factory test area user vectors. Program Space addressed 12-bit Program Counter register register). Thus, capable addressing bytes memory directly. 3.1.3 Readout Protection Program Memory EPROM devices protected against external readout memory setting Readout Protection option byte (Section page 16). EPROM parts, Readout Protection option desactivated only U.V. erasure that also results whole EPROM context being erased. Note: Once Readout Protection activated, longer possible, even STMicroelectronics, gain access contents. Returned parts therefore accepted Readout Protection set. 3.1.4 Data Space Data Space accommodates data necessary processing user program. This space comprises resource, processor core peripheral registers, well read-only data
such constants look-up tables OTP/ EPROM. 3.1.4.1 Data read-only data physically stored program memory, which also accommodates Program Space. program memory consequently contains program code executed, well constants look-up tables required application. Data Space locations which different constants look-up tables addressed processor core thought 64-byte window through which possible access read-only data stored OTP/EPROM. 3.1.4.2 Data data space includes user area, accumulator (A), indirect registers (X), (Y), short direct registers (V), (W), port registers, peripheral data control registers, interrupt option register Data Window register (DRWR register). 3.1.5 Stack Space Stack space consists 12-bit registers which used stack subroutine interrupt return addresses, well current program counter contents.
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MEMORY (Cont'd) Table Hardware Register
Address 080h 083h 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h 0C9h 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h 0D7h 0D8h 0D9h 0FEh 0FFh Watchdog Timer WDGR ADCR PSCR TSCR Ports DRWR Ports DDRA DDRB DDRC
Block
Register Label X,Y,V,W
Register Name index registers short direct registers Port Data Register Port Data Register Port Data Register Reserved Byte) Port Direction Register Port Direction Register Port Direction Register Reserved Byte) Interrupt Option Register Data Window register Reserved Bytes) Port Option Register Port Option Register Port Option Register Reserved byte) Converter Data Register Converter Control Register Timer Prescaler Register Timer Counter Register Timer Status Control Register Reserved Bytes) Watchdog Register Reserved Bytes) Accumulator
Reset Status
Remarks
Port
Write-only Write-only
0FFh
Read-only Ro/Wo
Timer1
0FEh
Legend: undefined, Read/Write, Read-only Bit(s) register, Write-only Bit(s) register. Notes: contents port registers readable only output configuration. input configuration, values pins returned instead register contents. bits associated with unavailable pins must always kept their reset value. single-bit instructions (SET, RES.) Port Data Registers port configured input mode (refer Section "I/O PORTS" page more details).
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MEMORY (Cont'd) 3.1.6 Data Window Mechanism Data read-only memory window located from address 0040h address 007Fh Data space. allows direct reading consecutive bytes located anywhere program memory, between address 0000h 0FFFh. There blocks bytes device: Block related address range 0000h 003Fh. Block related address range 0040h 007Fh. program memory therefore used store either instructions read-only data. Data window moved steps bytes along program memory writing appropriate code Data Window Register (DRWR). Figure Data Window
PROGRAM 0000h SPACE 000h DATA SPACE
3.1.6.1 Data Window Register (DRWR) DRWR addressed like location Data Space. This register used select 64-byte block program memory read Data window (from address address Data space). DRWR register cleared reset, therefore must written before accessing Data read-only memory window area first time. Address: 0C9h Write Only Reset Value (undefined)
DRWR5 DRWR4 DRWR3 DRWR2 DRWR1 DRWR0
Bits Reserved, must cleared. Bits DRWR[5:0] Data read-only memory Window Register Bits. These Data readonly memory Window bits that correspond upper bits data read-only memory space. Caution: This register undefined reset, write-only, therefore read access using Read-Modify-Write instructions (SET, RES, DEC).
040h DATA 64-BYTE 07Fh WINDOW
0FFFh
0FFh
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MEMORY (Cont'd) 3.1.6.2 Data Window memory addressing cases where some data (look-up tables example) stored program memory, reading these data requires Data window mechanism. this: DRWR register loaded with 64-byte block number where data located program memory). This number also gives start address block. Then, offset address byte Data Window (corresponding offset 64-byte block program memory) loaded register X,.). When above steps completed, data read. understand determine DRWR content register, please refer example shown Figure case calcula-
tion automatically handled development tools. Please refer user manual correspoding tool. 3.1.6.3 Recommendations Care required when handling DRWR register write only. this reason, DRWR contents should changed while executing interrupt service routine, service routine cannot save then restore register's previous contents. impossible avoid writing DRWR during interrupt service routine, image register must saved location, each time program writes DRWR, must also write image register. image register must written first that, interrupt occurs between instructions, DRWR affected.
Figure Data read-only memory Window Memory Addressing
DATA SPACE PROGRAM SPACE 0000h 000h
040h OFFSET
DATA
061h 07Fh
0400h OFFSET 0421h bytes DATA DRWR
0FFh
07FFh DATA address Program memory 421h DRWR content 421h (64) data located 64-bytes window number 64-byte window start address 400h Register X,.)content Offset (421h 400h) Data Window start address data space)
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PROGRAMMING MODES 3.2.1 Program Memory EPROM/OTP programming mode +12.5V voltage applied TEST/V pin. programming flow ST62T15C,T25C/E25C described User Manual EPROM Programming Board. Table ST6215C Program Memory
Device Address 0000h-087Fh 0880h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh Description Reserved User Reserved Interrupt Vectors Reserved Interrupt Vector Reset Vector
Table ST6225C Program Memory
Device Address 0000h-007Fh 0080h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh Description Reserved User Reserved Interrupt Vectors Reserved Interrupt Vector Reset Vector
Note: OTP/EPROM devices programmed with development tools available from STMicroelectronics (please refer Section page 100). 3.2.2 EPROM Erasing EPROM devices erased exposure Ultra Violet light. characteristics such that erasure begins when memory exposed light with wave lengths shorter than approximately should noted that sunlight some types fluorescent lamps have wavelengths range thus recommended that window packages covered opaque label prevent unintentional erasure problems when testing application such environment. recommended erasure procedure exposure short wave ultraviolet light which have wavelength integrated dose (i.e. U.V. intensity exposure time) erasure should minimum 30W-sec/cm2. erasure time with this dosage approximately minutes using ultraviolet lamp with 12000µW/cm2 power rating. EPROM device should placed within 2.5cm (1inch) lamp tubes during erasure.
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OPTION BYTES Each device available production user programmable versions (OTP) well factory coded versions (ROM). devices shipped customers with default content (00h), while factory coded parts contain code supplied customer. This implies that devices have configured customer using Option Bytes while devices factory-configured. option bytes allow hardware configuration microcontroller selected. option bytes have address memory accessed only programming mode (for example using standard programming tool). masked devices, option bytes fixed hardware code (see Section 12.6.2 "ROM Version" page 98). therefore impossible read option bytes. option bytes only programmed once. possible change selected options after they have been programmed. order reach power consumption value indicated Section 11.4, option byte must programmed default value. Otherwise, over-consumption will occur. OPTION BYTE Bits 15:10 Reserved, must always cleared. EXTCNTL External STOP MODE control. EXTCNTL mode available. STOP mode available with watchdog active. EXTCNTL mode available. STOP mode available with watchdog active setting one. Voltage Detector on/off. This option enable disable Voltage Detector (LVD) feature.
OPTION BYTE Reserved Default Value
Voltage Detector disabled Voltage Detector enabled. OPTION BYTE PROTECT Readout Protection. This option enables disables external access internal program memory. Program memory read-out protected Program memory read-out protected Oscillator selection This option selects main oscillator type. Quartz crystal, ceramic resonator external clock network Bits Reserved, must always cleared. PULL Pull-Up on/off. This option enables disables internal pullup pin. Pull-up disabled Pull-up enabled PULL TIMER Pull-Up on/off. This option enables disables internal pullup TIMER pin. Pull-up disabled Pull-up enabled WDACT Hardware software watchdog. This option selects watchdog type. Software (watchdog enabled software) Hardware (watchdog always enabled) OSGEN Oscillator Safeguard on/off. This option enables disables oscillator Safeguard (OSG) feature. Oscillator Safeguard disabled Oscillator Safeguard enabled
OPTION BYTE PRONMI Res. Res. TECT PULL PULL
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CENTRAL PROCESSING UNIT
INTRODUCTION Core devices independent Memory configuration. such, thought independent central processor communicating with on-chip I/O, Memory Peripherals internal address, data, control buses. MAIN FEATURES
basic instructions main addressing modes 8-bit index registers 8-bit short direct registers power modes Maskable hardware interrupts 6-level hardware stack
REGISTERS Family core features registers three pairs flags available programmer. These described following paragraphs. Accumulator (A). accumulator 8-bit general purpose register used arithmetic calculations, logical operations, data manipulaFigure Register7 RESET VALUE RESET VALUE RESET VALUE
tions. accumulator addressed Data Space location address FFh. Thus manipulate accumulator just like other register Data Space. Index Registers These registers used Indirect addressing mode pointers memory locations Data Space. They also accessed Direct, Short Direct, Direct addressing modes. They mapped Data Space addresses accessed like other memory location. Short Direct Registers These registers used Short Direct addressing mode. This means that data stored accessed with one-byte instruction (four cycles). also accessed using Direct Direct addressing modes. They mapped Data Space addresses accessed like other memory location. Note: registers also used Short Direct registers same Program Counter (PC). program counter 12-bit register which contains address next instruction executed core. This location opcode, operand, address operand.
ACCUMULATOR LEVEL STACK INDEX REGISTER NORMAL FLAGS INDEX REGISTER INTERRUPT FLAGS SHORT INDIRECT REGISTER RESET VALUE SHORT INDIRECT REGISTER RESET VALUE Undefined value FLAGS
CNMI ZNMI
PROGRAM COUNTER RESET VALUE RESET VECTOR 0FFEh-0FFFh
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REGISTERS (Cont'd) 12-bit length allows direct addressing 4096 bytes Program Space. However, program space contains more than 4096 bytes, additional memory program space addressed using Program Page register. value incremented after reading address current instruction. execute relative jumps, offset shifted through ALU, where they added; result then shifted back into program counter changed following ways: (Jump) instruction Jump address CALL instruction Call address Relative Branch InstructionPC offset Interrupt Interrupt vector Reset Reset vector RETI instructions (stack) Normal instruction Flags includes three pairs flags (Carry Zero), each pair being associated with three normal modes operation: Normal mode, Interrupt mode Maskable Interrupt mode. Each pair consists CARRY flag ZERO flag. pair (CN, used during Normal operation, another pair used during Interrupt mode (CI, ZI), third pair used Maskable Interrupt mode (CNMI, ZNMI). uses pair flags associated with current mode: soon interrupt Maskable Interrupt) generated, uses Interrupt flags flags) instead Normal flags. When RETI instruction executed, previously used flags restored. should noted that each flag only addressed context (Non Maskable Interrupt, Normal Interrupt Main routine). flags cleared during context switching thus retain their status. Carry flag. This when carry borrow occurs during arithmetic operations; otherwise cleared. Carry flag also value tested test instruction; also participates rotate left instruction. carry occured carry occured
Zero flag This flag result last arithmetic logical operation equal zero; otherwise cleared. result last operation different from zero result last operation zero Switching between three sets flags performed automatically when NMI, interrupt RETI instruction occurs. mode automatically selected after reset MCU, core uses flags first. Stack. includes true LIFO (Last First Out) hardware stack which eliminates need stack pointer. stack consists separate 12-bit locations that belong data space area. When subroutine call interrupt request) occurs, contents each level shifted into next level down, while content shifted into first level (the original contents sixth stack level lost). When subroutine interrupt return occurs (RET RETI instructions), first level register shifted back into value each level popped back into previous level. Figure Stack manipulation
PROGRAM COUNTER
RETURN FROM INTERRUPT, SUBROUTINE
LEVEL LEVEL LEVEL LEVEL LEVEL LEVEL
INTERRUPT, SUBROUTINE CALL
Since accumulator, common with other data space registers, stored this stack, management these registers should performed within subroutine. Caution: stack will remain "deepest" position more than nested calls interrupts executed, consequently last return address will lost. will also remain highest position stack empty RETI executed. this case next instruction will executed.
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CLOCKS, SUPPLY RESET
CLOCK SYSTEM main oscillator driven these clock sources: external clock signal external AT-cut parallel-resonant crystal external ceramic resonator external network (RNET). addition, on-chip Frequency Auxiliary Oscillator (LFAO) available back-up clock system reduce power consumption. optional Oscillator Safeguard (OSG) filters spikes from oscillator lines, switches LFAO backup oscillator event main oscillator failure. also automatically limits internal clock frequency (fINT) function VDD, order guarantee correct operation. These functions illustrated Figure Figure Figure Clock Circuit Block Diagram
OSCILLATOR SAFEGUARD (OSG) fOSC filtering CORE 8-BIT TIMER MAIN OSCILLATOR LFAO OSCOFF (ADCR REGISTER) 8-BIT ARTIMER 8-BIT ARTIMER Oscillator Divider fINT WATCHDOG
Table illustrates various possible oscillator configurations using external crystal ceramic resonator, external clock input, external resistor (RNET), lowest cost solution using only LFAO. more details configuring clock options, refer Option Bytes section this document. internal clock frequency (fINT) divided drive Timer, Watchdog timer converter, drive core drive ARTIMER, shown Figure With oscillator, fastest cycle therefore 1.625µs. cycle smallest unit time needed execute operation (for instance, increment Program Counter). instruction require two, four, five cycles execution.
ENABLE OPTION (See OPTION BYTE SECTION)
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Network Option1)
CLOCK SYSTEM (Cont'd) 5.1.1 Main Oscillator oscillator configuration specified selecting appropriate option option bytes (refer Option Bytes section this document). When CRYSTAL/RESONATOR option selected, must used with quartz crystal, ceramic resonator external signal provided OSCin pin. When NETWORK option selected, system clock generated external resistor (the capacitor implemented internally). main oscillator turned (when ENABLED option selected) setting OSCOFF Control Register (not available some devices). This will automatically start Frequency Auxiliary Oscillator (LFAO). main oscillator turned resetting OSCOFF Converter Control Register resetting MCU. When main oscillator starts there delay made oscillator start-up delay period plus duration software instruction clock frequency fLFAO. Caution: should noted that when network option selected, accuracy frequency about suitable some applications (For more details, please refer Electrical Characteristics Section).
Table Oscillator ConfigurationHardware Configuration Crystal/Resonator Option1) External Clock OSCin OSCout EXTERNAL CLOCK Crystal/Resonator Clock OSCin OSCout
Crystal/Resonator Option1)
LOAD CAPACITORS Network
OSCin
OSCout
RNET
Enabled Option1)
LFAO
OSCin
OSCout
Notes: select options shown column above table, refer Option Byte section. 2.This schematic given guidance only subject schematics given crystal ceramic resonator manufacturer. more details, please refer Electrical Characteristics Section.
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CLOCK SYSTEM (Cont'd) 5.1.2 Oscillator Safeguard (OSG) Oscillator Safeguard (OSG) feature means dramatically improving operational integrity MCU. available when ENABLED option selected option byte (refer Option Bytes section this document). acts filter whose cross-over frequency device dependent provides three basic functions: Filtering spikes oscillator lines which would result driving excessive frequencies Management Frequency Auxiliary Oscillator (LFAO), (useable cost internal clock source, backup clock case main oscillator failure power consumption) Automatically limiting fINT clock frequency function supply voltage, ensure correct operation even power supply drops. 5.1.2.1 Spike Filtering Spikes oscillator lines result effectively increased internal clock frequency. absence circuit, this lead over frequency given power supply voltage. filters such spikes illustrated Figure 10). cases, when active, max-
imum internal clock frequency, fINT, limited fOSG, which supply voltage dependent. 5.1.2.2 Management Supply Voltage Variations Over-frequency, given power supply level, seen spikes; therefore filters some cycles order that internal clock frequency device kept within range particular device stand (depending VDD), below fOSG: maximum authorised frequency with enabled. 5.1.2.3 LFAO Management When enabled, Frequency Auxiliary Oscillator used (see Section 5.1.3). Note: should used wherever possible provides maximum security application. should noted however, that increase power consumption reduce maximum operating frequency fOSG (see Electrical Characteristics section). Caution: Care taken when using OSG, internal frequency defined between minimum maximum value vary depending both temperature. precise timing measurements, recommended OSG.
Figure Filtering Function
fOSC>fOSG fOSC fOSG fOSC<fOSG
fINT
Figure LFAO Oscillator Function
MAIN OSCILLATOR STOPS fOSC fLFAO fINT MAIN OSCILLATOR RESTARTS
INTERNAL CLOCK DRIVEN LFAO
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CLOCK SYSTEM (Cont'd) 5.1.3 Frequency Auxiliary Oscillator (LFAO) Frequency Auxiliary Oscillator three main purposes. Firstly, used reduce power consumption timing critical routines. Secondly, offers fully integrated system clock, without external components. Lastly, acts backup oscillator case main oscillator failure. This oscillator available when ENABLED option selected option byte (refer Option Bytes section this document). this case, automatically starts periods after first missing edge main oscillator, whatever reason failure (main oscillator defective, clock circuitry provided, main oscillator switched off.). Figure User code, normal interrupts, WAIT STOP instructions, processed normal, reduced fLFAO frequency. converter accuracy decreased, since internal frequency below MHz. power until main oscillator starts, reset delay counter driven LFAO. main oscillator starts before 2048 32768 cycle delay elapsed, takes over.
Frequency Auxiliary Oscillator automatically switched soon main oscillator starts. 5.1.4 Register Description CONTROL REGISTER (ADCR) Address: 0D1h Read/Write Reset value: 0100 0000 (40h)
ADCR ADCR ADCR ADCR ADCR ADCR ADCR
7:3, ADCR[7:3], ADCR[1:0] Control Register. These bits used control converter available device) otherwise they used. OSCOFF Main Oscillator Off. Main oscillator enabled Main oscillator disabled Note: must enabled using OSGEN option Option Byte, otherwise OSCOFF setting effect.
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VOLTAGE DETECTOR (LVD) on-chip Voltage Detector enabled setting option bytes (refer Option Bytes section this document). allows device used without external RESET circuitry. this case, RESET should left unconnected. used, external circuit mandatory ensure correct Power Reset operation, figure Reset section. more details, please refer application note AN669. generates static Reset when supply voltage below reference value. This means that secures power-up well powerdown keeping reset. VIT- reference value voltage drop lower than VIT+ reference value power-on order avoid parasitic reset when starts running sinks current supply (hysteresis). Figure Voltage Detector Reset
Vhyst VIT+ VIT-
Reset circuitry generates reset when below: VIT+ when rising VIT- when falling function illustrated Figure enabled, only states: Over input threshold voltage, running under full software control Below input threshold voltage, static safe reset these conditions, secure operation guaranteed without need external reset hardware. During Voltage Detector Reset, RESET held low, thus permitting reset other devices.
RESET
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RESET 5.3.1 Introduction reset three ways: pulse input RESET Internal Watchdog reset Internal Voltage Detector (LVD) reset 5.3.2 RESET Sequence basic RESET sequence consists main phases: Internal (watchdog LVD) external Reset event delay 2048 32768 clock (fINT) cycles (selected through option bytes) RESET vector fetch reset delay allows oscillator stabilise ensures that recovery taken place from Reset state. Figure RESET Sequence
VIT+ VIT-
RESET vector fetch phase duration clock cycles. When reset occurs: stack cleared loaded with address Reset vector. located program starting address 0FFEh. jump beginning user program must coded this address. interrupt flag automatically set, that Maskable Interrupt mode. This prevents initialization routine from being interrupted. initialization routine should therefore terminated RETI instruction, order back normal mode.
WATCHDOG RESET WATCHDOG UNDERFLOW
RESET
RESET
INTERNAL RESET
RESET
RESET
RESET 2048 CLOCK CYCLE INT) DELAY
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RESET (Cont'd) 5.3.3 RESET RESET connected device application board order reset required. RESET pulled RUN, WAIT STOP mode. This input used reset internal state ensure starts-up correctly. pin, which connected internal pull-up, active features Schmitt trigger input. delay (2048 clock cycles) added external signal ensures that even short pulses RESET accepted valid, provided completed rising phase that oscillator running correctly (normal WAIT modes). kept Reset state long RESET held low. Figure Reset Block Diagram
RESET grounded while WAIT modes, processing user program stopped (RUN mode only), ports configured inputs with pull-up resistors main oscillator restarted. When level RESET then goes high, initialization sequence executed internal delay period. RESET grounded while STOP mode, oscillator starts ports configured inputs with pull-up resistors. When RESET level then goes high, initialization sequence executed internal delay period. simple external RESET circuitry shown Figure more details, please refer application note AN669.
RESET RESD1) WATCHDOG RESET RESET
Resistive protection. reset delay value selected through option bytes.
COUNTER 2048 32768 clock cycles
INTERNAL RESET
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RESET (Cont'd) 5.3.4 Watchdog Reset provides Watchdog timer function order able recover from software hangups. Watchdog register refreshed before end-of-count condition reached, Watchdog reset generated. After Watchdog reset, restarts same Reset generated RESET pin. Note: When watchdog reset occurs, RESET tied very short time period, flag reset phase. This time long enough reset external circuits. more details refer Watchdog Timer chapter. 5.3.5 Reset different RESET sequences caused internal circuitry distinguished: Power-On RESET Voltage Drop RESET During reset, RESET pulled when VDD<VIT+ (rising edge) VDD<VIT- (falling edge). more details, refer chapter. Caution: externally connect directly RESET VDD, this cause damage component case internal RESET (Watchdog LVD). Figure Simple External Reset Circuitry
Figure Reset Processing
RESET 2048 32768 CLOCK CYCLE DELAY INTERNAL RESET
MASK LATCH CLEARED PRESENT)
SELECT MODE FLAGS
FFEh ADDRESS
RESET STILL PRESENT? LOAD FROM RESET LOCATIONS FFEh/FFFh
FETCH INSTRUCTION
RESET Typical: 10nF ST62xx
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INTERRUPTS
core interrupted four maskable interrupt sources, addition Maskable Interrupt (NMI) source. interrupt processing flowchart shown Figure Maskable interrupts must enabled setting register. However, even they disabled (GEN interrupt events latched processed soon set. Each source associated with specific Interrupt Vector, located Program space (see Interrupt Mapping table). vector location, user must write Jump instruction associated interrupt service routine. When interrupt source generates interrupt request, register loaded with address interrupt vector, which then causes Jump relevant interrupt service routine, thus servicing interrupt. Interrupts triggered events either external pins, from on-chip peripherals. Several events ORed same interrupt vector. On-chip peripherals have flag registers determine which event triggered interrupt.
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Figure Interrupts Block Diagram
LATCH CLEARED START VECTOR ROUTINE
VECTOR
PA0.PA7
PORT REGISTER "INPUT WITH INTERRUPT" CONFIGURATION
LATCH VECTOR CLEARED START VECTOR ROUTINE
EXIT FROM STOP/WAIT
(IOR REGISTER)
PB0.PB7 PC4.PC7
PORT REGISTER "INPUT WITH INTERRUPT" CONFIGURATION
LATCH
VECTOR
(IOR REGISTER) CLEARED START VECTOR ROUTINE VECTOR
TIMER
(TSCR REGISTER) (IOR REGISTER) VECTOR
CONVERTER
(ADCR REGISTER)
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INTERRUPT MANAGEMENT
RULES
PRIORITY
MASKABLE INTERRUPT This interrupt triggered when falling edge occurs regardless state register. interrupt request vector latched flip flop which automatically reset core beginning service routine. PERIPHERAL INTERRUPTS Different peripheral interrupt flags peripheral control registers able cause interrupt when they active both: register corresponding enable peripheral control register. Peripheral interrupts linked vectors Interrupt requests flagged their corresponding control register. This means that request cannot lost, because flag must cleared user software.
Reset interrupt peripheral interrupt routines Maskable Interrupt request highest priority interrupt peripheral interrupt routine time cannot interrupt another interrupt. peripheral interrupt interrupt another. more than interrupt request pending, these processed processor core according their priority level: vector highest priority while vector lowest. priority each interrupt source fixed hardware (see Interrupt Mapping table).
INTERRUPTS POWER MODES interrupts cause processor exit from WAIT mode. Only external some specific interrupts from on-chip peripherals cause processor exit from STOP mode (refer "Exit from STOP" column Interrupt Mapping Table).
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EXTERNAL INTERRUPTS (I/O Ports) External interrupt vectors loaded into register corresponding external interrupt occurred set. These interrupts allow processor exit from STOP mode. external interrupt polarity selected through register. External interrupts linked vectors Interrupt requests vector configured either edge level-sensitive using Register. Interrupt requests from vector always edge sensitive. edge polarity configured using Register. edge-sensitive mode, latch when edge occurs interrupt source line cleared when associated interrupt routine started. interrupt request stored until completion currently executing interrupt routine, before being processed. several interrupt requests occurs before completion current interrupt routine, only first request stored. Storing interrupt requests possible level sensitive mode. taken into account, level must present interrupt when samples line after instruction execution. 6.5.1 Notes using External Interrupts Spurious Interrupt Vector associated with interrupt vector configured interrupt with pull-up, whenever vector configured rising edge sensitive setting register), interrupt latched although rising edge have occured associated pin. This vector circuitry.The workaround discard this first interrupt request routine (using flag example). Masking Interrupt Another Vector When more port pins (associated with interrupt vector configured together input with interrupt (falling edge sensitive), long stuck '0', other never generate interrupt even active edge occurs this pin. same thing occurs when stuck interrupt vector configured rising edge sensitive. avoid this first must input signal that goes back right after falling edge. Otherwise, interrupt routine first pin, deactivate "input with interrupt" mode using port control registers (DDR, DR). active edge another then latched. port Configuration Spurious Interrupt Vector associated with interrupt vector `input with pull-up' state, level present when configured interrupt with pull-up writing DDRx, register bits, interrupt latched although falling edge have occurred associated pin. opposite case, interrupt with pull-up state level present when port configured input with pull-up writing DDRx, bits, interrupt latched although rising edge have occurred associated pin.
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INTERRUPT HANDLING PROCEDURE interrupt procedure very similar call procedure, fact user consider interrupt asynchronous call procedure. this asynchronous event, user cannot know context time which occurred. result, user should save Data space registers which used within interrupt routines. following list summarizes interrupt procedure: When interrupt request occurs, following actions performed automatically: core switches from normal flags interrupt flags flags). contents stored level stack. normal interrupt lines inhibited (NMI still active). internal latch any) cleared. associated interrupt vector loaded When interrupt request occurs, following actions must performed user software: User selected registers have saved within interrupt service routine (normally software stack). source interrupt must determined polling interrupt flags more than source associated with same vector). RETI (RETurn from Interrupt) instruction must interrupt service routine. After RETI instruction executed, returns main routine. Caution: When maskable interrupt occurs while core NORMAL mode during execution "ldi IOR, 00h" instruction (disabling maskable interrupts): interrupt request occurs during first cycles "ldi" instruction (which 4-cycle instruction) core will switch interrupt mode flags will switch interrupt pair 6.6.1 Interrupt Response Time This defined time between moment when Program Counter loaded with interrupt vector when program jump interrupt subroutine ready execute code. depends when interrupt occurs while core processing instruction. Figure Interrupt Processing Flow Chart
INSTRUCTION
FETCH INSTRUCTION
EXECUTE INSTRUCTION
LOAD FROM INTERRUPT VECTOR
INSTRUCTION RETI CORE ALREADY NORMAL MODE?
CLEAR INTERNAL LATCH
DISABLE MASKABLE INTERRUPT
ENABLE MASKABLE INTERRUPTS PUSH INTO STACK
SELECT NORMAL FLAGS
SELECT INTERRUPT FLAGS
"POP" STACKED
THERE INTERRUPT REQUEST INTERRUPT MASK?
latch present interrupt source line
Table Interrupt Response Time
Minimum Maximum cycles cycle
cycle external clock cycles thus cycles /8M) 17.875 with external quartz.
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REGISTER DESCRIPTION INTERRUPT OPTION REGISTER (IOR) Address: 0C8h Write Only Reset status:
level sensitive mode selected interrupt vector Edge Selection bit. Falling edge mode interrupt vector Rising edge mode interrupt vector Global Enable Interrupt Disable maskable interrupts Enable maskable interrupts Note: When cleared, interrupt active cannot used exit from STOP WAIT modes. Bits Reserved, must cleared.
Caution: This register write-only cannot accessed single-bit operations (SET, RES, DEC,.). =Reserved, must cleared. Level/Edge Selection bit. Falling edge sensitive mode selected interrupt vector Table Interrupt Mapping
Vector number Vector Source Block RESET Description Reset Maskable Interrupt USED Vector Vector Vector Vector Port Port TIMER Ext. Interrupt Port Ext. Interrupt Port Timer underflow Conversion
Register Label
Flag
Exit from STOP
Vector Address FFEh-FFFh FFCh-FFDh FFAh-FFBh FF8h-FF9h FF6h-FF7h FF4h-FF5h FF2h-FF3h FF0h-FF1h
Priority Order Highest Priority
TSCR ADCR
Lowest Priority
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POWER SAVING MODES
INTRODUCTION give large measure flexibility application terms power consumption, main power saving modes implemented (see Figure 19). addition, Frequency Auxiliary Oscillator (LFAO) used instead main oscillator reduce power consumption WAIT modes. After RESET normal operating mode selected default (RUN mode). This mode drives device (CPU embedded peripherals) means master clock which based main oscillator frequency. From mode, different power saving modes selected calling specific software instruction LFAO setting relevant register bit. more information LFAO, please refer Clock chapter. Figure Power Saving Mode TransitionHigh LFAO WAIT
STOP POWER CONSUMPTION
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WAIT MODE goes into WAIT mode soon WAIT instruction executed. This following effects: Program execution stopped, microcontroller software considered being "frozen" state. contents peripheral registers preserved long power supply voltage higher than retention voltage. oscillator kept running provide clock peripherals; they still active. WAIT mode used when user wants reduce power consumption during idle periods, while losing track time ability monitor external events. WAIT mode places power consumption mode stopping CPU. active oscillator (main oscillator LFAO) kept running order provide clock signal peripherals. power consumption further reduced, Frequency Auxiliary Oscillator (LFAO) used place main oscillator, operating frequency lower. required, LFAO must switched before entering WAIT mode. Exit from Wait mode remains WAIT mode until following events occurs: RESET (Watchdog, RESET pin) peripheral interrupt (timer, ADC,.), external interrupt (I/O port, NMI) Program Counter then branches starting address interrupt RESET service routine. Refer Figure also Section 7.4.1. Figure WAIT Mode Flowchart
OSCILLATOR WAIT INSTRUCTION Clock
Clock PERIPHERALS
RESET INTERRUPT
OSCILLATOR Clock
Restart
Clock PERIPHERALS
2048 32768 CLOCK CYCLE DELAY
OSCILLATOR
Clock PERIPHERALS Clock
FETCH RESET VECTOR SERVICE INTERRUPT
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STOP MODE STOP mode lowest power consumption mode (see Figure 22). goes into STOP mode soon STOP instruction executed. This following effects: Program execution stopped, microcontroller considered being "frozen". contents peripheral registers kept safely long power supply voltage higher than retention voltage. oscillator stopped, peripherals cannot work except those that driven external clock. Exit from STOP Mode remains STOP mode until following events occurs: RESET (Watchdog, RESET pin) peripheral interrupt (assuming this peripheral driven external clock) external interrupt (I/O port, NMI) cases delay 2048 32768 clock cycles (fINT) generated make sure oscillator started properly. Program Counter then points starting address interrupt RESET service routine (see Figure 21). STOP Mode Watchdog When Watchdog active (hardware software activation), STOP instruction disabled WAIT instruction will executed place unless EXCTNL option option bytes high level present pin. this case, STOP instruction will executed Watchdog will frozen. Figure STOP Mode Timing Overview
STOP 2048 32768 CLOCK CYCLE DELAY
STOP INSTRUCTION
RESET INTERRUPT
FETCH VECTOR
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STOP MODE (Cont'd) Figure STOP Mode Flowchart
STOP INSTRUCTION ENABLE
WATCHDOG DISABLE
EXCTNL VALUE
LEVEL
OSCILLATOR Clock PERIPHERALS Clock
OSCILLATOR Clock
RESET INTERRUPT
OSCILLATOR Clock Restart
Clock PERIPHERALS
Clock PERIPHERALS
RESET
2048 32768 CLOCK CYCLE DELAY
INTERRUPT
OSCILLATOR Clock
Clock PERIPHERALS
FETCH RESET VECTOR SERVICE INTERRUPT
Notes: EXCTNL option bit. option byte section more details. Peripheral clocked with external clock source still active. Only some specific interrupts exit from STOP mode (such external interrupt). Refer Interrupt Mapping table more details.
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NOTES RELATED WAIT STOP MODES 7.4.1 Exit from Wait Stop Modes 7.4.1.1 Interrupt should noted that when register (interrupts disabled), interrupt active cannot cause wake from STOP/WAIT modes. 7.4.1.2 Restart Sequence When exits from WAIT STOP mode, should noted that restart sequence depends original state (normal, interrupt non-maskable interrupt mode) prior entering WAIT STOP mode, well interrupt type. Normal Mode. main routine when WAIT STOP instruction executed, exit from Stop Wait mode will occur soon interrupt occurs; related interrupt routine executed and, completion, instruction which follows STOP WAIT instruction then executed, providing other interrupts pending. Maskable Interrupt Mode. STOP WAIT instruction been executed during execution non-maskable interrupt routine, exits from Stop Wait mode soon interrupt occurs: instruction which follows STOP WAIT instruction executed, remains non-maskable interrupt mode, even another interrupt been generated. Normal Interrupt Mode. interrupt mode before STOP WAIT instruction executed, exits from STOP WAIT mode soon interrupt occurs. Nevertheless, cases must considered: interrupt normal one, interrupt routine which WAIT STOP mode entered will completed, starting with execution instruction which follows STOP WAIT instruction, still interrupt mode. this routine pending interrupts will serviced according their priority. event non-maskable interrupt, non-maskable interrupt service routine processed first, then routine which WAIT STOP mode entered will completed executing instruction following STOP WAIT instruction. remains normal interrupt mode. 7.4.2 Recommended Configuration lowest power consumption during WAIT modes, user software must configure follows: Configure unused I/Os output push-pull mode Place peripherals their power down modes before entering STOP mode Select Frequency Auxiliary Oscillator (provided this runs lower frequency than main oscillator). WAIT STOP instructions executed enabled interrupt request pending.
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PORTS
INTRODUCTION Each port contains pins. Each programmed independently digital input (with without pull-up interrupt generation), digital output (open drain, push-pull) analog input (when available). pins used either standard alternate function mode. Standard mode used for: Transfer data through digital inputs outputs specific pins): External interrupt generation Alternate function mode used for: Alternate signal input/output on-chip peripherals generic block diagram shown Figure FUNCTIONAL DESCRIPTION Each port associated with registers located Data space: Data Register (DR) Data Direction Register (DDR) Option Register (OR) Each programmed using corresponding register bits DDR, registers: corresponding port. Table illustrates various port configurations which selected user software. During initialization, registers cleared input mode with pull-up interrupt generation selected pins, thus avoiding conflicts. 8.2.1 Digital Input Modes input configuration selected clearing corresponding register bit. this case, reading register returns digital value applied external pin. Different input modes selected software through registers, Table External Interrupt Function input lines individually connected software interrupt system programming registers accordingly. interrupt trigger modes (falling edge, rising edge level) configured software each port described Interrupt section. 8.2.2 Analog Inputs Some pins configured analog inputs programming registers accordingly, Table These analog inputs connected on-chip 8-bit Analog Digital Converter. Caution: ONLY should programmed analog input time, since selecting more than input simultaneously their pins will effectively shorted. 8.2.3 Output Modes output configuration selected setting corresponding register bit. this case, writing register applies this digital value through latch. Then, reading register returns previously stored value. different output modes selected software through register: push-pull open-drain. register value output status:
Push-pull Open-drain Floating
Note: open drain setting true open drain. This means same structure push-pull setting P-buffer deactivated. avoid damaging device, please respect VOUT absolute maximum rating described Electrical Characteristics section. 8.2.4 Alternate Functions When on-chip peripheral configured pin, alternate function (timer input/output.) systematically selected configured through DDR, registers. Refer chapter describing peripheral more details.
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PORTS (Cont'd) Figure Port Block Diagram
PULL-UP
RESET
DATA DIRECTION REGISTER
DATA REGISTER INTERNAL OPTION REGISTER P-BUFFER
N-BUFFER CLAMPING DIODES
CMOS INTERRUPT SCHMITT TRIGGER
Table Port ConfigurationDDR Mode Input Input Input Input Output Output With pull-up, interrupt pull-up, interrupt With pull-up with interrupt Analog input (when available) Open-drain output (20mA sink when available) Push-pull output (20mA sink when available) Option
Note: Don't care
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PORTS (Cont'd) 8.2.5 Instructions used access Port Data registers (SET, RES, DEC) READ-MODIFY-WRITE INSTRUCTIONS (SET, RES, DEC) PORT DATA REGISTERS PORT CONFIGURED INPUT MODE. These instructions make implicit read write back entire register. port input mode, however, data register reads from input pins directly, from data register latches. Since data register information input mode used characteristics input (interrupt, pull-up, analog input), these unintentionally reprogrammed depending state input pins. general rule, better only single instructions data registers when whole (8bit) port output mode. case inputs mixed inputs outputs, advisable keep copy data register RAM. Single instructions then used copy, after which whole copy register written port data register: bit, datacopy datacopy DRA, 8.2.6 Recommendations Safe State Switching Sequence Switching ports from state another should done sequence which ensures that unwanted side effects occur. recommended safe transitions illustrated Figure Interrupt Pull-up Input Analog transition (and vice-vesra) potentially risky should avoided when changing operating mode.
Handling Unused Port Bits ports that have less than external pins connected: Leave unbonded pins reset state change their configuration. instructions that whole port register (INC, DEC, read operations). Unavailable bits must masked software (AND instruction). Thus, when read operation performed incomplete port followed comparison, mask. High Impedance Input CMOS device, recommended connect high impedance input pins. choice these impedance done with respect maximum leakage current defined datasheet. risk close specification input levels applied device. POWER MODES WAIT STOP instructions allow ST62xx used situations where power consumption needed. lowest power consumption achieved configuring I/Os output push-pull mode.
Mode WAIT STOP Description effect ports. External interrupts cause device exit from WAIT mode. effect ports. External interrupts cause device exit from STOP mode.
INTERRUPTS external interrupt event generates interrupt corresponding configuration selected with DDR, registers (see Table GEN-bit register set.
Input Analog Input
Figure Diagram showing Safe State Transitions Interrupt 010* pull-up
Input pull-up (Reset state) Output Open Drain Output Push-pull
Output Open Drain Output Push-pull
Note DDR, Bits respectively
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PORTS (Cont'd) Table Port Option SelectionMODE AVAILABLE ON(1) SCHEMATIC
Input
PA0-PA7 PB0-PB7 PC4-PC7
Data Interrupt
DDRx
Reset state
Digital Input
Input with pull DDRx Input with pull with interrupt DDRx
PA0-PA7 PB0-PB7 PC4-PC7
Data Interrupt
PA0-PA7 PB0-PB7 PC4-PC7
Data Interrupt
Analog Input
Analog Input
PA4-PA7 PB0-PB7 PC4-PC7
DDRx
Open drain output (5mA) PA4-PA7 PB0-PB7 PC4-PC7 Open drain output PA0-PA3 Digital output DDRx PA4-PA7 PB0-PB7 PC4-PC7 Push-pull output PA0-PA3 DDRx
P-buffer disconnected
Data
Push-pull output (5mA)
Data
Note Provided correct configuration been selected (see Table
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PORTS (Cont'd) REGISTER DESCRIPTION DATA REGISTER (DR) Port Data Register with Addresses 0C0h, 0C1h 0C2h- Read /Write Reset Value: 0000 0000 (00h)
Bits DDR[7:0] Data direction register bits. register gives input/output direction configuration pins. Each cleared software. Input mode Output mode
OPTION REGISTER (OR) Port Option Register with Addresses: 0CCh, 0CDh 0CEh Read /Write Reset Value: 0000 0000 (00h)
Bits DR[7:0] Data register bits. Reading register returns either register latch content (pin configured output) digital value applied (pin configured input). Caution: input mode, modifying this register will modify port configuration (see Table Single instructions port data registers. (Section 8.2.5). DATA DIRECTION REGISTER (DDR) Port Data Direction Register DDRx with Addresses: 0C4h, 0C5h 0C6h Read /Write Reset Value: 0000 0000 (00h)
Bits OR[7:0] Option register bits. register allows distinguish output mode push-pull open drain configuration selected. Output mode: Open drain output(with P-Buffer deactivated) Push-pull Output Input mode: Table Each cleared software. Caution: Modifying this register, will also modify port configuration input mode. (see Table
DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0
Table Port Register Reset ValueAddress (Hex.) Register Label
Reset Value port registers 0C0h 0C1h 0C2h 0C4h 0C5h 0C6h 0CCh 0CDh 0CEh DDRA DDRB DDRC
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ON-CHIP PERIPHERALS
WATCHDOG TIMER (WDG) 9.1.1 Introduction Watchdog timer used detect occurrence software fault, usually generated external interference unforeseen logical conditions, which causes application program abandon normal sequence. Watchdog circuit generates reset expiry programmed time period, unless program refreshes counter's contents before becomes cleared. Figure Watchdog Block Diagram 9.1.2 Main Features Programmable timer steps 3072 clock cycles) Software reset Reset watchdog activated) when reaches zero Hardware software watchdog activation selectable option (Refer option bytes section)
RESET
WATCHDOG REGISTER (WDGR)
7-BIT DOWNCOUNTER
fint
CLOCK DIVIDER
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WATCHDOG TIMER (Cont'd) 9.1.3 Functional Description watchdog activation selected through option option bytes: HARDWARE Watchdog option After reset, watchdog permanently active, WDGR forced high user change However, this read equally SOFTWARE Watchdog option After reset, watchdog deactivated. function activated setting WDGR register. Once activated, cannot deactivated. counter value stored WDGR register (bits SR:T0), decremented every 3072 clock cycles. length timeout period programmed user steps 3072 clock cycles. watchdog activated setting bit) when cleared, watchdog initiates reset cycle pulling reset typically 500ns. application program must write WDGR register regular intervals during normal operation prevent reset. value stored WDGR register must between (see Table 11). watchdog function following conditions must true: (watchdog activated) prevent generating immediate reset T[5:0] bits contain number decrements which represent time delay before watchdog produces reset. Table Watchdog Timing (fOSC MHz)
WDGR Register initial value timeout period (ms) 24.576 0.384
mode availability (refer description WDACT EXTCNTL bits Option Bytes). When STOP mode required, hardware activation without EXTERNAL STOP MODE CONTROL should preferred, provides maximum security, especially during power-on. When STOP mode required, hardware activation EXTERNAL STOP MODE CONTROL should chosen. should high default, allow STOP mode entered when idle. connected line (see Figure allow state controlled software. line then used keep while Watchdog protection required, avoid noise bounce. When more processing required, line released device placed STOP mode lowest power consumption. Figure typical circuit making EXERNAL STOP MODE CONTROL feature
SWITCH
VR02002
Max. Min.
9.1.3.1 Software Reset used generate software reset clearing while set. 9.1.4 Recommendations Watchdog plays important supporting role high noise immunity ST62xx devices, should used wherever possible. Watchdog related options should selected basis trade-off between application security STOP
When software activation selected (WDACT Option byte) Watchdog activated, downcounter used simple 7bit timer (remember that bits reverse order). software activation option should chosen only when Watchdog counter used timer. ensure Watchdog been unexpectedly activated, following instructions should executed: WDGR, C=0,jump next WDGR, 0FDH SR=0 reset next
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WATCHDOG TIMER (Cont'd) These instructions test reset (i.e. disable Watchdog) (i.e. Watchdog active), thus disabling Watchdog. more information watchdog, please read application note AN1015.
Note: This note applies only when watchdog used standard timer. recommended read counter twice, sometimes return invalid value read performed while counter decremented (counter bits transient state). validate return value, both values read must equal. counter decrements every fOSC.
9.1.5 Power Modes Mode WAIT STOP Description effect Watchdog.
Behaviour depends EXTCNTL option Option bytes: Watchdog disabled: will enter Stop mode STOP instruction executed. Watchdog enabled EXTCNTL option disabled: STOP instruction encountered, interpreted WAIT. Watchdog EXTCNTL option enabled: STOP instruction encountered when low, interpreted WAIT. however, STOP instruction encountered when high, Watchdog counter frozen enters STOP mode. When exits STOP mode (i.e. when interrupt generated), Watchdog resumes activity.
9.1.6 Interrupts None.
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WATCHDOG TIMER (Cont'd) 9.1.7 Register Description WATCHDOG REGISTER (WDGR) Address: 0D8h Read /Write Reset Value: 1111 1110
Bits T[5:0] Downcounter bits Caution: These bits reversed shifted with respect physical counter: bit-7 (T0) Watchdog downcounter bit-2 (T5) MSB. Software Reset Software generate reset clearing this while set. When (Watchdog deactivated) 7-bit timer. Generate (write) software reset generated, 7-bit timer
Watchdog Control bit. hardware option selected (WDACT Option byte), this forced high cannot changed user (the Watchdog always active). When software option selected (WDACT Option byte), Watchdog function activated setting bit, cannot then deactivated (except resetting MCU). When kept cleared counter used 7-bit timer. Watchdog deactivated Watchdog activated
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8-BIT TIMER 9.2.1 Introduction 8-Bit Timer on-chip peripheral free running downcounter based 8-bit downcounter with 7-bit programmable prescaler, giving maximum count 215. peripheral configured three different operating modes. 9.2.2 Main Features Time-out downcounting mode with 15-bit accuracy External counter clock source (valid also STOP mode) Interrupt capability counter underflow Output signal generation External pulse length measurement Event counter timer used WAIT STOP modes wake MCU.
Figure Timer Block Diagram
TIMER fINT/12 TCR7 REGISTER TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 8-BIT DOWN COUNTER fCOUNTER
fEXT TOUT
LATCH
DOUT TSCR REGISTER
INTERRUPT
fPRESCALER
RELOAD
PSCR REGISTER
PSCR7 PSCR6 PSCR5 PSCR4 PSCR3 PSCR2 PSCR1 PSCR0 /128
PROGRAMMABLE PRESCALER
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8-BIT TIMER (Cont'd) 9.2.3 Counter/Prescaler Description Prescaler prescaler input internal frequency fINT divided external clock applied TIMER pin. prescaler decrements rising edge, depending division factor programmed PS[2:0] bits TSCR register. state 7-bit prescaler read PSCR register. When prescaler reaches automatically reloaded with 7Fh. Counter free running 8-bit downcounter output programmable prescaler, decremented every rising edge COUNTER clock signal coming from prescaler. possible read write contents counter fly, reading writing timer counter register (TCR). When downcounter reaches automatically reloaded with value 0FFh. Counter Clock Prescaler counter clock frequency given fCOUNTER fPRESCALER 2PS[2:0] where fPRESCALER fINT/12 fEXT (input TIMER pin) fINT/12 gated TIMER timer input clock feeds 7-bit programmable prescaler. prescaler output programmed selecting available prescaler taps using PS[2:0] bits Status/Control Register (TSCR). Thus division factor prescaler (where equals Figure clock input enabled (Prescaler Initialize) TSCR register. When reset, counter frozen prescaler loaded with value 7Fh. When set, pres-
caler counter rate selected clock source. Counter Prescaler Initialization After RESET, counter prescaler initialized 0FFh respectively. 7-bit prescaler initialized clearing bit. Direct write access prescaler also possible when Then, value between loaded into 8-bit counter initialized separately writing register. 9.2.3.1 8-bit Counting Interrupt Capability Counter Underflow Whatever division factor defined prescaler, Timer Counter works 8-bit downcounter. input clock frequency user selectable using PS[2:0] bits. When downcounter decrements zero, (Timer Zero) TSCR set. (Enable Timer Interrupt) TSCR also set, interrupt request generated. Timer interrupt used exit from WAIT STOP mode. written time software define time period ending with underflow event, therefore manage delay timer functions. when downcounter reaches zero; however, also writing register setting TSCR register. must cleared user software when servicing timer interrupt avoid undesired interrupts when leaving interrupt service routine. Note: write register will predominate over 8-bit counter decrement function, i.e. write register decrement occur simultaneously, write will take precedence, until 8-bit counter underflows again.
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8-BIT TIMER (Cont'd) 9.2.4 Functional Description There three operating modes, which selected TOUT DOUT bits (see TSCR register). These three modes correspond clocks which connected 7-bit prescaler (fINT TIMER signal), output mode. settings different operating modes summarized Table Table Timer Operating ModeTOUT DOUT Timer Function Event Counter (input) Gated input (input) Output (output) Output (output) Application External counter clock source External Pulse length measurement Output signal generation
DDR, registers. more details, please refer Ports section. Figure fTIMER Clock Gated Mode
fINT/12 fPRESCALER
TIMER
fEXT
Figure Gated Mode Operation
COUNTER VALUE VALUE
VALUE
TIMER PULSE LENGTH
9.2.4.1 Gated Mode (TOUT "0", DOUT "1") this mode, prescaler decremented Timer clock input, only when signal TIMER held high INT/12 gated TIMER pin). Figure Figure This mode selected clearing TOUT TSCR register (i.e. input) setting DOUT bit. Note: this mode, TIMER multiplexed, corresponding port control bits have input with pull-up configuration through
TIMER CLOCK
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8-BIT TIMER (Cont'd) 9.2.4.2 Event Counter Mode (TOUT "0", DOUT "0") this mode, TIMER input clock Timer prescaler which decremented every rising edge input clock (allowing event count). Figure Figure This mode selected clearing TOUT TSCR register (i.e. input) clearing DOUT bit. Note: this mode, TIMER multiplexed, corresponding port control bits have input with pull-up configuration. Figure fTIMER Clock Event Counter Mode
transition used latch DOUT TSCR and, TOUT set, DOUT transferred TIMER pin. This operating mode allows external signal generation TIMER pin. Figure This mode selected setting TOUT TSCR register (i.e. output) setting DOUT output high level clearing DOUT output level. Note: soon TOUT set, timer configured output push-pull regardless corresponding port control registers setting TIMER multiplexed). Figure Output Mode Control
TIMER
fPRESCALER
TIMER
LATCH
Figure Event Counter Mode Operation
COUNTER VALUE VALUE TOUT DOUT
Figure Output Mode Operation
Counter
TIMER VALUE
TIMER
9.2.4.3 Output Mode (TOUT "1", DOUT "data out") Output mode, TIMER connected DOUT latch, hence Timer prescaler clocked prescaler clock input (fINT/12). Figure user select prescaler division ratio using PS[2:0] bits TSCR register. When decrements zero, sets TSCR. tested under program control perform timer function whenever goes high cleared user. low-to-high
each zero event DOUT copied TIMER
downcount: Default output value
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8-BIT TIMER (Cont'd) 9.2.5 Power ModeMode WAIT Description effect timer. Timer interrupt events cause device exit from WAIT mode. Timer registers frozen except Event Counter mode (with external clock TIMER pin).
9.2.6 InterruptInterrupt Event Timer Zero Event Event Flag Enable Exit from Wait Exit from Stop
STOP
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8-BIT TIMER (Cont'd) 9.2.7 Register Description PRESCALER COUNTER REGISTER (PSCR) Address: 0D2h Read/Write Reset Value: 0111 1111 (7Fh)
ETI=0 timer interrupt disabled. ETI=1 TMZ=1 interrupt request generated. Interrupt disabled (reset state) Interrupt enabled TOUT Timer Output Control. When low, this selects input mode TIMER pin. When high output mode selected. Input mode (reset state) Output mode, TIMER configured push-pull output DOUT Data Output. Data sent timer output when high (output mode only). Input mode selection (input mode only). PSI: Prescaler Initialize bit. Used initialize prescaler inhibit counting. When PSI="0" prescaler counter inhibited. When PSI="1" prescaler enabled count downwards. long PSE="1" both counter prescaler running Counting disabled Counting enabled Bits PS[2:0] Prescaler Mux. Select. These bits select division ratio prescaler register. Table Prescaler Division FactorPS2 Divided
PSCR PSCR PSCR PSCR PSCR PSCR PSCR PSCR
PSCR7: used, always read "0". Bits PSCR[6:0] Prescaler LSB. TIMER COUNTER REGISTER (TCR) Address: 0D3h Read Write Reset Value: 1111 1111 (FFh)
TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
Bits TCR[7:0] Timer counter bits. TIMER STATUS CONTROL REGISTER (TSCR) Address: 0D4h Read/Write Reset Value: 0000 0000 (00h)
TOUT DOUT
Timer Zero bit. low-to-high transition indicates that timer count register underflowed. means that value changed from FFh. This must cleared user software. Counter underflowed Counter underflow occurred Enable Timer Interrupt. When set, enables timer interrupt request.
Table 8-Bit Timer Register Reset ValueAddress (Hex.) 0D2h 0D3h 0D4h Register Label PSCR Reset Value Reset Value TSCR Reset Value PSCR7 TCR7 PSCR6 TCR6 PSCR5 TCR5 TOUT PSCR4 TCR4 DOUT PSCR3 TCR3 PSCR2 TCR2 PSCR1 TCR1 PSCR0 TCR0
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CONVERTER (ADC) 9.3.1 Introduction on-chip Analog Digital Converter (ADC) peripheral 8-bit, successive approximation converter. This peripheral multiplexed analog input channels (refer device description) that allow peripheral convert analog voltage levels from different sources. result conversion stored 8-bit Data Register. converter controlled through Control Register. 9.3.2 Main Features 8-bit conversion Multiplexed analog input channels Linear successive approximation Data register (DR) which contains results Conversion flag On/Off reduce consumption) Typical conversion time (with crystal) block diagram shown Figure
Figure Block Diagram
fINT
fADC
ADCR
AIN0 AIN1 PORT AINx
PORT
ANALOG DIGITAL CONVERTER
DDRx
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
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CONVERTER (Cont'd) 9.3.3 Functional Description 9.3.3.1 Analog Power Supply high level reference voltage pins internally connected pins. Conversion accuracy therefore impacted voltage drops noise event heavily loaded badly decoupled power supply lines. 9.3.3.2 Digital Conversion Result conversion monotonic, meaning that result never decreases analog input does never increases analog input does not. input voltage (VAIN) greater than equal (high-level voltage reference) then conversion result register (full scale) without overflow indication. input voltage (VAIN) lower than equal VSSA (low-level voltage reference) then conversion result register 00h. converter linear digital result conversion stored register. accuracy conversion described parametric section. RAIN maximum recommended impedance analog input signal. impedance high, this will result loss accuracy leakage sampling being completed allocated time. Refer electrical characteristics chapter more details. With oscillator clock frequency less than 1.2MHz, conversion accuracy decreased. 9.3.3.3 Analog Input Selection Selection input done configuring related line analog input Data Direction, Option Data registers (refer ports description additional information). Caution: Only line must configured analog input time. user must avoid situation which more than selected analog input simultaneously, because they will shorted internally.
9.3.3.4 Software Procedure Refer Control register (ADCR) Data register (ADR) Section 9.3.7 definitions. Analog Input Configuration analog input must configured through Port Control registers (DDRx, DRx). Refer port chapter. Configuration ADCR register: Reset power ADC. This must least instruction before beginning conversion allow stabilisation converter. enable interrupt needed. Conversion ADCR register: start conversion. This automatically clears (resets "0") Conversion (EOC). When conversion complete hardware flag that conversion complete that data data conversion register valid. interrupt generated Setting will start count will clear (thus clearing interrupt condition) Note: Setting must done different instruction from instruction that powers-on (setting bit) order make sure voltage converted present pin. Each conversion separately initiated writing bit. continuously scanned that, user sets while previous conversion progress, conversion started before completing previous one. start (STA) write only bit, attempt read will show logical "0".
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CONVERTER (Cont'd) 9.3.4 Recommendations following notes provide additional information using converter. 1.The converter does feature sample hold circuit. analog voltage measured should therefore stable during entire conversion cycle. Voltage variation should exceed ±1/2 optimum conversion accuracy. pass filter used analog input pins reduce input voltage variation during conversion. When selected analog channel, input internally connected capacitor typically 9pF. maximum accuracy, this capacitor must fully charged beginning conversion. worst case, conversion starts instruction (6.5 after channel been selected. impedance analog voltage source (ASI) worst case conditions, calculated using following formula: 6.5µs (capacitor charged over 99.9%), i.e. including guardband. higher been charged longer period adding instructions before start conversion (adding more than cycles pointless). Since same chip microprocessor, user should switch heavily loaded output signals during conversion, high precision required. Such switching will affect supply voltages used analog references. Conversion accuracy depends quality power supplies VSS). user must take special care ensure well regulated reference voltage present pins (power supply voltage variations must less than 0.1V/ms). This implies, particular, that suitable decoupling capacitor used pin. converter resolution given
-256
bances power supply variations output switching. Nevertheless, WAIT instruction should executed soon possible after beginning conversion, because execution WAIT instruction cause small variation voltage. negative effect this variation minimized beginning conversion when converter less sensitive, rather than conversion, when least significant bits determined. best configuration, from accuracy standpoint, WAIT mode with Timer stopped. this case only peripheral oscillator then still working. must woken from WAIT mode interrupt conversion. microcontroller also woken Timer interrupt, this means Timer must running resulting noise could affect conversion accuracy. Caution: When used analog input, conversion accuracy will impaired negative current injections (VINJ occur from adjacent pins with analog input capability. Refer Figure avoid this: another port located further away from analog pin, preferably multiplexed converter Increase input resistance reduce current injections) reduce RADC preserve conversion accuracy). Figure Leakage from Digital Input
Digital Input RINJ VINJ PBy/AINy
Port (Digital I/O)
Input voltage (Ain) which converted must constant before conversion remain constant during conversion. Conversion resolution improved power supply voltage microcontroller lowered. order optimize conversion resolution, user configure microcontroller WAIT mode, because this mode minimises noise distur-
Leakage Current VINJ
Analog Input PBx/AINx RADC VAIN
Converter
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CONVERTER (Cont'd) 9.3.5 Power ModeMode WAIT STOP Description effect Converter. interrupts cause device exit from Wait mode. Converter disabled.
cally cleared when set. Data data conversion register valid only when this "1". Conversion complete Conversion read from register Start Conversion. Write Only. effect Start conversion Note: Setting this automatically clears bit. again when conversion progress, present conversion stopped will take place. This write only, attempt read will show logical zero. Power Down Selection. converter switched converter switched ADCR3 Reserved, must cleared. OSCOFF Main Oscillator off. Main Oscillator enabled Main Oscillator disabled Note: This does apply peripheral main clock system. Refer Clock System section. Bits ADCR[1:0] Reserved, must cleared. CONVERTER DATA REGISTER (ADR) Address: 0D0h Read only Reset value: xxxx xxxx (xxh)
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
Note: converter disabled clearing bit. This feature allows reduced power consumption when conversion needed. 9.3.6 InterruptInterrupt Event Conversion Event Flag Enable Exit from Wait Exit from Stop
Note: cleared only when conversion started cannot cleared writing avoid generating further interrupt, cleared within interrupt subroutine. 9.3.7 Register Description CONVERTER CONTROL REGISTER (ADCR) Address: 0D1h Read/Write (Bit Read Only, Write Only) Reset value: 0100 0000 (40h)
ADCR ADCR ADCR
Enable Interrupt. interrupt disabled interrupt enabled conversion. Read Only When conversion been completed, this hardware interrupt request generated set. automatiTable Register Reset ValueAddress (Hex.) 0D0h 0D1h Register Label Reset Value ADCR Reset Value ADR7 ADR6 ADR5
ADR7
Bits ADR[7:0]: Conversion Result.
ADR4
ADR3 ADCR3
ADR2 OSCOFF
ADR1 ADCR1
ADR0 ADCR0
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INSTRUCTION
10.1 ARCHITECTURE architecture been designed maximum efficiency while keeping byte usage minimum; short, provide byte-efficient programming. core ability clear register location Data space using single instruction. Furthermore, programs branch selected address depending status Data space. 10.2 ADDRESSING MODES nine addressing modes, which described following paragraphs. Three different address spaces available: Program space, Data space, Stack space. Program space contains instructions which executed, plus data immediate mode instructions. Data space contains Accumulator, registers, peripheral Input/Output registers, locations Data locations (for storage tables constants). Stack space contains 12-bit cells used stack return addresses subroutines interrupts. Immediate. immediate addressing mode, operand instruction follows opcode location. operand byte, immediate addressing mode used access constants which change during program execution (e.g., constant used initialize loop counter). Direct. direct addressing mode, address byte which processed instruction stored location which follows opcode. Direct addressing allows user directly address bytes Data Space memory with single two-byte instruction. Short Direct. core address four registers (locations 80h, 81h, 82h, 83h) short-direct addressing mode. this case, instruction only byte selection location processed contained opcode. Short direct addressing subset direct addressing mode. (Note that also indirect registers). Extended. extended addressing mode, 12bit address needed define instruction obtained concatenating four least significant bits opcode with byte following opcode. instructions (JP, CALL) which extended addressing mode able branch address Kbyte Program space. Extended addressing mode instructions bytes long. Program Counter Relative. Relative addressing mode only used conditional branch instructions. instruction used perform test and, condition true, branch with span locations next address relative instruction. condition true, instruction which follows relative instruction executed. Relative addressing mode instructions byte long. opcode obtained adding three most significant bits which characterize test condition, which determines whether forward branch (when backward branch (when four least significant bits which give span branch which must added subtracted from address relative instruction obtain branch destination address. Direct. direct addressing mode, cleared part opcode, byte following opcode points address byte which specified must cleared. Thus, locations Data space memory cleared. Test Branch. test branch addressing mode combination direct addressing relative addressing. test branch instructions three bytes long. identification test condition included opcode byte. address byte tested given next byte. third byte jump displacement, which range -127 +128. This displacement determined using label, which converted assembler. Indirect. indirect addressing mode, byte processed register-indirect instruction address pointed content indirect registers, (80h, 81h). indirect register selected opcode. Register indirect instructions byte long. Inherent. inherent addressing mode, information necessary executing instruction contained opcode. These instructions byte long.
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10.3 INSTRUCTION offers basic instructions which, when combined with nine addressing modes, yield usable opcodes. They divided into different types: load/store, arithmetic/logic, conditional branch, control instructions, jump/call, manipulation. following paragraphs describe different types. instructions belonging given type presented individual tables. Table Load Store InstructionInstruction (X), (Y), Addressing Mode Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Indirect Indirect Immediate Immediate Bytes Cycles Flags
Load Store. These instructions one, three bytes depending addressing mode. LOAD, operand Accumulator other operand obtained from data memory using addressing modes. Load Immediate, operand data space bytes while other always immediate data.
Legend: Index Registers, Short Direct Registers Immediate data (stored memory) Data space register Affected Affected
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INSTRUCTION (Cont'd) Arithmetic Logic. These instructions used perform arithmetic calculations logic operations. AND, ADD, instructions operand always accumulator while, depending addressing mode, other Table Arithmetic Logic InstructionInstruction ADDI ANDI SUBI
Notes: Index Registers Short Direct Registers Affected
either data space memory location immediate value. CLR, DEC, instructions operand data space addresses. COM, RLC, operand always accumulator.
Addressing Mode Indirect Indirect Direct Immediate Indirect Indirect Direct Immediate Short Direct Direct Inherent Indirect Indirect Direct Immediate Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Inherent Inherent Indirect Indirect Direct Immediate
Bytes
Cycles
Flags
Immediate data (stored memory) Affected Data space register
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INSTRUCTION (Cont'd) Conditional Branch. Branch instructions perform branch program when selected condition met. Manipulation Instructions. These instructions handle Data space memory. group either sets clears. other group (see Conditional Branch) performs test branch operations. Table Conditional Branch InstructionInstruction JRNC JRNZ Branch Bytes
Control Instructions. Control instructions control microcontroller operations during program execution. Jump Call. These instructions used perform long (12-bit) jumps subroutine calls location whole program space.
Cycles
Flags
Notes: 3-bit address signed displacement range signed displacement range -126 +129
Data space register Affected. tested shifted into carry. Affected
Table Manipulation InstructionInstruction b,rr b,rr Addressing Mode Direct Direct Bytes Cycles Flags
Notes: 3-bit address Affected Data space register Manipulation Instructions should used Port Data Registers registers with read only and/or write only bits (see port chapter)
Table Control InstructionInstruction RETI STOP WAIT Addressing Mode Inherent Inherent Inherent Inherent Inherent Bytes Cycles Flags
Notes: This instruction deactivated WAIT automatically executed instead STOP watchdog function selected. Affected *Not Affected
Table Jump Call InstructionInstruction CALL
Notes: 12-bit address Affected
Addressing Mode Extended Extended
Bytes
Cycles
Flags
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Opcode Summary. following table contains opcode instructions used
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ 0001 CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL 0010 JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC 0011 b0,rr,ee b0,rr,ee b4,rr,ee b4,rr,ee b2,rr,ee b2,rr,ee b6,rr,ee b6,rr,ee b1,rr,ee b1,rr,ee b5,rr,ee b5,rr,ee b3,rr,ee b3,rr,ee b7,rr,ee b7,rr,ee a,(x) ANDI a,nn a,(x) SUBI a,nn (x),a 0100 0101 0110 a,(x) a,nn a,(x) a,nn a,(x) ADDI a,nn 0111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Abbreviations Addressing Modes: Direct Short Direct Immediate Inherent Extended Direct Test Program Counter Relative Indirect
Legend: Indicates Illegal Instructions 5-bit Displacement 3-bit Address 1-byte Data space address 1-byte immediate data 12-bit address 8-bit displacement
Cycles Operands Bytes Addressing Mode
Mnemonic
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Opcode Summary (Continued)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1000 JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ 1001 1010 JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC 1011 b0,rr b0,rr b4,rr b4,rr b2,rr b2,rr b6,rr b6,rr b1,rr b1,rr b5,rr b5,rr b3,rr b3,rr b7,rr b7,rr WAIT STOP RETI 1100 1101 rr,nn a,rr a,(y) a,rr (y),a rr,a a,(y) a,rr a,(y) a,rr a,(y) a,rr 1110 a,(y) 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Abbreviations Addressing Modes: Direct Short Direct Immediate Inherent Extended Direct Test Program Counter Relative Indirect
Legend: Indicates Illegal Instructions 5-bit Displacement 3-bit Address 1-byte Data space address 1-byte immediate data 12-bit address 8-bit Displacement
Cycles Operands Bytes Addressing Mode
Mnemonic
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ELECTRICAL CHARACTERISTICS
11.1 PARAMETER CONDITIONS Unless otherwise specified, voltages referred 11.1.1 Minimum Maximum Values Unless otherwise specified minimum maximum values guaranteed worst conditions ambient temperature, supply voltage frequencies tests production 100% devices with ambient temperature TA=25°C TA=TAmax (given selected temperature range). Data based characterization results, design simulation and/or technology characteristics indicated table footnotes tested production. Based characterization, minimum maximum values refer sample tests represent mean value plus minus three times standard deviation (mean±3). 11.1.2 Typical Values Unless otherwise specified, typical data based TA=25°C, VDD=5V (for 4.5VVDD6.0V voltage range) VDD=3.3V (for 3VVDD3.6V voltage range). They given only design guidelines tested. 11.1.3 Typical Curves Unless otherwise specified, typical curves given only design guidelines tested. 11.1.4 Loading Capacitor loading conditions used parameter measurement shown Figure Figure Loading Condition
11.1.5 Input Voltage input voltage measurement device described Figure Figure Input Voltage
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11.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed "absolute maximum ratings" cause permanent damage device. This stress rating only functional operation device under these condi11.2.1 Voltage CharacteristicSymbol VOUT VESD(HBM) Supply voltage Input voltage Output voltage Electro-static discharge voltage (Human Body Model) Rating
tions implied. Exposure maximum rating conditions extended periods affect device reliability.
Maximum value VSS-0.3 VDD+0.3 VSS-0.3 VDD+0.3 3500
Unit
11.2.2 Current CharacteristicSymbol IVDD IVSS Ratings Total current into power lines (source)
Maximum value
Unit
Total current ground lines (sink) Output current sunk standard control Output current sunk high sink Output current source I/Os control Injected current RESET Injected current other
IINJ(PIN)
11.2.3 Thermal CharacteristicSymbol TSTG Ratings Storage temperature range Maximum junction temperature (see THERMAL CHARACTERISTICS section) Value +150 Unit
Notes: Directly connecting RESET pins could damage device unintentional internal reset generated unexpected change configuration occurs (for example, corrupted program counter). guarantee safe operation, this connection done through pull-up pull-down resistor (typical: 4.7k RESET, I/Os). Unused pins must tied same according their reset configuration. When current limitation possible, absolute maximum rating must respected, otherwise refer IINJ(PIN) specification. positive injection induced VIN>VDD while negative injection induced VIN<VSS. Power (VDD) ground (VSS) lines must always connected external supply. Negative injection disturbs analog performance device. particular, induces leakage currents throughout device including analog inputs. avoid undesirable effects analog functions, care must taken: Analog input pins must have negative injection less than (assuming that impedance analog voltage lower than specified limits). Pure digital pins must have negative injection less than 1mA. addition, recommended inject current possible from analog input pins.
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11.3 OPERATING CONDITIONS 11.3.1 General Operating ConditionSymbol Parameter Supply voltage Conditions Figure VDD=3.0V, Suffix fOSC Oscillator frequency VDD=3.0V, Suffix VDD=3.6V, 6Suffix VDD=3.6V, Suffix fOSC=4MHz, Suffix Operating Supply Voltage fOSC=4MHz, Suffix fOSC=8MHz, Suffix fOSC=8MHz, Suffix Suffix Version Ambient temperature range Suffix Version Suffix Version Notes: oscillator frequency above 1.2MHz recommended reliable results. Operating conditions with TA=-40 +125°C. Unit
Figure fOSC Maximum Operating Frequency Versus Supply Voltage devicefOSC [MHz] suffix version FUNCTIONALITY GUARANTEED THIS AREA SUPPLY VOLTAGE suffix version fOSG
fOSG
this area, operation guaranteed quartz crystal frequency. When disabled, operation this area guaranteed crystal frequency. When enabled, operation this area guaranteed frequency least fOSG Min. When disabled, operation this area guaranteed quartz crystal frequency. When enabled, access this area prevented. internal frequency kept fOSG.
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OPERATING CONDITIONS (Cont'd) 11.3.2 Operating Conditions with Voltage Detector (LVD) Subject general operating conditions fOSC,
Symbol VIT+ VITVhys VtPOR tg(VDD) Parameter Reset release threshold (VDD rise) Reset generation threshold (VDD fall) voltage threshold hysteresis rise time rate Filtered glitch delay detected VIT+-VITConditions mV/s Unit
Notes: typical data based TA=25°C. They given only design guidelines tested. minimum rise time rate needed insure correct device power-on reset. tested production. Data based characterization results, tested production.
Figure Threshold Versus fOSC3)
fOSC [MHz] DEVICE UNDER RESET THIS AREA VIT-3.6 FUNCTIONALITY GUARANTEED THIS AREA
FUNCTIONAL AREA SUPPLY VOLTAGE
Figure Typical Thresholds Versus Temperature device
Figure Typical thresholds Temperature device
Thresholds
Thresholds
VIT+ VIT- down
VIT+ VIT- down
-40°C 25°C [°C] 95°C 125°C
-40°C 25°C [°C] 95°C 125°C
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11.4 SUPPLY CURRENT CHARACTERISTICS following current consumption specified functional operating modes over temperature range does take into account clock source current consumption. total de11.4.1 ModeSymbol Parameter 3VVDD3.6V 4.5VVDD6.0V
vice consumption, current values must added (except STOP mode which clock stopped).
Conditions fOSC=32kHz fOSC=1MHz fOSC=2MHz fOSC=4MHz fOSC=8MHz fOSC=32kHz fOSC=1MHz fOSC=2MHz fOSC=4MHz fOSC=8MHz
Unit
Supply current mode (see Figure Figure
Supply current mode (see Figure Figure
Notes: Typical data based TA=25°C, VDD=5V (4.5VVDD6.0V range) VDD=3.3V (3VVDD3.6V range). Data based characterization results, tested production max. fOSC max. running with memory access, pins input with pull-up mode load), peripherals reset state; clock input (OSCIN) driven external square wave, disabled, option bytes programmed.
Figure Typical fCPU
[mA] 8MHz 4MHz 2MHz 1MHz 32KHz
Figure Typical Temperature (VDD
[mA] 8MHz 4MHz 2MHz 1MHz 32KHz
T[°C]
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 11.4.2 WAIT ModeSymbol Parameter Supply current WAIT mode Option bytes programmed (see Figure 4.5VVDD6.0V Conditions fOSC=32kHz fOSC=1MHz fOSC=2MHz fOSC=4MHz fOSC=8MHz fOSC=32kHz fOSC=1MHz fOSC=2MHz fOSC=4MHz fOSC=8MHz fOSC=32kHz fOSC=1MHz fOSC=2MHz fOSC=4MHz fOSC=8MHz fOSC=32kHz fOSC=1MHz fOSC=2MHz fOSC=4MHz fOSC=8MHz fOSC=32kHz fOSC=1MHz fOSC=2MHz fOSC=4MHz fOSC=8MHz fOSC=32kHz fOSC=1MHz fOSC=2MHz fOSC=4MHz fOSC=8MHz Unit
Supply current WAIT mode Option bytes programmed (see Figure
Supply current WAIT mode (see Figure
device
device
Supply current WAIT mode Option bytes programmed (see Figure
3VVDD3.6V
Supply current WAIT mode Option bytes programmed (see Figure
Notes: Typical data based TA=25°C, VDD=5V (4.5VVDD6.0V range) VDD=3.3V (3VVDD3.6V range). Data based characterization results, tested production max. fOSC max. pins input with pull-up mode load), peripherals reset state; clock input (OSCIN) driven external square wave, disabled.
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device
device
Supply current WAIT mode Option bytes programmed (see Figure
ST6215C/ST6225C
SUPPLY CURRENT CHARACTERISTICS (Cont'd) Figure Typical WAIT fCPU Temperature devices with option bytes programmed
[µA] 8MHz T[°C] 4MHz 2MHz 32KHz [µA] 8MHz 4MHz 2MHz 1MHz 32KHz
Figure Typical WAIT fCPU Temperature devices with option bytes programmed
[µA] 8MHz 4MHz 2MHz
[µA]
32KHz
8MHz 4MHz 2MHz
1MHz 32KHz
T[°C]
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) Figure Typical WAIT fCPU Temperature deviceIDD [µA] 8MHz 4MHz 2MHz T[°C] 32KHz [µA] 8MHz 4MHz 2MHz 1MHz 32KHz
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 11.4.3 STOP Mode
Symbol Parameter Supply current STOP mode (see Figure Figure devices Conditions Unit
device
Notes: Typical data based VDD=5.0V TA=25°C. pins input with pull-up mode load), peripherals reset state, disabled, option bytes programmed 00H. Data based characterization results, tested production max. fCPU max. Maximum STOP consumption -40°C<Ta<90°C Maximum STOP consumption -40°C<Ta<125°C
Figure Typical STOP Temperature deviceIDD [nA] 1200 Ta=-40°C 1000 Ta=25°C Ta=95°C Ta=125°C
Figure Typical STOP Temperature deviceIDD [nA] Ta=-40°C 1500 Ta=25°C Ta=95°C Ta=125°C
1000
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 11.4.4 Supply Clock System previous current consumption specified functional operating modes over temperature range does take into account clock
Symbol Parameter
source current consumption. total device consumption, current values must added (except STOP mode).
Conditions Unit
Supply current oscillator
fOSC=32 kHz, fOSC=1 fOSC=2 fOSC=4 fOSC=8
VDD=5.0
IDD(CK)
fOSC=32 kHz, fOSC=1 fOSC=2 fOSC=4 fOSC=8 fOSC=32 kHz, fOSC=1 fOSC=2 fOSC=4 fOSC=8MHz fOSC=32 kHz, fOSC=1 fOSC=2 fOSC=4 fOSC=8
VDD=5.0 VDD=5.0 VDD=5.0
VDD=3.3
VDD=5.0
Supply current resonator oscillator
VDD=3.3
IDD(LFAO) IDD(OSG) IDD(LVD)
LFAO supply current supply current supply current
11.4.5 On-Chip PeripheralSymbol IDD(TIM) Parameter 8-bit Timer supply current supply current when converting
Conditions fOSC=8 fOSC=8 VDD=5.0 VDD=3.3 VDD=5.0 VDD=3.3
Unit
IDD(ADC)
Notes: Typical data based TA=25°C. Data based characterization results, tested production. Data based differential measurement between reset configuration (OSG LFAO disabled) LFAO running (also includes stand alone consumption). Data based differential measurement between reset configuration with disabled enabled. Data based differential measurement between reset configuration with disabled enabled. Data based differential measurement between reset configuration (timer disabled) timer running. Data based differential measurement between reset configuration continuous conversions.
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11.5 CLOCK TIMING CHARACTERISTICS Subject general operating conditions fOSC, 11.5.1 General TimingSymbol tc(INST) tv(IT) Parameter Instruction cycle time Interrupt reaction time tv(IT) tc(INST)
Conditions fCPU=8 fCPU=8
3.25 9.75
8.125 17.875
Unit tCPU tCPU
11.5.2 External Clock Source
Symbol VOSCINH VOSCINL Parameter OSCIN input high level voltage OSCIN input level voltage OSCx Input leakage current Conditions Figure VSSVINVDD 0.7xVDD 0.3xVDD Unit
Notes: Data based typical application software. Time measured between interrupt event interrupt vector fetch. tc(INST) number tCPU cycles needed finish current instruction execution.
Figure Typical Application with External Clock Source
VOSCINH VOSCINL
connected
OSCOUT
fOSC EXTERNAL CLOCK SOURCE OSCIN ST62XX
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CLOCK TIMING CHARACTERISTICS (Cont'd) 11.5.3 Crystal Ceramic Resonator Oscillators internal clock supplied with several different Crystal/Ceramic resonator oscillators. Only parallel resonant crystals used. information given this paragraph based
Symbol Feedback resistor Parameter
characterization results with specified typical external components. Refer crystal/ceramic resonator manufacturer more details (frequency, package, accuracy.).
Conditions fOSC=32 kHz, fOSC=1 fOSC=2 fOSC=4 fOSC=8 Unit
Recommended load capacitances versus equivalent crystal ceramic resonator frequency
Oscillator
Typical Crystal Ceramic Resonators Reference CSB455E MURATA Freq. Characteristic
tSU(osc) [pF] [pF] [ms]
455KHz 1MHz CSB1000J CSTCC2.00MG0H6 2MHz CSTCC4.00MG0H6 4MHz 8MHz CSTCC8.00MG
Notes: Resonator characteristics given crystal/ceramic resonator manufacturer. tSU(OSC) typical oscillator start-up time measured between VDD=2.8V fetch first instruction (with quick ramp-up from (<50µs). oscillator selection optimized terms supply current using high quality resonator with small value. Refer crystal/ceramic resonator manufacturer more details.
Figure Typical Application with Crystal Ceramic Resonator
OSCIN
Ceramic
RESONATOR OSCOUT
FOSC
ST62XX
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CLOCK TIMING CHARACTERISTICS (Cont'd) 11.5.4 Oscillator internal clock supplied with external oscillator. Depending RNET value, accuracy frequency about 20%, suitable some applications.
Symbol Parameter 3VVDD3.6V 4.5VVDD6.0V Conditions RNET=22 RNET=47 RNET=100 RNET=220 RNET=470 RNET=22 RNET=47 RNET=100 RNET=220 RNET=470 Figure Figure 0.95 0.55 Unit
fOSC
oscillator frequency
RNET
Oscillator external resistor
Notes: Data based characterization results, tested production. These measurements were done with OSCin unconnected (only soldered PCB). RNET must have positive temperature coefficient (ppm/°C), carbon resistors should therefore used.
Figure Typical Application with Oscillator
EXTERNAL OSCOUT
MIRROR CURRENT RNET fOSC OSCIN
CEX~9pF DISCHARGE
ST62XX
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ST6215C/ST6225C
CLOCK TIMING CHARACTERISTICS (Cont'd) Figure Typical Oscillator frequency
fosc [MHz] Rnet=22KOhm Rnet=47KOhm Rnet=100KOhm Rnet=220KOhm Rnet=470KOhm [°C]
Figure Typical Oscillator frequency Temperature (VDD
fosc [MHz] Rnet=22KOhm Rnet=47KOhm Rnet=100KOhm Rnet=220KOhm Rnet=470KOhm
11.5.5 Oscillator Safeguard (OSG) Frequency Auxiliary Oscillator (LFAO)
Symbol fLFAO Parameter Frequency Auxiliary Oscillator Frequency Internal Frequency with enabled Conditions TA=25° VDD=5.0 TA=25° VDD=3.3 TA=25° VDD=4.5 Unit
fOSG
TA=25° VDD=3.3
Figure Typical LFAO Frequenciefosc [kHz] Ta=-40°C Ta=25°C Ta=125°C
Note: Data based characterization results.
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ST6215C/ST6225C
11.6 MEMORY CHARACTERISTICS Subject general operating conditions fOSC, unless otherwise specified. 11.6.1 Hardware RegisterSymbol Parameter Data retention1) Conditions Unit
11.6.2 EPROM Program Memory
Symbol tret Data Parameter retention Conditions TA=+55°C
Unit year
Figure EPROM Retention Time Temperature
Retention time [Years] 100000 10000 1000 Temperature [°C]
Notes: Minimum supply voltage without losing data stored STOP mode under RESET) hardware registers (only STOP mode). Guaranteed construction, tested production. Data based reliability test results monitored production. data retention time increases when decreases, Figure
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ST6215C/ST6225C
11.7 CHARACTERISTICS Susceptibility tests performed sample basis during product characterization. 11.7.1 Functional (Electro Magnetic Susceptibility) Based simple running application product (toggling LEDs through ports), product stressed electro magnetic events until failure occurs (indicated LEDs). ESD: Electro-Static Discharge (positive negative) applied pins device until functional disturbance occurs. This test conforms with 1000-4-2 standard. FTB: Burst Fast Transient voltage (positive negative) applied through 100pF capacitor, until functional disturbance occurs. This test conforms with 1000-44 standard. device reset allows normal operations resumed.
Symbol VFESD
Parameter Voltage limits applied induce functional disturbance
Conditions VDD=5V, TA=+25°C, fOSC=8MHz conforms 1000-4-2
Unit
-2.5
VFFTB
Fast transient voltage burst limits apVDD=5V, TA=+25°C, fOSC=8MHz plied through 100pF pins conforms 1000-4-4 induce functional disturbance
Notes: Data based characterization results, tested production. suggested decoupling capacitors power supply lines proposed good price performance tradeoff. They have close possible device power supply pins. Other recommendations given other sections (I/Os, RESET, OSCx characteristics).
Figure Recommended Star Network Power Supply Connection
POWER SUPPLY SOURCE DIGITAL NOISE FILTERING (close MCU)
ST62XX
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ST6215C/ST6225C
CHARACTERISTICS (Cont'd) 11.7.2 Absolute Electrical Sensitivity Based three different tests (ESD, DLU) using specific measurement methods, product stressed order determine performance terms electrical sensitivity. more details, refer AN1181 application note. 11.7.2.1 Electro-Static Discharge (ESD) Electro-Static Discharges positive then negative pulses separated second) applied pins each sample according each combination. sample size depends number supply pins device parts*(n+1) supply pin). models usually simulated: Human Body Model Machine Model. This test conforms JESD22-A114A/A115A standard. Figure following test sequences. Human Body Model Test Sequence loaded through pulse generator. Absolute Maximum RatingSymbol VESD(HBM) Ratings Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model)
switches position from generator discharge from through (body resistance) occurs. must closed 100ms after pulse delivery period ensure left charge state. must opened least 10ms prior delivery next pulse. Machine Model Test Sequence loaded through pulse generator. switches position from generator ST6. discharge from occurs. must closed 100ms after pulse delivery period ensure left charge state. must opened least 10ms prior delivery next pulse. (machine resistance), series with ensures slow discharge ST6.
Conditions TA=+25°C TA=+25°C
Maximum value Unit
2000
VESD(MM)
Notes: Data based characterization results, tested production.
Figure Typical Equivalent CircuitS1 R=1500
R=10k~10M
HIGH VOLTAGE PULSE GENERATOR
CL=100pF
HIGH VOLTAGE PULSE GENERATOR CL=200pF
HUMAN BODY MODEL
MACHINE MODEL
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ST6215C/ST6225C
CHARACTERISTICS (Cont'd) 11.7.2.2 Static Dynamic Latch-Up complementary static tests required parts assess latch-up performance. supply overvoltage (applied each power supply pin), current injection (applied each input, output configurable pin) power supply switch sequence performed each sample. This test conforms EIA/ JESD latch-up standard. more details, refer AN1181 application note.
DLU: Electro-Static Discharges (one positive then negative test) applied each samples when micro running assess latch-up performance dynamic mode. Power supplies typical values, oscillator connected near possible pins micro component reset mode. This test conforms IEC1000-4-2 SAEJ1752/3 standards described Figure more details, refer AN1181 application note.
Electrical SensitivitieSymbol Parameter Static latch-up class TA=+25°C TA=+85°C Conditions Class
Dynamic latch-up claVDD=5V, fOSC=4MHz, TA=+25°C
Notes: Class description: Class STMicroelectronics internal specification. limits higher than JEDEC specifications, that means when device belongs Class exceeds JEDEC standard. Class strictly covers JEDEC criteria (international standard). Schaffner NSG435 with pointed test finger.
Figure Simplified Diagram Generator
RCH=50M RD=330
DISCHARGE
CS=150pF GENERATOR
RELAY
DISCHARGE RETURN CONNECTION
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ST6215C/ST6225C
CHARACTERISTICS (Cont'd) 11.7.3 Protection Strategy protect integrated circuit against ElectroStatic Discharge stress must controlled prevent degradation destruction circuit elements. stress generally affects circuit elements which connected pads also affect internal devices when supply pads receive stress. elements protected must receive excessive current, voltage heating within their structure. network combines different input output protections. This network works, allowing safe discharge paths pins subjected stress. critical stress cases presented Figure Figure standard pins.
Standard Protection protect output structure following elements added: diode (3a) diode from (3b) protection device between protect input structure following elements added: resistor series with diode (2a) diode from (2b) protection device between
Figure Positive Stress Standard
(3a)
(2a)
Main path Path avoid
(3b) (2b)
Figure Negative Stress Standard
(3a)
(2a)
Main path
(3b) (2b)
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ST6215C/ST6225C
11.8 PORT CHARACTERISTICS 11.8.1 General Characteristics Subject general operating conditions fOSC, unless otherwise specified.
Symbol Vhys COUT tf(IO)out tr(IO)out tw(IT)in Parameter Input level voltage
Condition
0.7xVDD
0.3xVDD
Unit
Input high level voltage VDD=5V Schmitt trigger voltage hysteresis VDD=3.3V Input leakage current Weak pull-up equivalent resistor input capacitance output capacitance Output high level fall time External interrupt pulse time CL=50pF Output high level rise time Between VSSVINVDD pull-up configured) VIN=VSS VDD=5V VDD=3.3V
tCPU
Figure Typical with
[Khom] Ta=-40°C Ta=25°C Ta=95°C Ta=125°C
Notes: Unless otherwise specified, typical data based TA=25°C VDD=5V. Data based characterization results, tested production. Hysteresis voltage between Schmitt trigger switching levels. Based characterization results, tested. pull-up equivalent resistor based resistive transistor. This data based characterization results, tested production. Data based characterization results, tested production. generate external interrupt, minimum pulse width applied port configured external interrupt source.
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