Agere Systems PayloadPlus10G Network Processor chip provides wire-spee

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Agere Systems PayloadPlus10G Network Processor chip provides wire-spee

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NP10 TM10 Network Processors
Agere Systems PayloadPlus10G Network Processor chip provides wire-speed deeppacket processing high performance packetprocessing systems. This software-compatible, programmable chip consists chips- NP10 classification engine TM10 traffic manager-and follows successful Agere Systems 2.5G PayloadPlus chip set. This chip provides full carrier-class packet processing functionality, including classification, policing, statistics, queueing, scheduling, shaping, buffer management packet/cell modification. three-chip configuration-one NP10 TM10s- provides full duplex Gb/s packet processing functionality. additional NP10 added egress classification required. PayloadPlus solution requires only DRAM small amount SRAM external memory provide high-performance functionality. content addressable memory (CAM) required. chip supports complex packet classification policies, including multifield IPv4/ IPv6 classification, PPPoE, L2TP, MPLS, etc., with large amount headroom future classification needs. OEMs Agere Systems high-level Functional Programming Language (FPL) specify packet classification policies. Statistics, policing, packet modification functions performed on-chip compute engines that programmed using C-like Agere Scripting Language (ASL).
10x2.5GSERDES
NP10
Framer
TM10
Switch Fabric
TM10
32/64 33/66
LINE CARD
Network Processor System Diagram
Host
Product Brief June 2001 Features
NP10 Network Processors
External scheduling port allow OEMs support proprietary switch fabric implementations (for example, credit-based flow control, global scheduling) and/or proprietary packet scheduling implementations.
Full line-rate performance with packet sizes greater than equal bytes long Supports complex multifield packet classification with large amount headroom future classification needs. Supports wire-speed access control list (ACL) processing, even with thousands rules.
Programmable packet modification, including support for: Adding/removing software-defined headers trailers Modifying data anywhere packet Forward congestion marking Wire-speed fragmentation Full multicast support with ability individually schedule modify each packet/cell copy Port based rate shaping media ports Configurations include OC192c, 4xOC48c, 1G/10G Ethernet, 192xDS3, etc. compliant 66-MHz, 32-/64-bit host interface allow easy interfacing variety host microprocessors other support logic Both cell- frame-based fabrics supported with programmable OEMs readily interface wide variety switch fabrics with minimal glue logic effort. Support simple interface third-party fabrics using Agere Systems Field Programmable System-on-a-Chip devices Complete Agere Systems fiber-to-fabric line card reference design with supporting software FPGA-based hardware emulation system software simulator provides complete pre-silicon hardware software development support.
Multiprotocol customer-programmable classification: POS, MPLS, IPv4/v6, ATM, Frame Relay, Ethernet, VLANs, access control lists, link aggregation, etc. OEMs easily supplement protocols standards they support with simple software upgrades. DRAM-based classification rule memory supports over million IPv4 routes with separate information each VPN. CAMs required. Uses high-level network processor programming languages-Functional Programming Language (FPL) Agere Scripting Language (ASL)-preserving investments classification, policing, statistics, packet modification programming. provides order magnitude reduction (compared C/C++) number lines code required specify packet classification policies. eliminates need complex handoptimization assembly microcode achieve wirespeed performance. Programmable per-flow statistics policing allows OEMs implement highly differentiated admission control billing policies. Full carrier-class traffic management functionality help maximize amount premium traffic that reliably served, with support for: Hierarchical weighted fair queuing (WFQ) with bandwidth delay guarantees VPNs with traffic isolation service-level agreements (SLAs) Dynamic bandwidth QoS/CoS modification enable real-time dynamic service provisioning million packet handling behavior types with buffer management profiles behavior type allow finegrained service differentiation Random early detection (RED) weighted (WRED) external packet buffer memory direction
Applications
Target applications include multiprotocol core edge switches routers, multiservice optical core edge devices service-aware switches provisioning platforms.
NP10 Network Processors
additional information, contact your Agere Systems Account Manager following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com AMERICA: Agere Systems, Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA PACIFIC: Agere Systems, Inc., Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 CHINA: Agere Systems, Inc. (China) Co., Ltd., A-F2, 23/F, Fong Universe Building, 1800 Zhong Shan Road, Shanghai 200233 China Tel. (86) 6440 0468, ext. 316, (86) 6440 0652 JAPAN: Agere Systems, Inc. Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 EUROPE: Data Requests: Agere Systems, Inc. DATALINE: Tel. (44) 7000 368, (44) 1189 Technical Inquiries: GERMANY: (49) 95086 (Munich), UNITED KINGDOM: (44) 1344 (Ascot), FRANCE: (33) (Paris), SWEDEN: (46) (Stockholm), FINLAND: (358) 4354 2800 (Helsinki), ITALY: (39) 6608131 (Milan), SPAIN: (34) 1441 (Madrid)
Agere Systems, Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. PayloadPlus trademark Agere Systems, Inc.
Copyright 2001 Agere Systems, Inc. Rights Reserved Printed U.S.A.
6/1/01 PB01-137NP
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Agere Systems PayloadPlus10G Network Processor chip provides wire-spee

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