Description device consists four independent channels codec digit

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Description device consists four independent channels codec digit

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T8538B Quad Programmable Codec
Description
device consists four independent channels codec digital signal processing functions chip. addition classic A-to-D D-to-A conversion, each channel provides termination impedance synthesis hybrid balance network. device controlled serial microprocessor interface, series bidirectional leads provided that this control mechanism utilized operate battery feed device, ringing voltage switches, etc. Common data clock paths shared over number devices. filter coefficients, signal processing, SLIC, test features accessible through this interface. This serial interface operated speeds Mbits/s. choice also programmable, with channel capable being assigned time slot. operated speeds 16.384 Mbits/s, allowing maximum time slots. Separate transmit receive interfaces available 4-wire designs, they strapped together 2-wire bus. device available packages. T8538B 64-pin TQFP features five data latches channel 100-pin TQFP features data latches channel. Both devices pin-compatible with T8536B Quad Programmable Codecs.
operation Per-channel programmable gains, equalization, termination impedance, hybrid balance Programmable µ-law, linear, A-law modes time slots frame Supports data rates kbits/s 16.384 Mbits/s Double-clock mode timing compatible with ISDN standard interfaces Fully programmable time-slot assignment with offset Analog digital loopback test modes Serial microprocessor interface Normal byte-by-byte control modes Fast scan mode bidirectional control leads channel, SLIC line card function control Differential analog output Mates directly SLICs, eliminating external components Sigma-delta converters with dither noise reduction Quad design minimize package count dense line card applications Meets exceeds ITU-T G.711-G.712 relevant Telcordia Technologies* requirements
Telcordia Technologies trademark Telcordia Technologies, Inc.
T8538B Quad Programmable Codec
General Description
Refer Figure following discussion.
ANALOG GAIN CONVERTER DIGITAL LOOPBACK ANALOG LOOPBACK DIGITAL LOOPBACK ANALOG LOOPBACK DIGITAL LOOPBACK DIGITAL GAIN (GAIN TRANSFER) CHANNEL COMMON TSX0 TSX1 TO/FROM POWER GROUND
VFXIn
TO/FROM SLIC
TERMINATION IMPEDANCE
HYBRID BALANCE NETWORK
µ-LAW A-LAW CONVERSION
INTERFACE
VFROPn VFRONn CONVERTER ANALOG BUFFER DIGITAL GAIN (GAIN TRANSFER) CONTROL DATA SIGNALS
BCLK
SLIC CONTROL LATCHES CHANNEL
MICROPROCESSOR CONTROL
FREQUENCY SYNTHESIZER
COMMON
SERIAL CONTROL INTERFACE
5-8125CF
Figure Functional Block Diagram, Each Section
This device performs virtually signal processing functions associated with central office line termination. Functionality includes line termination impedance synthesis, fixed hybrid balance impedance synthesis, level conversion both analog sense accommodate various subscriber line interface circuits (SLICs) digital sense adjustment levels bus. general, termination impedance synthesis generates equivalent circuit with parallel combination capacitor resistor series with resistor parallel combination resistor series combination resistor capacitor. These general forms impedance characteristic will satisfy most requirements
specified throughout world. Programmable selection either µ-law A-law encoding further aids worldwide deployment. coefficients used filtering algorithms computed off-line advance downloaded device time powerup. signal processing contained within device, there only three interfaces consequence system designer: SLIC interface, interface, control interface. SLIC interface designed flexible convenient with variety SLIC circuits. With appropriate choice SLIC, external components required interface.
Agere Systems Inc.
T8538B Quad Programmable Codec
microprocessor control interface serial interface that uses classical chip select type operation. interface controls device writing reading various internal addresses. command consists simple read write operations, with address determining effect. memory locations, including per-chip functions, organized channel. There several test modes included facilitate confirmation correct operation. signal path, analog three digital loopback tests available, while microprocessor interface, there write/ read test mode that tests operation memory. external test access switches allows complete test signal path through line card that correct operation various operational modes verified.
General Description (continued)
interface flexible that allows, independently, transmit receive data channel placed time slot. operated maximum 16.384 Mbits/s rate accommodate maximum time slots. Separate pins provided each direction transmission allow 4-wire operation. frame strobe signal signal that defines beginning frame structure four channels. interface will count bits time slot insert read data each channel programmed. Lower speeds allowed. clock must synchronous with frame strobe signal.
Agere Systems Inc.
T8538B Quad Programmable Codec
Applications
following reference circuit shows complete schematic interfacing Agere L9215G SLIC. parameters programmed T8538B. Note that this implementation differentiates itself that external components required interface provide termination impedance stability. illustration purposes, Vrms injection assumed this example meter pulse rejection used. Also, this example illustrates device using programmable overhead current limit.
VBAT1 CBAT1 DBAT1 FUSIBLE VBAT1 AGERE L7591 FUSIBLE RCVP FROM PROGRAMMABLE VOLTAGE SOURCE RCVN VPROG
rate battery reversal ramped
VBAT2 CBAT2 AGND TRGDET
ground used
VBAT1 RTFLT
BGND
VBAT2
4640 VITR VFXI VFROP VFRON T8538B SYNC CLOCK HIGHWAY
DCOUT
L9215G
VREF 0.47
NSTAT RPD1
RINGIN
PPMIN CPPM
SLIC4a SLIC3a SLIC2a SLIC1a SLIC0a
BCLK
CRING 0.47
DGND
FROM/TO CONTROL
NSTAT Vrms
12-3534.R
Figure POTS Interface
additional information, contact your Agere Systems Account Manager following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com AMERICA: Agere Systems Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18109-3286 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Tower, Century Boulevard Pudong, Shanghai 200121 Tel. (86) 50471212, (86) 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 368, (44) 1189 Technical Inquiries: GERMANY: (49) 95086 (Munich), UNITED KINGDOM: (44) 1344 (Ascot), FRANCE: (33) (Paris), SWEDEN: (46) (Stockholm), FINLAND: (358) 3507670 (Helsinki), ITALY: (39) 6608131 (Milan), SPAIN: (34) 1441 (Madrid)
Agere Systems Inc. reserves right make changes product(s) information contained herein without notice. liab ility assumed result their application.
Copyright 2001 Agere Systems Inc. Rights Reserved
2001 PB01-108ALC

Description device consists four independent channels codec digit

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