ADN2809's proprietary delay phase-locked loop architecture ensures tha

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ADN2809-Multirate Limiting Amplifier Clock Data Recovery
ADN2809's proprietary delay phase-locked loop architecture ensures that every SONET/SDH jitter requirement exceeded over operating conditions. bandwidth jitter transfer simultaneous with high bandwidth jitter tolerance minimal jitter peaking-an ideal scenario regenerator applications. ADN2809 user-friendly flexible. Both native Forward Error Correction (FEC) digital `wrappers' supported rates, without change reference clock. Either internal external reference clock four frequencies) used, multiplexor incorporated allow bypass CDR. these features accelerate time market while minimizing costs improving manufacturability. Analog over years experience designing fiber optic components; expertise work you. FEATURES
ADN2809's proprietary delay phase-locked loop design provides unprecedented jitter performance robust high-speed networking designs.
Multirate (155/166 Mbps, 622/666 Mbps, 1.25/1.34 Gbps, 2.49/2.67 Gbps) Integrated limiting amplifier with adjustable slice -Quantizer sensitivity; -Adjustable slice level: Exceeds SONET/SDH requirements jitter
Integrated limiting amplifier with adjustable slice level facilitates design high-performance fiber optic receivers. demand bandwidth grows, Analog Devices continues provide innovative solutions fiber optic interface ICs, which translates into compelling competitive advantages customers. prime example Analog's system knowledge design expertise working together ADN2809. This highly integrated, low-power multirate device provides Adjustable Slice Level Quantization Clock Data Recovery functions. Diagnostic capabilities include Signal Detector with user-adjustable threshold optical hysteresis prevent chatter, Loss-of-Lock Detector, Loopback mode.
transfer, generation, tolerance Internal bypass power: typical supply: Single reference clock frequency rates Loss-of-Lock indicator Small footprint: 48-Lead LFCSP package overall)
ADN2809-Multirate Limiting Amplifier Clock Data Recovery
APPLICATIONS SONET OC-3/12/48, STM-1/4/16, Gigabit Ethernet associated rates transponders SONET/SDH regenerators SONET/SDH test equipment Backplane applications
Jitter Transfer Rate OC48 SONET Spec ADN2809
Jitter Tolerance SONET Margin Spec ADN2809 Margin 2.56 11.7 46.5
OC12
TYPICAL JITTER TRANSFER TOLERANCE-3 BETTER THAN SONET/SDH SPECIFICATIONS OVER TEMPERATURE
JITTER TRANSFER 1.E+00 JITTER TOLERANCE PEAK-TO-PEAK SPECIFICATION TEST EQUIPMENT LIMITATION
JITTER GENERATION PEAK-TO-PEAK
TYPICAL OC48 JITTER GENERATION EXCEEDS SONET/SDH SPECIFICATIONS
0.120000 0.100000 0.080000 0.060000 0.040000 0.020000 0.000000
1.E+02 1.E+04 1.E+06 JITTER FREQUENCY
1.E+08
JITTER GIVEN TEMPERATURE
SPEC
PRBS23 PATTERN
1.E+01
1.E+03 1.E+05 JITTER FREQUENCY
1.E+07
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacture, unless otherwise agreed writing. responsibility assumed Analog Devices use; infringement patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices.
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