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IBM041841QLAD IBM043641QLAD 128K 256K SRAM Registered Outputs Com


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128K 256K Organizations CMOS Technology Synchronous Pipeline Mode Operation with Self-Timed Late Write Single Differential HSTL Clock +3.3V Power Supply, Ground, VDDQ VREF HSTL Input Output levels, Registered Addresses, Write Enables, Synchronous Select Data
IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Registered Outputs Common Asynchronous Output Enable Power Down Inputs Boundary Scan using limited JTAG 1149.1 functions Byte Write Capability Global Write Enable Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout Boundary SCAN Order
Description
IBM041841QLAD IBM043641QLAD SRAMS Synchronous Pipeline Mode, high performance CMOS Static Random Access Memories that versatile, wide I/O, achieve 4.0ns cycle times. Dual differential clocks used initiate read/write operation, internal operations self-timed. rising edge Clock, Addresses, Write-Enables, Sync Select, Data registered internally. Data Outs updated from output registers next rising edge clock. internal Write buffer allows write data follow cycle after addresses controls. These chips operate with +3.3V power supply, have 1.5V output power supply, compatible with HSTL interfaces
75H4339 Revised 2/99
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Bump Layout (Top View)
DQc18 DQc20 VDDQ DQc23 DQc25 VDDQ DQd34 DQd32 VDDQ DQd29 DQd27 VDDQ DQc19 DQc21 DQc22 DQc24 DQc26 DQd35 DQd33 DQd31 DQd30 DQd28 SBWc VREF SBWd SA16 SA11 SA10 SBWb VREF SBWa SA13 SA14 SA15 DQb10 DQb12 DQb13 DQb15 DQb17 DQa8 DQa6 DQa4 DQa3 DQa1 SA12 VDDQ DQb9 DQb11 VDDQ DQb14 DQb16 VDDQ DQa7 DQa5 VDDQ DQa2 DQa0 VDDQ
Note: clock mode pins. this application, need connect VDD, respectively
Bump Layout (Top View)
VDDQ DQb9 VDDQ DQb16 VDDQ DQb14 VDDQ DQb11 VDDQ DQb12 DQb15 DQb17 DQb13 DQb10 SBWb VREF SA16 SA11 SA10 VREF SBWa SA17 SA14 SA15 DQa1 DQa4 DQa8 DQa6 DQa3 SA13 SA12 VDDQ DQa2 VDDQ DQa5 VDDQ DQa7 VDDQ DQa0 VDDQ
Note: clock mode pins. this application, need connect respectively
©IBM Corporation. rights reserved. further subject provisions this document
75H4339 Revised 2/99
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Description
SA0-SA17 DQ0-DQ35 SBWa SBWb SBWc SBWd TMS,TDI,TCK Address Input Data Differential Input Register Clocks Write Enable, Global Write Enable, Byte (DQ0-DQ8) Write Enable, Byte (DQ9-DQ17) Write Enable, Byte (DQ18-DQ26) Write Enable, Byte (DQ27-DQ35) IEEE 1149.1 Test Inputs (LVTTL levels) IEEE 1149.1 Test Output (LVTTL level) VREF(2) VDDQ Asynchronous Output Enable Synchronous Select Clock Mode Inputs Selects Single Dual Clock Operation. HSTL Input Reference Voltage Power Supply (+3.3V) Ground Output Power Supply Asynchronous Sleep Mode Output Driver Impedance Control Connect
Block Diagram
SA0-SA17
Register Register Register Latch Register
Decoder
128Kx36 256K Array Column Decoder Read/Write
Latch
Register
Register
Match Write Buffer Data Register
Register
Register
DQ0-DQ35
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
SRAM Late Write Late Write function allows write data registered cycle after addresses controls. This feature will alleviate SRAM data contention going from Read Write cycle eliminating dead cycle. Late Write accomplished buffering write addresses data that write operation occurs during next write cycle. case read cycle occurs after write cycle, address write data information stored temporarily holding registers. During first write cycle preceded read cycle, SRAM array will updated with address data from holding registers. Read cycle addresses monitored determine read data supplied from SRAM array write buffer. bypassing SRAM array occurs byte byte basis. When only byte written during write cycle, read data from last written address will have byte data from write buffer remaining bytes from SRAM array. Mode Control Mode control pins: used select four different JEDEC standard read protocols. This SRAM supports Single Clock, Pipeline VSS, VDD). This data sheet only describes Single Clock Pipeline functionality. Mode control inputs must with power must change during SRAM operation.This Sram tested only Pipeline mode. Power Down Mode Power Down Mode "Sleep" Mode enabled switching asynchronous signal High When powering SRAM down inputs should dropped first followed VREF then VDDQ; must dropped last. VDDQ simultaneously dropped with VDD. Programmable Impedance Power Requirements external resistor, must connected between SRAM allow SRAM adjust output driver impedance. value must value intended line impedance driven SRAM. allowable range guarantee impedance matching with tolerance between 350. Periodic readjustment output driver impedance necessary impedance greatly affected drifts supply voltage temperature. evaluation occurs every clock cycles each evaluation move output driver impedance level only step time towards optimum level. output driver discrete binary weighted steps. impedance update output driver occurs when SRAM High-Z. Write Deselect operations will synchronously switch SRAM into High-Z, therefore, triggering update. user choose invoke asynchronous updates providing setup hold about Clock guarantee proper update. Power requirements SRAM that must powered before simultaneously with VDDQ followed VREF; inputs should powered last. limitation VDDQ that must exceed more than 0.4V during power order guarantee optimum internally regulated supply voltage, SRAM requires power-up time after reaches operating range.To guarantee optimum output driver impedance after power SRAM needs 2080 clock cycles followed single Low-Z High-Z transition 2080 cycles. Sleep Mode Operation Sleep mode power mode initiated bringing asynchronous HIGH. During sleep mode, other inputs ignored outputs brought High-Z state. Sleep mode current output High guaranteed after specified sleep mode enable time. During sleep mode, array data contents pre©IBM Corporation. rights reserved. further subject provisions this document
75H4339 Revised 2/99
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
served. Sleep mode must initiated until after pending operations have completed, pending operation guaranteed properly complete after sleep mode initiated. Sense data lost. Normal operation resumed bringing low, only after specified sleep mode recovery time
Ordering Information
Part Number IBM041841QLAD-4 (Rev IBM041841QLAD-5 (Rev IBM041841QLAD-6 (Rev IBM041841QLAD-7 (Rev IBM043641QLAD-4 (Rev IBM043641QLAD-4N (Rev IBM043641QLAD-5 (Rev IBM043641QLAD-6 (Rev IBM043641QLAD-7 (Rev Organization 256K 256K 256K 256K 128K 128K 128K 128K 128K Speed 2.1ns Access Cycle 2.5ns Access Cycle 3.0ns Access Cycle 3.5ns Access Cycle 2.1ns Access Cycle 2.25ns Access Cycle 2.5ns Access Cycle 3.0ns Access Cycle 3.5ns Access Cycle Leads PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA PBGA
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Clock Truth Table
SBWa SBWb SBWc SBWd High-Z (n+1) DOUT 0-35 9-17 18-26 27-35 0-35 High-Z High-Z High-Z MODE Read Cycle Bytes Write Cycle Byte Write Cycle Byte Write Cycle Byte Write Cycle Byte Write Cycle Bytes Abort Write Cycle Deselect Cycle Sleep Mode
Output Enable Truth Table
Operation Read Read Sleep (ZZ=H) Write (SW=L) Deselect (SS=H) DOUT 0-35 High-Z High-Z High-Z High-Z
Absolute Maximum Ratings
Item Power Supply Voltage Input Voltage Output Voltage Output Power Supply Voltage Operating Temperature Storage Temperature Short Circuit Output Current Symbol VOUT VDDQ TSTG IOUT Rating -0.5 -0.5 VDD+0.5 -0.5 VDD+0.5 +110 +125 Units Notes
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability
©IBM Corporation. rights reserved. further subject provisions this document
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Recommended Operating Conditions (TA=0 85°C)
Parameter Supply Voltage Output Driver Supply Voltage Input High Voltage Input Voltage Input Reference Voltage Clocks Signal Voltage Differential Clocks Signal Voltage Clocks Common Mode Voltage Output Current Symbol VDDQ VREF VDIF IOUT Min. 3.135 VREF +0.1 -0.3 0.68 -0.3 0.55 Typ. 0.75 Max. 3.63 VDDQ VREF -0.1 0.90 VDDQ VDDQ 0.90 Units Notes
voltages referenced VSS. VDD, VDDQ pins must connected. VIH(Max)DC VDDQ VIH(Max)AC (pulse width 4.0ns). VIL(Min)DC VIL(Min)AC= -1.5 (pulse width 4.0ns). VIN-CLK specifies maximum allowable excursions each differential clock VDIF-CLK specifies minimum Clock differential voltage required switching. Peak Peak component superimposed VREF exceed VREF
Electrical Characteristics (TA= +85°C, VDD=3.3V -5%/+10%, VDDQ 1.5V)
Parameter Symbol IDD4 IDD4.3 IDD5 IDD6 IDD7 IDD4 IDD5 IDD6 IDD7 ISBZZ ISBSS VDDQ VDDQ VSS+.4 Min. Max. Units Notes
Average Power Supply Operating Current- (IOUT VIL, VIL)
Average Power Supply Operating Current (IOUT VIL, VIL) Power Supply Standby Current (ZZ= VIH, other inputs VIL, IOUT (SS=VIH, ZZ=VIL. their inputs VIL, IOUT= Input Leakage Current, input (VIN VDD) Output Leakage Current (VOUT VDD, High-Z Output "High" Level Voltage (IOH=-6mA VDDQ 0.3) Output "Low" Level Voltage (IOL=+6mA VDDQ 0.3)
IOUT Chip Output Current. IDD4 means current cycle time example. Minimum Impedance Output Driver
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
PBGA Thermal Characteristics
Item Thermal Resistance Junction Case Symbol Rating Units °C/W
PBGA Capacitance
Input Capacitance
(TA=0 85°C, VDD=3.3V -5%/+10%, f=1MHz)
Symbol COUT Test Condition VOUT Units
Parameter
Data Capacitance (DQ0-DQ35)
Input Characteristics
Item Input Logic High (Volts) Input Logic (Volts) Clock Input Differential Voltage (Volts) VREF Peak Peak Voltage (Volts) Symbol (ac) (ac) VDIF (ac) VREF (ac) VREF (dc) VREF+0.4 VREF-0.4 Notes
peak peak component superimposed VREF exceed component VREF. Implies very stable signal. Sourcing from VDDQ recommended. Separate board plane recommended. noisy signal line. Performance function levels clock inputs. Input Definition page
Input Definition
(ac) VREF (ac)
©IBM Corporation. rights reserved. further subject provisions this document
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Programmable Impedance Output Driver Electrical Characteristics (TA= +85°C,
VDD=3.3V -5%/+10%)
Parameter Output "High" Level Voltage Output "Low" Level Voltage Symbol Min. VDDQ Max. VDDQ VDDQ Units Notes
(VDDQ VDDQ For: 350. (VDDQ VDDQ For: 350.
Test Conditions (TA=0 +85°C, VDD=3.3V 5%/+10%, VDDQ =1.5V)
Parameter Input High Level Input Level Input Reference Voltage Differential Clocks Voltage Clocks Common Mode Voltage Input Rise Time Input Fall Time Signals Reference Level (except Clocks) Clocks Reference Level Output Load Conditions Test Loading figure page Symbol VREF VDIF-CLK VCM-CLK Conditions 1.25 0.25 0.75 0.75 0.75 0.75 Differential Cross Point Units Notes
Test Loading
16.7 16.7 16.7 0.75V 0.75V
0.75V
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Characteristics (TA=0 85°C, VDD=3.3V -5%/+10%, VDDQ=1.5V)
Parameter Cycle Time Clock High Pulse Width Clock Pulse Width Clock Output Valid Address Setup Time Address Hold Time Sync Select Setup Time Sync Select Hold Time Write Enables Setup Time Write Enables Hold Time Data Setup Time Data Hold Time Data Hold Time Clock High Output High-Z Clock High Output Active Output Enable High-Z Output Enable Low-Z Symbol tKHKH tKHKL tKLKH tKHQV tAVKH tKHAX tSVKH tKHSX tWVKH tKHWX tDVKH tKHDX tKHQX tKHQZ tKHQX4 tGHQZ tGLQX Min. 0.75 0.75 Max. (X36 Only) Min. 0.75 0.75 Max. 2.25 Min. Max. Min. Max. Min. Units Notes Max.
Output Enable Output Valid tGLQV Output Enable Set-up Time Output Enable Hold TIme Sleep Mode Recovery TIme Sleep Mode Enable TIme tGHKH tKHGX tZZR tZZE
Test Loading figure page Verified design tested without guardband Output Driver Impedance update specifications induced updates. Write Deselect cycles will also induce Output Driver updates during High-Z. conditions VIH,VIL,Trise, Tfall inputs must within VIH, VIL, Trise, Tfall Clock. Verified design 0.6ns. Strobed 0.6ns sort, others. sort, this spec verified design 0.4ns. Strobed 0.3ns
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75H4339 Revised 2/99
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Timing Diagram (Read Deselect Cycles)
tKLKH tKHKL tKHKH
tAVKH
tKHAX tKHSX
tWVKH
tSVKH
tGLQV tKHWX tKHQZ
tGHQZ
tKHQX
tGLQX
tKHQV
tKHQX4
tKHQV
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Timing Diagram (Read Write Cycles)
tKLKH tKHKL tAVKH tKHAX tKHKH
tSVKH tKHSX tWVKH
tKHWX
tKHWX
tWVKH tKHWX tKHWX
tWVKH tWVKH
tKHQZ tKHDX tKHQV tDVKH tKHQV
tGHQZ
tKHQX4
tDVKH tKHDX
NOTES: input data written memory location output data read from write buffer, result address being match from last write cycle address
©IBM Corporation. rights reserved. further subject provisions this document
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Timing Diagram (Sleep Mode)
tKHKH
tZZE tZZR
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
IEEE 1149.1 Boundary Scan
SRAM provides limited JTAG functions intended test interconnection between SRAM printed circuit board traces other components. There multiplexer path from pins core. conformance with IEEE std. 1149.1, SRAM contains controller, Instruction register, Boundary Scan register, Bypass register register. controller standard 16-state machine that resets internally upon power-up, therefore, TRST signal required. Signal List TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data Test Data Caution: TCK,TMS,TDI must tied down, even JTAG used. tied will allow data clocked however. JTAG Recommended Operating Conditions (TA=0 85°C)
Parameter JTAG Input High Voltage JTAG Input Voltage JTAG Output High Level JTAG Output Level Symbol VIH1 VIL1 Min. -0.3 Typ. Max. VDD+0.3 Units Notes
VOH1
VOL1
JTAG Inputs/Outputs LVTTL Compatible only. IOH1 -8mA 2.4V. IOL1 +8mA 0.4V
JTAG Test Conditions (TA=0 +85°C, VDD=3.3V ±5%)
Parameter Input Pulse High Level Input Pulse Level Input Rise Time Input Fall Time Input Output Timing Reference Level Test Loading page Symbol VIH1 VIL1 Conditions Units Notes
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75H4339 Revised 2/99
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
JTAG Characteristics (TA=0 +85°C, VDD=3.3V -5%/+10%)
Parameter Cycle Time High Pulse Width Pulse Width Setup Hold Setup Hold Valid Data Test Loading page Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tTLOV Min. Max. Units Notes
JTAG Timing Diagram
tTLTH tTHTH
tTHTL
tTHMX
tTHDX tDVTH tMVTH
tTLOV
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Scan Register Definition
Register Name Instruction Bypass Boundary Scan Boundary Scan chain consists following bits: bits Data Inputs Depending Configuration bits SA16 x36, bits SA17 bits SBWa SBWd x36, bits SBWa SBWb bits bits Place Holders clocks connect differential receiver that generates single-ended clock signal. This signal inverted value used Boundary Scan sampling. Size Size
Register Definition
Field Number Description Part 256K 128K Revision Number (31:28) 0001 0001 Device Density Configuration (27:18) 1011 1100 Vendor Definition (17:12) 001000 001000 Manufacture JEDEC Code (11:1) Start Bit(0)
Instruction
Code Instruction SAMPLE-Z IDCODE SAMPLE-Z PRIVATE SAMPLE PRIVATE PRIVATE BYPASS Notes
Places High-Z order sample input data regardless other SRAM inputs. sampled input first register allow serial shift external data. BYPASS register initiated when BYPASS instruction invoked. BYPASS register also holds last serially loaded when exiting Shift state. SAMPLE instruction does place High-Z. SRAM must Sleep mode when SAMPLE-Z SAMPLE instructions invoked
List IEEE 1149.1 standard violations:
7.2.1.b, 7.7.1.a-f 10.1.1.b, 10.7.1.a-d 6.1.1.d
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Boundary Scan Order (x36) =Place Holder)
Exit Order Signal SA12 SA13 SBWa SBWb DQ16 DQ17 DQ14 DQ15 Bump Exit Order Signal DQ13 DQ11 DQ12 DQ10 SA14 SA15 SA10 SA16 SA11 DQ19 DQ18 DQ21 DQ20 DQ22 DQ24 DQ23 Bump Exit Order Signal DQ26 DQ25 SBWc C=02 C=12 SBWd DQ34 DQ35 DQ32 DQ33 DQ31 DQ29 DQ30 DQ27 DQ28 Bump
Input register connected VSS. Balls unused Clock pins this application
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Boundary Scan Order
=Place Holder)
Exit Order Signal SA12 SA13 SA17 SBWa SA14 SA15 SA10 SA16 SA11 Bump Exit Order Signal DQ12 DQ15 DQ16 SBWb C=02 C=12 DQ17 DQ14 DQ13 DQ11 DQ10 Bump
Input register connected Balls unused Clock pins this application
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75H4339 Revised 2/99
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Controller State Machine
Test Logic Reset
Test Idle
Select
Select
Capture
Capture
Shift
Shift
Exit1
Exit1
Pause
Pause
Exit2
Update
Exit2
Update
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
PBGA Dimensions
20.32 0.84 (119X) 0.89 0.04 Solder Ball 0.035" 0.0015(mils) 7.62
3.19
1.27
22.00 16.764
Under fill 12.7 14.00
Indicates Location PLATE CHIP
Structural Adhesive
0.1778
0.625±.254
Under fill PLATE
2.549 0.13
0.701 0.099 0.71 0.05
Note: dimensions Millimeters Unless Otherwise noted
©IBM Corporation. rights reserved. further subject provisions this document
75H4339 Revised 2/99
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
References Last Character Part Number
following documents give recommendations, restrictions limitations level attach process: SRAM Assembly Guide Single Sided Assembly Double Sided 4Meg Coupled PBGA Card Assembly Guide There qualification information, including scope application conditions qualified, available from your marketing representative
75H4339 Revised 2/99
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IBM041841QLAD IBM043641QLAD 128K 256K SRAM
Revision
9/95 11/95 2/96 5/13/96 7/16/96 11/24/96 1/97 8/20/97 9/17/97 9/97 12/97 5/98 6/98 2/99 Contents Modification Initial Release 128K 256K (5/6/7 cycle), BGA, HSTL, PIPE LINE Application Spec. Update scan chain. Update part numbers, updated package drawing. Update part number. thermal resistance, update timings currents. Cleanup Updated package drawing. Updated JTAG definitions. Power Up/Down requirements. Tkhqx4 updated. Updated Power up/down definitions. Updated part number added +10% power supply. Updated Tkhqz part number. Updated capacitance part. Added ceramic part Updated Tri-state measurement point (Test change). Added sorts Updated input data. Changed Pimp tolerance ±15% 2080 cycle update. Changed Added references changed package diagram. Added Sleep mode statement. Removed Ceramic parts. Minor update Boundary Scan. Tightened ball diameter tolerance
©IBM Corporation. rights reserved. further subject provisions this document
75H4339 Revised 2/99
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International Business Machines Corp.1999
Copyright
Printed United States America rights reserved
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This document contain preliminary information subject change without notice. assumes responsibility liability information contained herein. Nothing this document shall operate express implied license indemnity under intellectual property rights third parties. products described this document intended implantation other direct life support applications where malfunction result direct physical harm injury persons. WARRANTIES KIND, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, OFFERED THIS DOCUMENT
more information contact your Microelectronics sales representative visit World Wide http://www.chips.ibm.com
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