IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM Registered Addresses,
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Registered Addresses, Write Enables, Synchronous Select Data Latched Outputs Asynchronous Output Enable Power Down Inputs Boundary Scan using limited JTAG 1149.1 functions Byte Write Capability Global Write Enable
Synchronous Register-Latch Mode Operation with Self-Timed Late Write Single Differential PECL Clock compatible with LVTTL Levels +3.3V Power Supply, VDDQ Ground
Common LVTTL Compatible Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout Boundary SCAN Order
Description
IBM04184ARLAD IBM04364ARLAD SRAMS Synchronous Register-Latch Mode, high performance CMOS Static Random Access Memories that versatile, wide I/O, achieve cycle 5.5ns access times. Dual differential clocks used initiate read/write operation internal operations self-timed. rising edge Clock, Addresses, WriteEnables, Sync Select, Data registered internally. Data Outs updated from output latches falling edge Clock. internal Write buffer allows write data follow cycle after addresses controls. chip operated with +3.3V power supply, 2.5V 3.3V Output Power Supply, compatible with LVTTL interfaces
75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Bump Layout (Top View)
VDDQ DQc18 DQc20 VDDQ DQc23 DQc25 VDDQ DQd34 DQd32 VDDQ DQd29 DQd27 VDDQ DQc19 DQc21 DQc22 DQc24 DQc26 DQd35 DQd33 DQd31 DQd30 DQd28 SBWc SBWd SA16 SA11 SA10 SBWb SBWa SA13 SA14 SA15 DQb10 DQb12 DQb13 DQb15 DQb17 DQa8 DQa6 DQa4 DQa3 DQa1 SA12 VDDQ DQb9 DQb11 VDDQ DQb14 DQb16 VDDQ DQa7 DQa5 VDDQ DQa2 DQa0 VDDQ
Note: clock mode pins. this application, need connect VSS, respectively
Bump Layout (Top View)
VDDQ DQb9 VDDQ DQb16 VDDQ DQb14 VDDQ DQb11 VDDQ DQb12 DQb15 DQb17 DQb13 DQb10 SBWb SA16 SA11 SA10 SBWa SA17 SA14 SA15 DQa1 DQa4 DQa8 DQa6 DQa3 SA13 SA12 VDDQ DQa2 VDDQ DQa5 VDDQ DQa7 VDDQ DQa0 VDDQ
Note: clock mode pins. this application, need connect VSS, respectively
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75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Description
SA0-SA17 DQ0-DQ35 SBWa SBWb SBWc SBWd TMS,TDI,TCK Address Input Data Differential PECL CLocks (LVTTL Compatible) Write Enable, global Write Enable, Byte (DQ0 DQ8) Write Enable, Byte (DQ9 DQ17) Write Enable, Byte (DQ18 DQ26) Write Enable, Byte (DQ27 DQ35) IEEE 1149 Test Inputs VDDQ IEEE 1149 Test Output Synchronous Select Mode Inputs- Selects Read Protocol Operation. Power Supply (+3.3V) Ground Output Power Supply Asynchronous Output Enable Asynchronous Sleep Mode Connect
Block Diagram
SA0-SA17
Register Register Register Latch Register
Decode
128Kx36 256K Array Column Decode Read/Write
Latch
Register
Register
Match Write Buffer Data Latch
Register
Register
DQ0-DQ35
75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
SRAM Late Write Late Write function allows write data registered cycle after addresses controls. This feature eliminates bus-turnaround cycle necessary when going from Read Write operation. Late Write accomplished buffering write addresses data that write operation occurs during next write cycle. case read cycle occurs after write cycle, address write data information stored temporarily holding registers. During first write cycle preceded read cycle, SRAM array will updated with address data from holding registers. Read cycle addresses monitored determine read data supplied from SRAM array write buffer. bypassing SRAM array data occurs byte byte basis. When byte written during write cycle, read data from last written address will have byte data from write buffer remaining bytes from SRAM array. Mode Control Mode control pins: used select four different JEDEC standard read protocols. This SRAM supports Register-Latch VDD, VSS) protocols. Mode control inputs must with power-up must change during SRAM operation. Power Down Mode Power Down Mode, "Sleep Mode" accomplished switching asynchronous signal high. When SRAM Sleep Mode, outputs will High-Z state SRAM will draw standby current. SRAM data will preserved recovery time (tZZR) required before SRAM resumes normal operation. When powering SRAM down inputs must dropped first VDDQ must dropped before simultaneously with VDD. Power-Up Requirements order guarantee optimum internally regulated supply voltage, SRAM requires power-up time after reaches operating range. Power requirements SRAM that must powered before simultaneously with VDDQ, then inputs after VDDQ. VDDQ limitation that VDDQ should exceed supply more than 0.4V during power Sleep Mode Operation Sleep mode power mode initiated bringing asynchronous HIGH. During sleep mode, other inputs ignored outputs brought High-Z state. Sleep mode current output High guaranteed after specified sleep mode enable time. During sleep mode, array data contents preserved. Sleep mode must initiated until after pending operations have completed, pending operation guaranteed properly complete after sleep mode initiated. Sense data lost. Normal operation resumed bringing low, only after specified sleep mode recovery time
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75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Ordering Information
Part Number IBM04364ARLAD-5N (Rev IBM04184ARLAD-6P (Rev IBM04184ARLAD-6F (Rev IBM04184ARLAD-6N (Rev IBM04364ARLAD-5N (Rev IBM04364ARLAD-6P (Rev IBM04364ARLAD-6F (Rev IBM04364ARLAD-6N (Rev Organization 256K 256K 256K 256K 128K 128K 128K 128K Speed 5.5ns Access Cycle 6.0ns Access Cycle 6.5ns Access Cycle 7.0ns Access Cycle 5.5ns Access Cycle 6.0ns Access Cycle 6.5ns Access Cycle 7.0ns Access Cycle Leads
75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Clock Truth Table
SBWa SBWb SBWc SBWd DOUT 0-35 High-Z High-Z High-Z (n+1) 9-17 18-26 27-35 0-35 High-Z MODE Read Cycle Bytes Write Cycle Byte Write Cycle Byte Write Cycle Byte Write Cycle Byte Write Cycle Bytes Abort Write Cycle Deselect Cycle Sleep Mode
Output Enable Truth Table
Operation Read Read Sleep (ZZ=H) Write (SW=L) Deselect (SS=H) DOUT 0-35 High-Z High-Z High-Z High-Z
Absolute Maximum Ratings
Item Power Supply Voltage Output Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Symbol VDDQ VOUT TSTG Rating -0.5 Units Notes
-0.5 VDD+0.5 -0.5 VDD+0.5
+110 +125
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability
PBGA Thermal Characteristics
Item Thermal Resistance Junction Case Symbol Rating Units °C/W
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Recommended Operating Conditions (TA=0 85°C)
Parameter Supply Voltage Output Driver Supply Voltage Input High Voltage Input Voltage PECL Clock Input High Voltage PECL Clock Input Voltage Output Current Symbol VDDQ PECL PECL IOUT Min. 3.135 2.375 1.65 -0.3 2.135 1.490 Typ. Max. 3.465 VDD+0.3 1.15 2.420 1.825 Units Notes
voltages referenced VSS. VDD, VDDQ pins must connected. VIH(Max)DC VIH(Max)AC (pulse width 4.0ns). VIL(Min)DC VIL(Min)AC= -1.5 (pulse width 4.0ns). PECL Clock operated LVTTL levels
Capacitance (TA=0 +85°C, VDD= 3.3V ±5%, f=1MHz)
Parameter Input Capacitance Data Capacitance (DQ0-DQ35) Symbol COUT Test Condition VOUT Units
Electrical Characteristics (TA= +85°C, VDD=3.3V ±5%)
Parameter Average Power Supply Operating Current (IOUT VIL) Average Power Supply Operating Current (IOUT VIL, VIL) Power Supply Standby Current =VIH,All other inputs VIL, IOUT Power Supply Standby Current (SS=VIH, ZZ=VIL, other inputs =VIH VIL,IOUT Input Leakage Current, input, except TDI, TMS, (VIN VDD) Output Leakage Current (VOUT 3.0V, High-Z) (VOUT= max, High-Z) Output High Level Voltage (IOH=-8mA 2.4V) VDDQ=3.3V. Output Level Voltage (IOL=+8mA 0.4V) VDDQ=3.3V. Output High Level Voltage (IOH=-8mA 1.6V) VDDQ=2.5V. Output Level Voltage (IOL=+8mA 0.4V) VDDQ=2.5V. Symbol IDD5.5 IDD6 IDD5.5 IDD6 ISBZZ ISBSS ILO1 ILO2 +100 Min. Max. Units Notes
IOUT Chip Output Current. IDD5.5 active current 5.5ns access sort 6.0ns cycle. IDD6 active current other sorts 6.0ns cycle time
75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Test Conditions (TA=0 +85°C, 3.3V ±5%, VDDQ =2.5V -5%/+10%)
Parameter Input High Level Input High Level Input Level Input Level PECL Clock Input High Voltage PECL Clock Input Voltage Input Rise Time Input Fall Time PECL Clock Input Rise Time PECL Clock Input Fall Time Input Output Timing Reference Level (except K,K) PECL Clock Reference Level Output Load Conditions VIH,VIL Data Ins, Addresses Controls when their Time ns.(Verified design) Test Loading page Symbol VIH(1CADVKH) VIL(1CADVKH) VIH-PECL VIL-PECL TR-PECL TF-PECL Conditions 2.25 0.25 1.25 Cross Point Units Notes
Test Loading
16.7 1.25V
16.7
16.7
1.25V
1.25V
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Characteristics (TA=0 +85°C, VDD, 3.3V ±5%, VDDQ 2.5V -5%/+10%)
Parameter Cycle Time Clock High Pulse Width Clock Pulse Width Clock High Output Valid Clock Output Valid Address Setup Time Address Hold Time Sync Select Setup Time Sync Select Hold Time Write Enables Setup Time Write Enables Hold Time Data Setup Time Data Hold Time Clock Data Hold Time Clock Output Active Clock High Output High-Z Output Enable High-Z Output Enable Low-Z Output Enable Output Valid Sleep Mode Recovery TIme Sleep Mode Enable TIme Symbol Min. tKHKH tKHKL tKLKH tKHQV tKLQV tAVKH tKHAX tSVKH tKHSX tWVKH tKHWX tDVKH tKHDX tKLQX tKLQX4 tKHQZ tGHQZ
tGLQX
Max. Min. Max. Min.
Max. Min.
Units Max. Notes
tGLQV tZZR tZZE
Test Loading page This specification Data Retention. data integrity least 200ns Recovery Time recommended coupled with 0.5ns Set-up time around clock. Verified design tested without guardband
75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Timing Diagram (Read Deselect Cycles)
tKLKH tKHKL tAVKH tKHAX tKHSX tWVKH tKHWX tGHQZ tGLQX tKHQV tKLQV tKHQZ tKLQX4 tKLQV tKLQX tKLQV tGLQV tKHQV tKHQZ tSVKH tKHKH
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75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Timing Diagram (Read Write Cycles)
tKLKH tKHKL tAVKH tKHKH
tSVKH tKHSX
tKHAX
tKHWX tWVKH tKHWX tWVKH tKLQV tKLQX4 tKHQV tWVKH tWVKH
tKHWX
tKHWX
tKHQZ
tGHQZ tKHQZ
tKHQV
tKHDX tDVKH
tDVKH tKHDX
NOTES: input data written memory location output data read from write buffer, result address being match from last write cycle address
75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Timing Diagram (Sleep Mode)
tKHKH
tZZE tZZR
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75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
IEEE 1149.1 Boundary Scan
SRAM provides limited JTAG functions intended test interconnection between SRAM I/Os printed circuit board traces other components. There multiplexer path from pins core. conformance with IEEE std. 1149.1, SRAM contains controller, Instruction register, Boundary Scan register, Bypass register register. controller standard 16-state machine that resets internally upon power-up, therefore, TRST signal required. Signal List TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data Test Data
Caution: TCK, TMS, inputs must placed valid logic level, even JTAG used. tied will allow data clocked however. JTAG Recommended Operating Conditions (TA=0 85°C)
Parameter JTAG Input High Voltage JTAG Input Voltage JTAG Output High Level JTAG Output Level JTAG Input Leakage Current (VIN VDD) Symbol VIH1 VIL1 VOH1 VOL1 IJTAG Min. -0.3 Typ. Max. VDD+0.3 Units Notes
JTAG inputs/outputs LVTTL compatible only. IOH1 -8mA 2.4V. IOL1 +8mA 0.4V. JTAG used, signals TCK, left floating. These inputs defaulted with weak active devices
JTAG Test Conditions (TA=0 +85°C, VDD=3.3V ±5%)
Parameter Input Pulse High Level Input Pulse Level Input Rise Time Input Fall Time Input Output Timing Reference Level Test Loading page Symbol VIH1 VIL1
Conditions
Units
Notes
75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
JTAG Characteristics (TA=0 +85°C, VDD=3.3V ±5%)
Parameter Cycle Time High Pulse Width Pulse Width Setup Hold Setup Hold Valid Data Test Loading page Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tTLOV Min. Max. Units Notes
JTAG Timing Diagram
tTHTL tTLTH tTHTH
tTHMX
tTHDX tMVTH
tDVTH
tTLOV
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75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Scan Register Definition
Register Name Instruction Bypass Boundary Scan Boundary Scan chain consists following bits: bits Data Inputs Depending Configuration bits SA16 x36, bits SA17 bits SBWa SBWd x36, bits SBWa SBWb bits bits Place Holders clocks connect differential receiver that generates single-ended clock signal. This signal inverted value used Boundary Scan sampling. Size Size
Register Definition
Field Number Description Part 256K 128K Revision Number (31:28) 0001 0001 Device Density Configuration (27:18) 1011 1100 Vendor Definition (17:12) 001111 001111 Manufacture JEDEC Code (11:1) Start Bit(0)
Instruction
Code Instruction SAMPLE-Z IDCODE SAMPLE-Z PRIVATE SAMPLE PRIVATE PRIVATE BYPASS Notes
Places High-Z order sample input data regardless other SRAM inputs. sampled input first register allow serial shift external data. BYPASS register initiated when BYPASS instruction invoked. BYPASS register also holds last serially loaded when exiting Shift state. SAMPLE instruction does place High-Z. This instruction reserved exclusive IBM. Invoking this instruction cause improper SRAM functionality
List IEEE 1149.1 standard violations: 7.2.1.b, 7.7.1.a-f 10.1.1.b, 10.7.1.a-d
75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Boundary Scan Order (x36) =Place Holder)
Exit Order Signal SA12 SA13 SBWa SBWb DQ16 DQ17 DQ14 DQ15 Bump Exit Order Signal DQ13 DQ11 DQ12 DQ10 SA14 SA15 SA10 SA16 SA11 DQ19 DQ18 DQ21 DQ20 DQ22 DQ24 DQ23 Bump Exit Order Signal DQ26 DQ25 SBWc (PH) C=02 C=12 SBWd DQ34 DQ35 DQ32 DQ33 DQ31 DQ29 DQ30 DQ27 DQ28 Bump
Input register connected Balls unused Clock pins this application
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75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Boundary Scan Order (x18) =Place Holder)
Exit Order Signal SA12 SA13 SA17 SBWa SA14 SA15 SA10 SA16 SA11 Bump Exit Order Signal DQ12 DQ15 DQ16 SBWb (PH) C=02 C=12 DQ17 DQ14 DQ13 DQ11 DQ10 Bump
Input register connected Balls unused Clock pins this application
75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Controller State Machine
Test Logic Reset
Test Idle
Select
Select
Capture
Capture
Shift
Shift
Exit1
Exit1
Pause
Pause
Exit2
Update
Exit2
Update
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75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Dimensions
20.32 0.84 (119X) 0.89 0.04 Solder Ball 0.035" 0.0015(mils) 7.62
3.19
1.27
22.00 16.764
Under fill 12.7 14.00
Indicates Location PLATE CHIP
Structural Adhesive
0.1778
0.625±.254
Under fill PLATE
2.549 0.13
0.701 0.099 0.71 0.05
Note: dimensions Millimeters Unless Otherwise noted
75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
References Last Character Part Number
following documents give recommendations, restrictions limitations level attach process: SRAM Assembly Guide Single Sided Assembly Double Sided 4Meg Coupled PBGA Card Assembly Guide There qualification information, including scope application conditions qualified, available from your marketing representative
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75H4338 Revised 2/99
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IBM04184ARLAD IBM04364ARLAD 128K 256K SRAM
Revision
3/96 5/13/96 7/9/96 7/16/96 10/03/96 11/24/96 12/07/96 12/19/97 1/23/97 3/97 4/97 9/97 5/98 6/98 2/99 Contents Modification Initial Release 128K 256K (5/6/7) REGISTER-LATCH Application Spec. Update part numbers. Corrected footprint. Added Thermal resistance, Updated timings currents. Timing, timing level update Update output leakage Reduced VIH,VIL setup time. VDDQ test -5%, +10% Added Part Number, updated package drawing. Added Sleep Mode note. Removed references Updated Recommended Operating Vddq. Updated JTAG pins. Updated Temp testing documentation from junction ambient. Updated Tklqv both KLKH KHKL -6N. Updated TGLQV. Updated test conditions Data with long set-up. Added nomenclature tristate tests. Added part x36. Updated output leakage spec. Changed Revision Updated mechanical drawing. sort 6.0ns cycle time. Updated references. Tightened ball diameter tolerance
75H4338 Revised 2/99
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International Business Machines Corp.1999
Copyright
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