High Performance SRAM Highlights Access Time 2.25 (Pipeline), 5.7

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High Performance SRAM Highlights Access Time 2.25 (Pipeline), 5.7

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Workstation cache applications 250MHz
High Performance SRAM
Highlights Access Time 2.25 (Pipeline), 5.7ns (Flow Thru), (Register Latch) Cycle Time (Pipeline (Flow Thru), (Register Latch) Organizations Power Dissipation HSTL Active Power (250Mhz) Standby Power HSTL/LVTTL compatible HSTL/PECL clock compatible LVTTL JTAG Package Industry standard Ball Grid Array MO-163. 2.5VI/O capability 3.3Vpower supply Registered addresses, write enables,synch select,data Registered outputs Pipeline operations Register latch operations Programmable HSTL output impedance Asynchronous output enable Flow thru output hold time control Self-timed late write Byte write capability global write enable Asynchronous sleep mode Boundary scan using limited 149.1 functions
Description introduces High Performance Synchronous SRAM workstations, workstation servers, telecommunication applications operating frequencies MHz. These versatile CMOS SRAMs offer wide configurations various voltage interface levels operating with single volt power supply. They support fully pipelined, flow thru, register latch operations.The self-timed late write featured SRAM devices. Pipelined operation accomplished placing registers inputs outputs devices. During read write operation, latency cycle between addresses data expected. Pipelining supported with single clock operation. Flow thru operation accomplished gating output registers with output clock. This dual clock operation provides control data window. output clock used control data output hold time. This mode available with dual clock operation. Register latch operation uses falling edge output clock control output register. Self-timed late write simplifies write operation significantly. SRAM timings require extra cycle when switching from read write operation.
Product Options (All modules 3.3Voperation 7x17 BGA.)
Part Number IBM041810TLAA IBM043610TLAA IBM041811ULAA IBM043611ULAA IBM041811TLAA IBM043611TLAA IBM04181AULAA IBM04361AULAA Features Compatibility Flow Thru, Dual Clock,HSTL Flow Thru, Dual Clock,HSTL Pipeline, Single PECL Clock,LVTTL Pipeline, Single PECL Clock,LVTTL Pipeline, Single Clock,HSTL Pipeline, Single Clock,HSTL Register Latch, Single PECL Clock,LVTTL Register Latch, Single PECL Clock,LVTTL Access Cycle Time (ns) 5.7, 6.8, 4.0, 5.0, 5.0, 5.7, 6.8, 4.0, 5.0, 5.0, 2.5, 5.0, 2.5, 5.0, 2.25, 2.5, 4.0, 5.0, 2.25, 2.5, 4.0, 5.0, 6.0, 6.5, 6.0, 6.0, 6.0, 6.5, 6.0, 6.0, Org.
International Business Machines Corp. 1997 Microelectronics Division 1580 Route Hopewell Junction, 12533-6531 Printed United States America, January 1997 rights reser logo registered trademarks Corporation. This document contain preliminary informa tion subject change without notice. assumes responsibility liability information contained herein. Nothing this document shall operate express implied license indemnity under intellectual property rights third parties. products described this document intended implantation other direct life support applications where malfunction result direct physical harm injury persons. WARRANTIES KIND, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, OFFERED THIS DOCUMENT. datasheets more information contact your Microelectronics Sales Representative. visit World Wide Web:
Microelectronics Manufacturing 9000 compliant.
SA14-xxxx-00
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High Performance SRAM Highlights Access Time 2.25 (Pipeline), 5.7

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