AK2504A DS3/STS-1/E3 Transceiver GENERAL DESCRIPTION AK

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AK2504A DS3/STS-1/E3 Transceiver GENERAL DESCRIPTION AK

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[AK2504A]
AK2504A
DS3/STS-1/E3 Transceiver
GENERAL DESCRIPTION
AK2504A based line transceiver. provides analog transmit/receive line interface functions DS3(44.736MHz) /STS-1(51.84MHz) E3(34.368MHz) interface. Transmitter includes on-chip pulse shaper, B3ZS/ HDB3 Encoder. Pulse level adjustment function very useful pulse into pulse mask customer's system. Receiver includes root-f equalizer, automatic-gain control, clock data recovery, B3ZS/HDB3 Decoder, Loss-Of-Signal Loss-Of-Lock alarm function. Local Remote Loop-back function included system level trouble shooting. device operates single +3.3 Volt supply transparent framing format.
FEATURE
"Robust" based line transceiver Provides Complete Analog Line Transmitter Receiver function DS3, STS-1 Applications Transmit Pulse Level Adjustment Provides Line Equalization, Clock Data Recovery Functions Compliance with Bellcore GR-499-CORE GR-253-CORE, ANSI T1.102, T1.404, Compliance with ITU-T G.703 G.823 Local/Remote Loopback functions B3ZS/HDB3 Encoder/Decoder voltage supply +3.3V
PACKAGE
LQFP
APPLICATIONS
Interfacing network transmission equipment such SONET multiplexor DSX-3 cross connect. Interfacing equipment. network transmission
Interfacing customer premises equipment line.
MS0143-E-01
2004/01
[AK2504A]
BLOCK DIAGRAM
RESET
TAOS
TPDATA TNDATA TCLK
B3ZS/HDB3 ENCODER LOOP BACK PULSE SHAPER OUTPUT DRIVER
TTIP
TRING
CLOCK RECOVERY
RLOL EXCLK EQDIS
TCKPOL RCKPOL RCLK RPDATA RNDATA /LCV TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7
B3ZS/HDB3 DECODER
DATA RECOVERY
GAIN LINE EQUALIZATION
RTIP RRING VDDT VSST VSST VDDA VDDV VSSV VDDP VSSP VDDB VSSB
TEST CIRCUIT LOGIC
VSSD
LOSTHR
RLOS
VSSS VDDD
RLOOP LLOOP
TCAP1 TCAP2 IREF
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LOCATION
TEST1 RTIP RRING LOSTHR RCKPOL TEST7 TTIP VSST TRING VDDT TAOS
EQDIS VDDV VSSV VDDB IREF VSSB TEST6 VDDA RESET RLOS
TCAP1 VSST TCAP2 TEST3 TEST4/eTX TNDATA TPDATA TCLK RNDATA/LCV RPDATA RCLK TEST5
Connection. Leave these pins open.
MS0143-E-01
VDDP VSSP TCKPOL EXCLK RLOOP TEST2 LLOOP VSSS VDDD VSSD RLOL
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[AK2504A]
CONDITION
Name VDDP VSSP TCKPOL EXCLK RLOOP TEST2 LLOOP VSSS VDDD VSSD RLOL TEST5 RCLK RPDATA RNDATA /LCV TCLK TPDATA TNDATA TEST4 TEST3 TCAP2 VSST TCAP1 Analog Note CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Analog Note 15pF 15pF 15pF 15pF CMOS CMOS CMOS CMOS CMOS Type CMOS Maximum load Minimum load Status Reset
Remarks
Note: number Connection. Leave these pins open. 1)External capacitor (0.1 connected VSS.
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[AK2504A]
Name TAOS VDDT TRING VSST TTIP TEST7 RCKPOL LOSTHR
Type CMOS Analog Analog CMOS CMOS Analog CMOS Analog Analog CMOS CMOS
Maximum load
Minimum load
Status Reset
Remarks
Hi-Z Hi-Z
RRING RTIP TEST1 EQDIS VDDV VSSV VDDB IREF VSSB TEST6 VDDA
RESET
Analog Analog CMOS CMOS CMOS CMOS 15pF
Note Note
Note
RLOS
Note *)NC number Connection. Leave these pins open. 2)External resister k±1% should connected between IREF VSS. 3)External resister should connected between VSS. Normally 1.33k connected DS3/STS-1 1.27k 4)Pulled with internal register. (typical
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[AK2504A]
DESCRIPTION
Receive Name LOSTHR Function Loss Signal Threshold Control (See Table voltage forced this controls input loss-of-signal threshold. settings provided forcing VDD. Receive Loss-of-Lock Active High alarm. recovered clock frequency larger than approximately 0.5% EXCLK, RLOL alarm goes High. Receive Input Receive input differential signal. Requires transformer. Receive Ring Input Receive input differential signal. Requires transformer. Receive Loss-of-Signal. This high loss incoming signal RIN. External Reference Clock. valid DS3/STS-1/E3 clock must provided this input. EXCLK frequency determines operating frequency device. Recovered Clock. Receive Negative Data/Line Code Violation Indicator This pin's function depends input level. Receive Negative Data output High Bipolar Violation Output period High level signal output bipolar violation corresponding appropriate coding rule code error detected incoming data stream. violation pulse corresponding appropriate coding rule removed from incoming data. Receive Positive Data This pin's function depends input level. Receive Positive Data output high data output RCLK Polarity select. RCKPOL=L Received data output rising edge RCLK. RCKPOL=H Received data output falling edge RCLK. Equalizer Disable. When EQDIS=H, Equalizer disable. Power Supply ADC. Power Supply VGA. Ground VGA. Ground PLL. Power Supply PLL. volts. +3.3 volts. volts. +3.3 volts. +3.3 volts. +3.3 volts
RLOL RTIP RRING RLOS EXCLK RCLK
RNDATA /LCV
RPDATA
RCKPOL EQDIS VDDA VDDV VSSV VDDP VSSP VDDB VSSB
volts.
Power Supply Bandgap Reference. Ground Bandgap Reference.
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[AK2504A]
Transmit Name TPDATA
TNDATA
TCLK
TCKPOL TTIP TRING
Function Transmit Positive Data/NRZ data This pin's function depends input level. Positive data output High data Transmit Negative Data This pin's function depends input level. Negative data output High Should tied Transmit Clock TPDATA TNDATA sampled rising falling edge TCLK. Sampling edge must assigned TCKPOL pin. TCLK Polarity select. TCKPOL=Low Transmit data sampled rising edge TCLK. TCKPOL=High Transmit data sampled falling edge TCLK. Transmit Ring Output signal output. Requires 1:1CT transformer. Hi-Z when RESET Low. Pulse Level Adjustment Transmit pulse level adjusted external resister. Normally 1.33k connected DS3/STS-1 1.27k signal power level larger than requirement, tweak increasing value this resister. mode Enable Active High input enables data interface with TPDATA RPDATA. TPDATA TNDATA Positive Negative (VSS) RPDATA RNDATA Positive Negative
mode, TNDATA should tied RNDATA indicates LCV. Line Built High, Line Built function enable. input High Cable length 450ft 225ft
TCAP1 TCAP2 TAOS VDDT VSST
This active only with High(DS3/STS-1 mode). Reference Voltage Output driver. external capacitor (0.1µF±20%) should connected VSSA. Reference Voltage Output driver. external capacitor (0.1µF±20%) should connected VSSA. Transmit Ones Select Active High input. continuous pattern transmitted from TTIP TRING. Transmit rate defined TCLK. Power Supply Transmitter. +3.3 volts. Ground Transmitter. volts
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[AK2504A]
Others Name
IREF RLOOP
LLOOP
RESET
TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 VDDD VSSD VSSS
Function DS3/STS-1 select High DS3/STS-1 Current Reference Output External resistance (4.7 k±1%) should connected VSSA. Remote Loop Back Active High input. RPDATA RNDATA transmitted from TTIP TRING using RCLK. Input High both RLOOP LLOOP inhibited. Local Loop Back Active High input. TPDATA,TNDATA TCLK looped back RPDATA, RNDATA RCLK. Input High both RLOOP LLOOP inhibited. Active RESET. Pulled with internal resister. Test Mode. Should connected VSS. TEST1=High part goes into Test mode. TEST1=Low part goes into Normal operation mode. Should connected VSS. Should connected VSS. Output "Low" when TEST1=Low (Normal operation mode) Should connected VSS. Should connected VSS. Should open. Power Supply Digital. Ground Digital. Ground Substrate. +3.3 volts. volts volts
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[AK2504A]
FUNCTIONAL DESCRIPTION
AK2504A provides basic transmit receive functions high-speed line card.
Signal Requirements
DS3/STS1 Pulse characteristics specified DSX-3. Table Interface Specification Parameter Line Rate Line Code Test Load Standards 44.736Mbps±20ppm B3ZS 75±5% GR-499-CORE ANSI T1.102 T1.404 Specification
Table STS-1 Interface Specification Parameter Line Rate Line Code Test Load Standards 51.840Mbps±20ppm B3ZS 75±5% GR-253-CORE ANSI T1.102 Specification
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[AK2504A]
Normalized Amplitude
Normilized Amplitude
-0.2 -1.00
-0.2 -1.0 -0.5 Time[UI]
-0.50
0.00 Time[UI]
0.50
1.00
1.50
Fig. DSX-3 Pulse Mask
Fig. STS-1 Pulse Mask
Table Pulse Mask Equations (ANSI T1.102, T1.404, GR-499-CORE)
Lower Curve Upper Curve
Time -0.85 -0.36 -0.36 0.36 0.36
Equation -0.03 0.5{1+sin[(/2)(1+T/0.18)]}-0.03 -0.03
Time -0.85 -0.68 -0.68 0.36 0.36
Equation 0.03 0.5{1+sin[(/2)(1+T/0.34)]}+0.03 0.08+0.407e-1.84(T-0.36)
Table STS-1 Pulse Mask Equations (GR-253-CORE, T1.102)
Lower Curve Upper Curve
Time -0.85 -0.36 -0.36 0.36 0.36
Equation -0.03 0.5{1+sin[(/2)(1+T/0.18)]}-0.03 -0.03
Time -0.85 -0.68 -0.68 0.26 0.26
Equation 0.03 0.5{1+sin[(/2)(1+T/0.34)]}+0.03 0.1+0.61e-2.4(T-0.26)
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Pulse characteristics specified output ports Table Pulse Specification (G.703)
Pulse shape (nominally rectangular) Pair(s) each direction Test load impedance Nominal peak voltage mark (pulse) Peak voltage space pulse) Nominal pulse width Ratio amplitudes positive negative pulses center pulse interval Ratio widths positive negative pulses nominal half amplitude marks valid signal must conform with mask (see Fig.3), irrespective sign coaxial pair resistive 14.55 0.95 1.05 0.95 1.05
(14.55 2.45)
8.65 (14.55 5.90) Nominal pulse 14.55
12.1 (14.55 2.45)
24.5 (14.55 9.95) 29.1 (14.55 14.55)
T1818860-92
FIGURE 17/G.703
Pulse mask 368-kbit/s interface
Fig. Pulse Mask
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[AK2504A]
Logic Data Interface
AK2504A handle Positive/Negative data data. Positive/Negative data Interface Low, transmitter accepts Positive/Negative transmit data TPDATA/TNDATA receiver outputs Positive/Negative received data RPDATA/RNDATA. this mode, B3ZS/HDB3 Encoder/Decoder disable. Transmit Received data output transparently. data Interface High, transmitter accepts transmit data TPDATA (TNDATA should tied VSS). receiver outputs received data RPDATA. this mode, B3ZS/HDB3 Encoder/Decoder enable. alarm will indicated RNDATA whenever bipolar violation detected incoming data stream.
Disable TPOS TNEG RPOS RNEG TPDATA TNDATA RPDATA RNDATA B3ZS HDB3 Encoder Decoder TNRZ TPDATA TNDATA RNRZ RPDATA RNDATA High Enable B3ZS HDB3 Encoder Decoder
Positive/Negative
Fig. Logic Data Interface
Line Code Violation
bipolar violation corresponding appropriate coding rule code error detected incoming data stream, high period. violation pulse corresponding appropriate coding rule removed from incoming data. Bipolar Violation B3ZS, HDB3 HDB3: (+1,+1) (-1,-1) (+1, 0,+1) (-1, 0,-1) RPDATA -LCV -RPDATA
Coding Violation (With even number since last B3ZS HDB3: 0,+1) 0,-1) 0,+1) 0,-1) RPDATA -LCV -RPDATA -LCV
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[AK2504A]
Excessive Zeros B3ZS HDB3: RPDATA -LCV -RPDATA -LCV
Receive data includes B3ZS encode error
Bipolar violation
Code violation
Excessive zeros
RPDATA
Fig. RPDATA outputs mode (B3ZS)
Receive data includes HDB3 encode error
Bipolar violation
Code violation
Excessive zeros
RPDATA
Fig. RPDATA outputs mode (HDB3)
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[AK2504A]
Pulse Shaper
Pulse Shaper generates waveform meeting pulse mask such described Table 3,4,5. input data Pulse Shaper sampled data TPDATA and/or TNDATA pins rising falling edge TCLK. Polarity TCLK selected TCKPOL pin.
Line Built
When High, transmit pulse output through circuit which makes transmit pulse filtered with frequency response equivalent 225ft cable. Table Transmit Pulse Amplitude (DS3/STS-1) High Cable Length 225ft DS3, STS-1 1150mVpk(typ) 800mVpk(typ)
Note; active only with High(DS3/STS-1 mode).
Transmit Ones Select
TAOS high, continuos transmitted from TTIP/TRING. While this pattern transmitted, input data TPDATA/TNDATA ignored. Local Loopback mode (LLOOP high), TAOS request accepted input data TPDATA/TNDATA loopback RPDATA/RNDATA. Remote Loopback mode (RLOOP high), TAOS request accepted recoverd data output RPDATA/RNDATA.
Line Short Protect
Line short, there large current transmit output driver because that driver current source drive type.
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[AK2504A]
Equalization
DS3/STS1 incoming data have loss cable and/or flat. Cable type length from cross-connect specified shown Table Equalizer compensates appropriately nominal DSX-3/STS-1 pulse attenuated feet 728A cable. Table DS3/STS-1 Cable Specification Parameter Cable Type Cable Length incoming data have cable loss shown Table Equalizer compensates appropriately nominal pulse attenuated cable. Table Cable Specification Parameter Cable Loss 12dB Specification Remarks Fig.7-(1)(2) Specification Type 728A coaxial cable equivalent) feet (from DSX-3 point) Fig.7-(1)(2) Remarks
Equalizer Bypass
incoming signal attenuated flat loss only (zero cable loss), internal equalizer should bypassed with EQDIS=1. level incoming signal should satisfy input range (50mVpk 1000mVpk DS3/STS-1, 90mVpk 1200mVpk E3). Table Equalizer Bypass Control EQDIS Equalizer Enable Bypass
Flat Loss (1)Cable loss Flat loss Cable AK2504
EQDIS
DSX-3 STS-1 DSX-3 Transmitter Port Flat loss only
feet STS-1:0 feet
Equalizer enable
Flat Loss Transmitter
Monitoring circuit
AK2504
EQDIS
Equalizer bypass
Fig. AK2504A Application MS0143-E-01 2004/01
[AK2504A]
Clock Acquisition
valid input signal assumed already present analog input, maximum time between application device power error-free operation typically Table Lock Acquisition Time
Tmin Tmax; 3.3V±0.3V; GND**
Power Input data restore
Conditions Power Input data Valid Power Input data Loss Valid
Units
GND=VSSP= VSSV= VSSB=VSST=VSSS=VSSD=0V
Output Jitter
Typical output jitter characteristics shown table ANALOG SPECIFICATIONS
Jitter Transfer
Jitter transfer characteristics shown table ANALOG SPECIFICATIONS.
Jitter Tolerance
Typical jitter tolerance characteristics shown table ANALOG SPECIFICATIONS. DS3/STS-1 Compliance with GR-499-CORE, GR-253-CORE, G.752, G.824 Compliance with ITU-T G.823.
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[AK2504A]
Loopback
AK2504A loopback modes, which Remote Loopback mode Local Loopback mode. Each function those shown Table Fig. Table Loopback Function Mode Remote Local RLOOP LLOOP RPDATA RNDATA TPDATA TNDATA TCLK TTIP TRING RPDATA RNDATA RCLK Function Transmit rate determined RCLK. TPDATA/TNDATA ignored. Transmit rate determined TCLK. TPDATA/TNDATA ignored.
permitted that both RLOOP LLOOP high.
LOOP BACK
Remote LoopBack
RLOOP=1 LLOOP=0
TPDATA TNDATA TCLK
B3ZS/HDB3 ENCODER PULSE SHAPER OUTPUT DRIVER
TTIP TRING
RPDATA RNDATA/BPV RCLK
B3ZS/HDB3 ENCODER
CLOCK&DATA RECOVERY
RTIP RRING
RLOOP LLOOP
LOOP BACK
Local LoopBack
RLOOP=0 LLOOP=1
TPDATA TNDATA TCLK
B3ZS/HDB3 ENCODER PULSE SHAPER OUTPUT DRIVER
TTIP TRING
RPDATA RNDATA/BPV RCLK
B3ZS/HDB3 ENCODER
CLOCK&DATA RECOVERY
RTIP RRING
RLOOP LLOOP
Fig. Loopback Path
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[AK2504A]
Output status related NRZ, TAOS, RLOOP, LLOOP input
Table Output status TAOS RLOO LLOO TTIP/TRING ones ones ones Recovered data Recovered data Recovered data ones ones ones TPDATA/TNDATA TPDATA/TNDATA(HDB3) TPDATA/TNDATA(B3ZS) ones TPDATA/TNDATA TPDATA/TNDATA(HDB3) TPDATA/TNDATA(B3ZS) RPDATA/RNDATA Recovered data Recovered data(UNHDB3) Recovered data(UNB3ZS) Recovered data Recovered data(UNHDB3) Recovered data(UNB3ZS) TPDATA/TNDATA TPDATA/TNDATA(UNHDB3) TPDATA/TNDATA(UNB3ZS) TPDATA/TNDATA TPDATA/TNDATA(UNHDB3) TPDATA/TNDATA(UNB3ZS) Recovered data Recovered data Recovered data(UNHDB3) Recovered data(UNB3ZS)
Loss-of-Lock Detection
recovered clock frequency larger than approximately 0.5% EXCLK, RLOL alarm goes High.
External Reference Clock
external reference clock EXCLK used frequency PLL. frequency EXCLK should within ideal clock±100ppm.
Reset
AK2504A goes into RESET status RESET input low. Output pins status follows during input RESET RLOS RLOL RPDATA RNDATA RCLK High High High
Test Mode
AK2504A goes into Test Mode when TEST1 High.
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[AK2504A]
Loss Signal DS3/STS-1
AK2504A detects loss signal analog digital methods. Loss Signal function DS3/STS-1 mode follows. Analog Loss Signal(ALOS) Analog loss detector operates follows. Analog loss detector monitors peak level incoming signal. peak level falls below Alarm threshold shown Table output pins status shown diagram below.
Table Analog Loss-of-Signal thresholds (DS3/STS-1/E3) LOSTHR Voltage Clear Alarm Level Min. Upper Threshold Max. Upper Threshold Alarm Level Min. Lower Threshold Max. Lower Threshold Units mVpk mVpk
Notes: Alarm Level 0.5dB lower than Clear Alarm Level. Digital Loss Signal(DLOS) Digital loss detector operates follows. digital loss detector monitors consecutive density recovered data. RLOS high 175±5 consecutive detected. RPDATA,RNDATA ALOS detected. RLOS density consecutive bits) consecutive detected.
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Normal Operation
RCLK Recovered from data RPDATA Recovered data RNDATA Recovered data RLOS 175bits incoming data includes following data. 58bits (33% density) 100bits consecutive
bits consecutive incoming data
DLOS
RCLK Recovered from data RPDATA Recovered data RNDATA Recovered data RLOS Peak level incoming data Alarm Threshold Level High
Peak level incoming data
Clear Alarm Threshold Level
ALOS
RCLK Recovered from EXCLK RPDATA RNDATA RLOS High
Fig. Loss Signal state diagram (DS3/STS-1)
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[AK2504A]
Loss Signal
AK2504A detects loss signal analog digital methods. Loss Signal function mode follows.
Analog loss detector monitors peak level incoming signal. peak level falls below Alarm Threshold Level shown Table DLOS circuit starts counting number incoming data bits described following section "DLOS". DLOS circuit detects consecutive 128±5 bits incoming data lower than Alarm Threshold Level, AK2504A alarms Loss Signal setting RLOS high. Other output pins status shown diagram below. RLOS 32±5 bits incoming data higher than Clear Alarm Threshold Level detected.
Normal Operation
RCLK Recovered from input RPDATA Recovered data RNDATA Recovered data RLOS
Peak level incoming data
Alarm Threshold Level
Peak level incoming data
Alarm Threshold Level
consecutive bits incoming data
bits incoming data
RCLK Recovered from EXCLK RPDATA RNDATA RLOS High
Fig. Loss Signal state diagram (E3)
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[AK2504A]
ABSOLUTE MAXIMUM RATINGS
Parameter Supply (referenced GND) (Note Input Voltage, Input Current, (Note Ambient Operating Temperature Storage Temperature Power Dissipation Symbol Tstg -0.3 GND-0.3 (V+)+0.3 Units
WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes. Note; 2.Transient currents will cause latch
RECOMMENDED OPERATING CONDITIONS
Parameter Supply (referenced GND) Ambient Operating Temperature Supply Current: STS-1 EXCLK Frequency Symbol Condition Units
PN20 PN20 PN20
44.736 100ppm 51.84 100ppm 34.368 100ppm
44.736
44.736 100ppm 51.84 100ppm 34.368 100ppm
STS-1
51.84 34.368
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[AK2504A]
RECEIVER
ANALOG SPECIFICATIONS
Tmin Tmax; 3.3V±0.3V;
Parameter
Condition
0.05
Units
Uipp Uipp Uipp Uipp Uipp
Jitter Transfer Bandwidth with repetitive pattern (Note Peaking Jitter Tolerance 5kHz 10kHz 60kHz
(Note
300kHz 1MHz one's pattern Repetitive 1000 pattern DS3/STS1
Signal Noise Immunity Output Jitter
(Note (Note
1000 1200
nsp-p nsp-p mVpk mVpk bits bits bits
Output Clock Duty Cycle Receiver Input Range
(Note
DLOS detection Loss Detection RPDATA Delay Time
DS3/STS1
Note; Measured with repetitive input nominal DSX-3 level(DS3/STS-1), nominal G.703 level(E3) with (V+)=3.3V, TA=25°C Typical performance shown Measured with sinusoidal noise, peak amplitude noise 11dB down from peak amplitude signal. noise frequency 22MHz(DS3), 25MHz(STS-1), 17MHz(E3).
Jitter Amplitude [UIpp]
1000 10000
itte
Fig. Jitter Tolerance
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[AK2504A]
TRANSMITTER
ANALOG SPECIFICATIONS
Tmin Tmax; 3.3V±0.3V;
Parameter Transmitter amplitude (Note DS3/STS1
Condition LBO=1 LBO=0
1050
1150 1000
1250 1080
Units
mVpk mVpk mVpk
Note; Measured line side transformer.
DIGITAL CHARACTERISTICS
Tmin Tmax; 3.3V±0.3V; Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage IOUT=-40µA Low-Level Output Voltage Input Leakage Current IOUT=1.6mA (Note IOUT=0.4mA (Note
(Note
Symbol
(V+) (V+)
(V+) (V+)
Units
Note; RCLK, RPDATA, RNDATA RLOS, RLOL, TEST4, TEST7 Except RESET
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[AK2504A]
RECEIVER SWITCHING SPECIFICATIONS
Tmin Tmax; 3.3V±0.3V; Input: Logic Logic Parameter RCLK Pulse Width RCLK Pulse Width RCLK Pulse Width STS-1 Symbol Tpwh (Note Tpwl Tpwh (Note Tpwl Tpwh (Note Tpwl 10.1 10.1 13.1 13.1 11.177 11.177 9.645 9.645 14.548 14.548 12.2 12.2 10.6 10.6 16.0 16.0 Units
EXCLK Duty Cycle (EXCLK Rise/Fall time 5ns) Rise Time, RCLK Fall Time, RCLK
(Note (Note
Delay Time: RCLK high RPDATA/RNDATA (Note Tdcrd
TRANSMITTER SWITCHING SPECIFICATIONS
Tmin Tmax; 3.3V±0.3V; Input: Logic Logic Parameter TCLK Duty Cycle (TCLK Rise/Fall time 5ns) Rise Time, TCLK Fall Time, TCLK
(Note (Note
Symbol
Units
Tstdc Thtdc
Setup Time, TPDATA/TNDATA TCLK Falling Hold Time, TPDATA/TNDATA TCLK Falling
Note;
Assumes locked 44.736 signal. pulse widths must always meet frequency specifications. Assumes locked 51.84 signal Assumes locked 34.368MHz signal. Load 15pF.
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[AK2504A]
RCLK
Fig. Signal Rise Fall Characteristics
RCLK RPDATA RNDATA
dcrd
Fig. Recovered Clock Data Switching Characteristics
pwh1
VDD/2
EXCLK
Fig. EXCLK Duty Cycle Requirements
TCLK
TPDATA TNDATA
Fig. Transmitter Switching Characteristics
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[AK2504A]
Application Circuit Example
Note
Leave following pins open.
Recommended Diode
diode with V(forward) 0.58V 0.89V I(forward)=10mA temperature range used. e.g. 1SS184, 1SS181
3.3V FRAMER CONTROL LOGIC Open 26,40 CLOCK SOURCE TCLK TPDATA TNDATA RCLK RPDATA RNDATA TCKPOL RCKPOL TAOS RLOL RLOS LOSTHR EQDIS VSSV VDDP VSSP VDDV VDDA RRING TRING TTIP
AK2504A
VSST
COAX
RTIP
37.4
37.4 0.01 3.3V 0.01
0.01
0.01
RESET
RLOOP LLOOP
VDDB VSSB VDDT VSST
0.01
TEST1 TEST2 TEST3 TEST4, TEST7 TEST5 TEST6 EXCLK TCAP1 TCAP2 0.1uF
0.01
VDDD VSSD VSSS
0.01
Recommended Transformer
Maker Product WBTRID2.5-J004C002 WBTRID2.5-0340N Ratio 1CT:1
IREF k±1%
0.1uF
RPLA
RPLA: 1.33k DS3/STS-1, 1.27k
NOTE) power transmit signal larger than requirement, power reduced increasing value RPLA.
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[AK2504A]
Marking
64pin LQFP indication Date Code: 7digits XXXXYZZ (3)Marketing Code: AK2504A (4)AKM Logo
AK2504A XXXXYZZ
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[AK2504A]
Outline Dimensions
12.0±0.3 10.0
12.0±0.3
10.0
0.21±0.05
1.70MAX
0.10
0°-10° 1.40
MS0143-E-01
0.17±0.05
0.45±0.2
0.10
0.10±0.10
2004/01
[AK2504A]
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
MS0143-E-01
2004/01

AK2504A DS3/STS-1/E3 Transceiver GENERAL DESCRIPTION AK

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