Programmable Logic Device Family March 2001, ver. Features.

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Programmable Logic Device Family March 2001, ver. Features.

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3000A
Programmable Logic Device Family
March 2001, ver.
Features.
High-performance, low-cost CMOS EEPROM-based programmable logic devices (PLDs) built MAX® architecture (see Table 3.3-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability circuitry compatible with IEEE Std. 1532 Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 Enhanced features: Enhanced algorithm faster programming ISP_Done ensure complete programming Pull-up resistor pins during in-system programming High-density PLDs ranging from 5,000 usable gates 4.5-ns pin-to-pin logic delays with counter frequencies 227.3 MultiVoltI/O interface enabling device core while pins compatible with 5.0-V, 3.3-V, 2.5-V logic levels counts ranging from variety thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J-lead chip carrier (PLCC) packages Hot-socketing support Programmable interconnect array (PIA) continuous routing structure fast, predictable performance compatible Bus-friendly architecture including programmable slew-rate control Open-drain output option
Table 3000A Device Features Feature
Usable gates Macrocells Logic array blocks Maximum user pins (ns) (ns)
EPM3032A
EPM3064A
1,250
EPM3128A
2,500
EPM3256A
5,000
Altera Corporation
A-DS-M3000A-02.0
3000A Programmable Logic Device Family
Table 3000A Device Features Feature
tCO1 (ns) fCNT (MHz)
EPM3032A
227.3
EPM3064A
222.2
EPM3128A
192.3
EPM3256A
172.4
.and More Features
Programmable macrocell flipflops with individual clear, preset, clock, clock enable controls Programmable power-saving mode power reduction over each macrocell Configurable expander product-term distribution, allowing product terms macrocell Programmable security protection proprietary designs Enhanced architectural features, including: pin- logic-driven output enable signals global clock signals with optional inversion Enhanced interconnect resources improved routability Programmable output slew-rate control Software design support automatic place-and-route provided Altera's development systems Windows-based SPARCstations, 9000 Series 700/800 workstations Additional design entry simulation support provided EDIF netlist files, library parameterized modules (LPM), Verilog HDL, VHDL, other interfaces popular tools from third-party manufacturers such Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest Programming support with Altera master programming unit (MPU), MasterBlastercommunications cable, ByteBlasterMVparallel port download cable, BitBlasterserial download cable well programming hardware from third-party manufacturers in-circuit tester that supports JamStandard Test Programming Language (STAPL) Files (.jam), STAPL Byte-Code Files (.jbc), Serial Vector Format Files (.svf)
General Description
3000A devices low-cost, high-performance devices based Altera architecture. Fabricated with advanced CMOS technology, EEPROM-based 3000A devices operate with 3.3-V supply voltage provide 5,000 usable gates, ISP, pin-to-pin delays fast counter speeds 227.3 MHz. 3000A devices speed grades compatible with timing requirements Special Interest Group (PCI SIG) Local Specification, Revision 2.2. Table
Altera Corporation
3000A Programmable Logic Device Family
Table 3000A Speed Grades Device
EPM3032A EPM3064A EPM3128A EPM3256A Note:
Contact Altera up-to-date information availability this speed grade.
Speed Grade
3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation high-density small-scale integration (SSI), medium-scale integration (MSI), large-scale integration (LSI) logic functions. 3000A architecture easily integrates multiple devices ranging from PALs, GALs, 22V10s MACH pLSI devices. 3000A devices available wide range packages, including PLCC, PQFP, TQFP packages. Table Table 3000A Maximum User Pins Device
EPM3032A EPM3064A EPM3128A EPM3256A Notes:
Contact Altera up-to-date information available device package options. When IEEE Std. 1149.1 (JTAG) interface used in-system programming boundary-scan testing, four pins become JTAG pins.
Notes (1), 144-Pin TQFP 208-Pin PQFP
44-Pin PLCC
44-Pin TQFP
100-Pin TQFP
3000A devices CMOS EEPROM cells implement logic functions. user-configurable 3000A architecture accommodates variety independent combinatorial sequential logic functions. devices reprogrammed quick efficient iterations during design development debugging cycles, programmed erased times.
Altera Corporation
3000A Programmable Logic Device Family
3000A devices contain macrocells, combined into groups macrocells called logic array blocks (LABs). Each macrocell programmable-AND/fixed-OR array configurable register with independently programmable clock, clock enable, clear, preset functions. build complex logic functions, each macrocell supplemented with shareable expander high-speed parallel expander product terms provide product terms macrocell. 3000A devices provide programmable speed/power optimization. Speed-critical portions design high speed/full power, while remaining portions reduced speed/low power. This speed/power optimization feature enables designer configure more macrocells operate lower power while adding only nominal timing delay. 3000A devices also provide option that reduces slew rate output buffers, minimizing noise transients when non-speed-critical signals switching. output drivers 3000A devices input pins 2.5-V, 3.3-V, 5.0-V tolerant, allowing 3000A devices used mixed-voltage systems. 3000A devices supported Altera development systems, which integrated packages that offer schematic, text-including VHDL, Verilog HDL, Altera Hardware Description Language (AHDL)-and waveform design entry, compilation logic synthesis, simulation timing analysis, device programming. software provides EDIF LPM, VHDL, Verilog HDL, other interfaces additional design entry simulation support from other industry-standard UNIX-workstation-based tools. software runs Windows-based PCs, well SPARCstation, 9000 Series 700/800 workstations.
Functional Description
more information development tools, MAX+PLUS Programmable Logic Development System Software Data Sheet andthe Quartus Programmable Logic Development System Software Data Sheet. 3000A architecture includes following elements:
Logic array blocks (LABs) Macrocells Expander product terms (shareable parallel) Programmable interconnect array (PIA) control blocks
3000A architecture includes four dedicated inputs that used general-purpose inputs high-speed, global control signals (clock, clear, output enable signals) each macrocell pin. Figure shows architecture 3000A devices.
Altera Corporation
3000A Programmable Logic Device Family
Figure 3000A Device Block Diagram
INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1
INPUT/GCLRn Output Enables
Output Enables
Control Block
Macrocells
Macrocells
Control Block
Macrocells
Control Block
Macrocells
Control Block
Logic Array Blocks
3000A device architecture based linking high-performance LABs. LABs consist 16-macrocell arrays, shown Figure Multiple LABs linked together PIA, global that dedicated input pins, pins, macrocells. Each following signals:
signals from that used general logic inputs Global controls that used secondary register functions
Macrocells
3000A macrocells individually configured either sequential combinatorial logic operation. Macrocells consist three functional blocks: logic array, product-term select matrix, programmable register. Figure shows 3000A macrocell.
Altera Corporation
3000A Programmable Logic Device Family
Figure 3000A Macrocell
Local Array Global Clear Parallel Logic Expanders (from other macrocells) Global Clocks Programmable Register Register Bypass Control Block
ProductTerm Select Matrix
Clock/ Enable Select
CLRN
Clear Select
Shared Logic Expanders Signals from Expander Product Terms
Combinatorial logic implemented logic array, which provides five product terms macrocell. product-term select matrix allocates these product terms either primary logic inputs gates) implement combinatorial functions, secondary inputs macrocell's register preset, clock, clock enable control functions. kinds expander product terms ("expanders") available supplement macrocell logic resources:
Shareable expanders, which inverted product terms that back into logic array Parallel expanders, which product terms borrowed from adjacent macrocells
Altera development system automatically optimizes product-term allocation according logic requirements design.
Altera Corporation
3000A Programmable Logic Device Family
registered functions, each macrocell flipflop individually programmed implement operation with programmable clock control. flipflop bypassed combinatorial operation. During design entry, designer specifies desired flipflop type; Altera development system software then selects most efficient flipflop operation each registered function optimize resource utilization. Each programmable register clocked three different modes:
Global clock signal mode, which achieves fastest clock-to-output performance. Global clock signal enabled active-high clock enable. clock enable generated product term. This mode provides enable each flipflop while still achieving fast clock-to-output performance global clock. Array clock implemented with product term. this mode, flipflop clocked signals from buried macrocells pins.
global clock signals available 3000A devices. shown Figure these global clock signals true complement either global clock pins, GCLK1 GCLK2. Each register also supports asynchronous preset clear functions. shown Figure product-term select matrix allocates product terms control these operations. Although product-term-driven preset clear from register active high, active-low control obtained inverting signal within logic array. addition, each register clear function individually driven active-low dedicated global clear (GCLRn).
Expander Product Terms
Although most logic functions implemented with five product terms available each macrocell, highly complex logic functions require additional product terms. Another macrocell used supply required logic resources. However, 3000A architecture also offers both shareable parallel expander product terms ("expanders") that provide additional product terms directly macrocell same LAB. These expanders help ensure that logic synthesized with fewest possible logic resources obtain fastest possible speed.
Altera Corporation
3000A Programmable Logic Device Family
Shareable Expanders
Each shareable expanders that viewed pool uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into logic array. Each shareable expander used shared macrocells build complex logic functions. Shareable expanders incur small delay (tSEXP). Figure shows shareable expanders feed multiple macrocells. Figure 3000A Shareable Expanders
Shareable expanders shared macrocells LAB.
Macrocell Product-Term Logic
Product-Term Select Matrix
Macrocell Product-Term Logic
Signals from
Shared Expanders
Parallel Expanders
Parallel expanders unused product terms that allocated neighboring macrocell implement fast, complex logic functions. Parallel expanders allow product terms directly feed macrocell logic, with five product terms provided macrocell parallel expanders provided neighboring macrocells LAB.
Altera Corporation
3000A Programmable Logic Device Family
Altera development system compiler automatically allocate three sets five parallel expanders macrocells that require additional product terms. Each five parallel expanders incurs small, incremental timing delay (tPEXP). example, macrocell requires product terms, compiler uses five dedicated product terms within macrocell allocates sets parallel expanders; first includes five product terms, second includes four product terms, increasing total delay tPEXP. groups eight macrocells within each (e.g., macrocells through through form chains lend borrow parallel expanders. macrocell borrows parallel expanders from lower- numbered macrocells. example, macrocell borrow parallel expanders from macrocell from macrocells from macrocells Within each group eight, lowest-numbered macrocell only lend parallel expanders highest-numbered macrocell only borrow them. Figure shows parallel expanders borrowed from neighboring macrocell. Figure 3000A Parallel Expanders
Unused product terms macrocell allocated neighboring macrocell.
From Previous Macrocell
Preset Producter Select Matrix Clock Clear
Macrocell ProductTerm Logic
Preset ProductT Term Select Matrix Clock Clear
Macrocell ProductTerm Logic
Signals from
Shared Expanders
Next Macrocell
Altera Corporation
3000A Programmable Logic Device Family
Programmable Interconnect Array
Logic routed between LABs PIA. This global programmable path that connects signal source destination device. 3000A dedicated inputs, pins, macrocell outputs feed PIA, which makes signals available throughout entire device. Only signals required each actually routed from into LAB. Figure shows signals routed into LAB. EEPROM cell controls input two-input gate, which selects signal drive into LAB. Figure 3000A Routing
Signals
While routing delays channel-based routing schemes masked FPGAs cumulative, variable, path-dependent, 3000A predictable delay. makes design's timing performance easy predict.
Control Blocks
control block allows each individually configured input, output, bidirectional operation. pins have tri-state buffer that individually controlled global output enable signals directly connected ground VCC. Figure shows control block 3000A devices. control block global output enable signals that driven true complement output enable signals, subset pins, subset macrocells.
Altera Corporation
3000A Programmable Logic Device Family
Figure Control Block 3000A Devices
Global Output Enable Signals
Select Multiplexer
Other Pins From Macrocell
Open-Drain Output Slew-Rate Control
When tri-state buffer control connected ground, output tri-stated (high impedance), used dedicated input. When tri-state buffer control connected VCC, output enabled. 3000A architecture provides dual feedback, which macrocell feedbacks independent. When configured input, associated macrocell used buried logic.
In-System Programmability
3000A devices programmed in-system industry- standard four-pin IEEE Std. 1149.1-1990 (JTAG) interface. In-system programmability (ISP) offers quick, efficient iterations during design development debugging cycles. 3000A architecture internally generates high programming voltages required program EEPROM cells, allowing in-system programming with only single 3.3-V power supply. During in-system programming, pins tri-stated weakly pulled-up eliminate board conflicts. pull-up value nominally
Altera Corporation
3000A Programmable Logic Device Family
3000A devices have enhanced algorithm faster programming. These devices also offer ISP_Done that ensures safe operation when in-system programming interrupted. This ISP_Done bit, which last programmed, prevents pins from driving until programmed. simplifies manufacturing flow allowing devices mounted printed circuit board (PCB) with standard pick-and-place equipment before they programmed. 3000A devices programmed downloading information in-circuit testers, embedded processors, MasterBlaster communications cable, ByteBlasterMV parallel port download cable, BitBlaster serial download cable. Programming devices after they placed board eliminates lead damage high-pin-count packages (e.g., packages) device handling. 3000A devices reprogrammed after system already shipped field. example, product upgrades performed field software modem. STAPL programming test language used program 3000A devices with in-circuit testers, PCs, embedded processors.
more information using STAPL programming test language, Application Note (Using Language Embedded Processor), Application Note (Using STAPL Embedded Processor) (Embedded Programming Using 8051 Byte-Code). circuitry 3000A devices compliant with IEEE Std. 1532 specification. IEEE Std. 1532 standard developed allow concurrent between multiple vendors.
Programming with External Hardware
3000A devices programmed Windows-based with Altera Logic Programmer card, MPU, appropriate device adapter. performs continuity checking ensure adequate electrical contact between adapter device. more information, Altera Programming Hardware Data Sheet. Altera software text- waveform-format test vectors created with Altera Text Editor Waveform Editor test programmed device. added design verification, designers perform functional testing compare functional device behavior with results simulation. Data I/O, Microsystems, other programming hardware manufacturers also provide programming support Altera devices.
more information, Programming Hardware Manufacturers.
Altera Corporation
3000A Programmable Logic Device Family
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
3000A devices include JTAG circuitry defined IEEE Std. 1149.1-1990. Table describes JTAG instructions supported 3000A devices. pin-out tables found Altera site (http://www.altera.com) Altera Digital Library show location JTAG control pins each device. JTAG interface required, JTAG pins available user pins.
Table 3000A JTAG Instructions JTAG Instruction
SAMPLE/PRELOAD EXTEST BYPASS
Description
Allows snapshot signals device pins captured examined during normal device operation, permits initial data pattern output device pins Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins Places 1-bit bypass register between pins, which allows data pass synchronously through selected device adjacent devices during normal device operation Selects IDCODE register places between pins, allowing IDCODE serially shifted Selects 32-bit USERCODE register places between pins, allowing USERCODE value shifted These instructions used when programming 3000A devices JTAG ports with MasterBlaster, ByteBlasterMV, BitBlaster cable, when using STAPL file, file, file embedded processor test equipment
IDCODE USERCODE Instructions
instruction register length 3000A devices bits. IDCODE USERCODE register length bits. Tables show boundary-scan register length device IDCODE information 3000A devices.
Altera Corporation
3000A Programmable Logic Device Family
Table 3000A Boundary-Scan Register Length Device
EPM3032A EPM3064A EPM3128A EPM3256A
Boundary-Scan Register Length
Table 32-Bit 3000A Device IDCODE Value Device Version Bits)
EPM3032A EPM3064A EPM3128A EPM3256A Notes:
Note
IDCODE bits) Part Number Bits)
0111 0000 0011 0010 0111 0000 0110 0100 0111 0001 0010 1000 0111 0010 0101 0110
Manufacturer's Bit) Identity Bits)
00001101110 00001101110 00001101110 00001101110
0001 0001 0001 0001
most significant (MSB) left. least significant (LSB) JTAG IDCODEs
Application Note (IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) more information JTAG BST.
Altera Corporation
3000A Programmable Logic Device Family
Figure shows timing information JTAG signals. Figure 3000A JTAG Waveforms
tJPZX tJSSU Signal Captured Signal Driven tJSH JPCO JPXZ JPSU
tJSZX
tJSCO
tJSXZ
Table shows JTAG timing parameters values 3000A devices. Table JTAG Timing Parameters Values 3000A Devices Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output Update register high impedance valid output Update register valid output high impedance
Parameter
Unit
Altera Corporation
3000A Programmable Logic Device Family
Programmable Speed/Power Control
3000A devices offer power-saving mode that supports low-power operation across user-defined signal paths entire device. This feature allows total power dissipation reduced more because most logic applications require only small fraction gates operate maximum frequency. designer program each individual macrocell 3000A device either high-speed low-power operation. result, speed-critical paths design high speed, while remaining paths operate reduced power. Macrocells that power incur nominal timing delay adder (tLPA) tLAD, tLAC, tIC, tACL, tEN, tCPPW tSEXP parameters.
Output Configuration
3000A device outputs programmed meet variety system-level requirements.
MultiVolt Interface
3000A device architecture supports MultiVolt interface feature, which allows 3000A devices connect systems with differing supply voltages. 3000A devices packages 2.5-V, 3.3-V, 5.0-V operation. These devices have pins internal operation input buffers (VCCINT), another output drivers (VCCIO). VCCIO pins connected either 3.3-V 2.5-V power supply, depending output requirements. When VCCIO pins connected 2.5-V power supply, output levels compatible with 2.5-V systems. When VCCIO pins connected 3.3-V power supply, output high therefore compatible with 3.3-V 5.0-V systems. Devices operating with VCCIO levels lower than incur nominally greater timing delay tOD2 instead tOD1. Inputs always driven 2.5-V, 3.3-V, 5.0-V signals. Table summarizes 3000A MultiVolt support. Table 3000A MultiVolt Support VCCIO Voltage
Note:
When VCCIO 3000A device drive 2.5-V device that 3.3-V tolerant inputs.
Input Signal
Output Signal
Altera Corporation
3000A Programmable Logic Device Family
Open-Drain Output Option
3000A devices provide optional open-drain (equivalent open-collector) output each pin. This open-drain output enables device provide system-level control signals (e.g., interrupt write enable signals) that asserted several devices. also provide additional wired-OR plane. Open-drain output pins 3000A devices (with pull-up resistor 5.0-V supply) drive 5.0-V CMOS input pins that require high VIH. When open-drain active, will drive low. When inactive, resistor will pull trace thereby meeting CMOS requirements. open-drain will only drive tri-state; will never drive high. rise time dependent value pull-up resistor load impedance. current specification should considered when selecting pull-up resistor
Slew-Rate Control
output buffer each 3000A adjustable output slew rate that configured low-noise high-speed performance. faster slew rate provides high-speed transitions high-performance systems. However, these fast transitions introduce noise transients into system. slow slew rate reduces system noise, adds nominal delay When configuration cell turned off, slew rate low-noise performance. Each individual EEPROM that controls slew rate, allowing designers specify slew rate pin-by-pin basis. slew rate control affects both rising falling edges output signal.
Design Security
3000A devices contain programmable security that controls access data programmed into device. When this programmed, design implemented device cannot copied retrieved. This feature provides high level design security because programmed data within EEPROM cells invisible. security that controls this function, well other programmed data, reset only when device reprogrammed. 3000A devices fully tested. Complete testing each programmable EEPROM internal logic elements ensures 100% programming yield. test measurements taken under conditions equivalent those shown Figure Test patterns used then erased during early stages production flow.
Generic Testing
Altera Corporation
3000A Programmable Logic Device Family
Figure 3000A Test Conditions
Power supply transients affect measurements. Simultaneous transitions multiple outputs should avoided accurate measurement. Threshold tests must performed under conditions. Large-amplitude, fast- ground-current transients normally occur device outputs discharge load capacitances. When these transients flow through parasitic inductance between device ground test system ground, significant reductions observable noise immunity result. Numbers brackets 2.5-V outputs. Numbers without brackets 3.3-V devices outputs.
[521 Device Output
Test System
[481 Device input rise fall times
(includes capacitance)
Operating Conditions
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, capacitance 3000A devices. Note
-0.5 -2.0 bias Under bias PQFP TQFP packages, under bias
Table 3000A Device Absolute Maximum Ratings Symbol
IOUT TSTG
Parameter
Supply voltage input voltage output current, Storage temperature Ambient temperature Junction temperature
Conditions
With respect ground
5.75
Unit
Altera Corporation
3000A Programmable Logic Device Family
Table 3000A Device Recommended Operating Conditions Symbol
VCCINT VCCIO
Parameter
Supply voltage internal logic input buffers Supply voltage output drivers, 3.3-V operation Supply voltage output drivers, 2.5-V operation
Conditions
5.75 VCCIO
Unit
VCCISP
Supply voltage during Input voltage Output voltage Ambient temperature Junction temperature Input rise time Input fall time commercial commercial
-0.5
Table 3000A Device Operating Conditions Symbol
Note
-0.5
Parameter
High-level input voltage Low-level input voltage 3.3-V high-level output voltage 3.3-V high-level CMOS output voltage 2.5-V high-level output voltage
Conditions
5.75
Unit
VCCIO 3.00 -0.1 VCCIO 3.00 -100 VCCIO 2.30 VCCIO 2.30 VCCIO 2.30
VCCIO
3.3-V low-level output voltage VCCIO 3.00 3.3-V low-level CMOS output voltage 2.5-V low-level output voltage VCCIO 3.00 VCCIO 2.30 VCCIO 2.30 VCCIO 2.30
Input leakage current Tri-state output off-state current Value pull-up resistor when programming in-system during power-up
VCCINT ground VCCINT ground
Altera Corporation
3000A Programmable Logic Device Family
Table 3000A Device Capacitance Symbol
CI/O
Note Conditions
Parameter
Input capacitance capacitance
Unit
VOUT
Notes tables:
Operating Requirements Altera Devices Data Sheet. Minimum input voltage -0.5 During transitions, inputs undershoot -2.0 overshoot 5.75 input currents less than periods shorter than pins, including dedicated inputs, pins, JTAG pins, driven before VCCINT VCCIO powered. These values specified under recommended operating conditions, shown Table page parameter measured with outputs each sourcing specified current. parameter refers high-level CMOS output current. parameter measured with outputs each sinking specified current. parameter refers low-level TTL, PCI, CMOS output current. This pull-up exists while devices programmed in-system unprogrammed devices during power-up. Capacitance measured sample-tested only. (high-voltage during programming) maximum capacitance time MAX3000A devices does exceed
Figure shows typical output drive characteristics 3000A devices.
Altera Corporation
3000A Programmable Logic Device Family
Figure Output Drive Characteristics 3000A Devices
Typical Output Current (mA)
VCCINT VCCIO Temperature
Output Voltage
Typical Output Current (mA)
VCCINT VCCIO Temperature
Output Voltage
Power Sequencing Hot-Socketing
Because 3000A devices used mixed-voltage environment, they have been designed specifically tolerate possible power-up sequence. VCCIO VCCINT power planes powered order. Signals driven into 3000A devices before during power-up without damaging device. addition, 3000A devices drive during power-up. Once operating conditions reached, 3000A devices operate specified user.
Altera Corporation
3000A Programmable Logic Device Family
Timing Model
3000A device timing analyzed with Altera software, with variety popular industry-standard simulators timing analyzers, with timing model shown Figure 3000A devices have predictable internal delays that enable designer determine worst-case timing design. software provides timing simulation, point-to-point delay prediction, detailed timing analysis device-wide performance evaluation.
Figure 3000A Timing Model
Internal Output Enable Delay Input Delay Delay Global Control Delay GLOB Logic Array Delay Register Control Delay Shared Expander Delay SEXP
Parallel Expander Delay PEXP
Register Delay COMB
Output Delay Delay
timing characteristics signal path derived from timing model parameters particular device. External timing parameters, which represent pin-to-pin timing delays, calculated internal parameters. Figure shows timing relationship between internal external delay parameters.
Altera Corporation
3000A Programmable Logic Device Family
Figure 3000A Switching Waveforms
Inputs driven logic high logic low. timing characteristics measured
Combinatorial Mode
Input
tPIA
Delay
tSEXP
Shared Expander Delay
tLAC tLAD
Logic Array Input
tPEXP
Parallel Expander Delay
tCOMB
Logic Array Output
Output
Global Clock Mode
Global Clock Global Clock Register
tGLOB
Data Enable (Logic Array Output)
Array Clock Mode
Input
tACH
tACL
Clock into Clock into Logic Array Clock Register Data from Logic Array
tPIA
Register Logic Array
tPIA
tCLR tPRE
tPIA
Register Output
Altera Corporation
3000A Programmable Logic Device Family
Tables through show EPM3032A, EPM3064A, EPM3128A, EPM3256A timing information. Table EPM3032A External Timing Parameters Symbol Parameter Conditions
tPD1 tPD2 tCO1 tASU tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input non- registered output input non- registered output Global clock setup time 227.3 227.3 138.9 138.9 103.1
Note Speed Grade
103.1
Unit
Global clock hold time Global clock output delay Global clock high time Global clock time Array clock setup time Array clock hold time Array clock output delay Array clock high time Array clock time Minimum pulse width clear preset
Minimum global clock period Maximum internal (2), global clock frequency Minimum array clock period
Maximum internal (2), array clock frequency
Altera Corporation
3000A Programmable Logic Device Family
Table EPM3032A Internal Timing Parameters (Part Symbol Parameter Conditions
tSEXP tPEXP tLAD tLAC tIOE tOD1 Input buffer delay input buffer delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer delay, slow slew rate VCCIO Output buffer delay, slow slew rate VCCIO Output buffer delay, slow slew rate VCCIO
Note Speed Grade
Unit
tOD2
tOD3
tZX1
Output buffer enable delay, slow slew rate VCCIO Output buffer enable delay, slow slew rate VCCIO Output buffer enable delay, slow slew rate VCCIO Output buffer disable delay Register setup time Register hold time Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time
tZX2
tZX3
10.0
tCOMB tGLOB tPRE
Altera Corporation
3000A Programmable Logic Device Family
Table EPM3032A Internal Timing Parameters (Part Symbol Parameter Conditions
tCLR tPIA tLPA Register clear time delay Low-power adder
Note Speed Grade
Unit
Table EPM3064A External Timing Parameters Symbol Parameter Conditions
Note Speed Grade
222.2 222.2 135.1 135.1 100.0 100.0 10.0
Unit
10.0 10.0 10.0
tPD1 tPD2 tCO1 tASU tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT
Input non-registered output
input non-registered output Global clock setup time Global clock hold time Global clock high time Global clock time Array clock setup time Array clock hold time Array clock output delay Array clock high time Array clock time Minimum pulse width clear preset Minimum global clock period Maximum internal global clock frequency Maximum internal array clock frequency (2),
Global clock output delay
Minimum array clock period (2),
Altera Corporation
3000A Programmable Logic Device Family
Table EPM3064A Internal Timing Parameters (Part Symbol Parameter Conditions
tSEXP tPEXP tLAD tLAC tIOE tOD1 Input buffer delay input buffer delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer delay, slow slew rate VCCIO Output buffer delay, slow slew rate VCCIO Output buffer delay, slow slew rate VCCIO
Note Speed Grade
Unit
tOD2
tOD3
tZX1
Output buffer enable delay, slow slew rate VCCIO Output buffer enable delay, slow slew rate VCCIO Output buffer enable delay, slow slew rate VCCIO Output buffer disable delay Register setup time Register hold time Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time delay
tZX2
tZX3
10.0
tCOMB tGLOB tPRE tCLR tPIA
Altera Corporation
3000A Programmable Logic Device Family
Table EPM3064A Internal Timing Parameters (Part Symbol Parameter Conditions
tLPA Low-power adder
Note Speed Grade
Unit
Table EPM3128A External Timing Parameters Symbol Parameter Conditions
Note Speed Grade
Unit
tPD1 tPD2 tCO1 tASU tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input non- registered output input non- registered output Global clock setup time
10.2 10.2
129.9 129.9
Global clock hold time Global clock output delay Global clock high time Global clock time Array clock setup time Array clock hold time Array clock output delay Array clock high time Array clock time Minimum pulse width clear preset
Minimum global clock period Maximum internal (2), global clock frequency Minimum array clock period 192.3 192.3
98.0
Maximum internal (2), array clock frequency
98.0
Altera Corporation
3000A Programmable Logic Device Family
Table EPM3128A Internal Timing Parameters (Part Symbol Parameter Conditions
tSEXP tPEXP tLAD tLAC tIOE tOD1 Input buffer delay input buffer delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer delay, slow slew rate VCCIO Output buffer delay, slow slew rate VCCIO Output buffer delay, slow slew rate VCCIO
Note Speed Grade
Unit
tOD2
tOD3
tZX1
Output buffer enable delay, slow slew rate VCCIO Output buffer enable delay, slow slew rate VCCIO Output buffer enable delay, slow slew rate VCCIO Output buffer disable delay Register setup time Register hold time Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time
tZX2
tZX3
10.0
tCOMB tGLOB tPRE tCLR
Altera Corporation
3000A Programmable Logic Device Family
Table EPM3128A Internal Timing Parameters (Part Symbol Parameter Conditions
tPIA tLPA delay Low-power adder
Note Speed Grade
Unit
Table EPM3256A External Timing Parameters Symbol Parameter Conditions
Note Speed Grade
Unit
tPD1 tPD2 tCO1 tASU tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input non- registered output input non- registered output Global clock setup time
10.5 10.5
126.6 126.6
Global clock hold time Global clock output delay Global clock high time Global clock time Array clock setup time Array clock hold time Array clock output delay Array clock high time Array clock time Minimum pulse width clear preset
Minimum global clock period Maximum internal (2), global clock frequency Minimum array clock period 172.4 172.4
95.2
Maximum internal (2), array clock frequency
95.2
Altera Corporation
3000A Programmable Logic Device Family
Table EPM3256A Internal Timing Parameters (Part Symbol Parameter Conditions
tSEXP tPEXP tLAD tLAC tIOE tOD1 Input buffer delay input buffer delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer delay, slow slew rate VCCIO Output buffer delay, slow slew rate VCCIO Output buffer delay, slow slew rate VCCIO
Note Speed Grade
Unit
tOD2
tOD3
tZX1
Output buffer enable delay, slow slew rate VCCIO Output buffer enable delay, slow slew rate VCCIO Output buffer enable delay, slow slew rate VCCIO Output buffer disable delay Register setup time Register hold time Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time
tZX2
tZX3
10.0
tCOMB tGLOB tPRE
Altera Corporation
3000A Programmable Logic Device Family
Table EPM3256A Internal Timing Parameters (Part Symbol Parameter Conditions
tCLR tPIA tLPA Register clear time delay Low-power adder
Note Speed Grade
Unit
Notes tables:
These values specified under recommended operating conditions, shown Table page These values specified fan-out macrocells). each additional fan-out these devices, additional timing value. This minimum pulse width preset clear applies both global clear array controls. tLPA parameter must added this minimum width clear reset signal incorporates tLAD parameter into signal path. These parameters measured with 16-bit loadable, enabled, up/down counter programmed into each LAB. tLPA parameter must added tLAD, tLAC, tIC, tEN, tSEXP, tACL, tCPPW parameters macrocells running low-power mode.
Power Consumption
Supply power versus frequency (fMAX, MHz) 3000A devices calculated with following equation: PINT ICCINT value, which depends device output load characteristics switching frequency, calculated using guidelines given Application Note (Evaluating Power Altera Devices). ICCINT value depends switching frequency application logic. ICCINT value calculated with following equation: ICCINT MCTON) (MCDEV MCTON)] MCUSED fMAX togLC) parameters ICCINT equation are:
Altera Corporation
3000A Programmable Logic Device Family
MCTON MCDEV MCUSED fMAX togLC
Number macrocells with Turbo Bitoption turned reported MAX+PLUS Report File (.rpt) Number macrocells device Total number macrocells design, reported File Highest clock frequency device Average percentage logic cells toggling each clock (typically 12.5%) Constants (shown Table
Table 3000A Equation Constants Device
EPM3032A EPM3064A EPM3128A EPM3256A
0.85 0.85 0.85 0.85
0.36 0.36 0.36 0.36
0.017 0.017 0.017 0.017
ICCINT calculation provides estimate based typical conditions using pattern 16-bit, loadable, enabled, up/down counter each with output load. Actual should verified during operation because this measurement sensitive actual pattern device environmental operating conditions.
Altera Corporation
3000A Programmable Logic Device Family
Figures show typical supply current versus frequency 3000A devices. Figure Frequency 3000A Devices
EPM3032A
Room Temperature
Typical Active (mA)
High Speed
227.3
144.9
Non-Turbo
Frequency (MHz)
EPM3064A
Room Temperature
Typical Active (mA)
High Speed
222.2
125.0
Non-Turbo
250°
Frequency (MHz)
Altera Corporation
3000A Programmable Logic Device Family
Figure Frequency 3000A Devices
EPM3128A
Room Temperature
High Speed
192.3
Typical Active (mA)
108.7
Non-Turbo
Frequency (MHz)
EPM3256A
Room Temperature
172.4
Typical Active (mA)
High Speed
102.0
Non-Turbo
Frequency (MHz)
Altera Corporation
3000A Programmable Logic Device Family
Device Pin-Outs
Altera site (http://www.altera.com) Altera Digital Library pin-out information. Figures through show package pin-out diagrams 3000A devices.
Figure 44-Pin PLCC/TQFP Package Pin-Out Diagram
Package outlines drawn scale.
INPUT/OE2/GCLK2 INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/GCLRn
INPUT/GCLK1
INPUT/GCLK1
INPUT/OE1
INPUT/OE1
I/O/TDO I/O/TCK
I/O/TDI I/O/TMS
I/O/TDI I/O/TMS I/O/TDO
EPM3032A EPM3064A
EPM3032A EPM3064A
I/O/TCK
44-Pin PLCC
44-Pin TQFP
Figure 100-Pin TQFP Package Pin-Out Diagram
Package outline drawn scale.
EPM3064A EPM3128A
Altera Corporation
3000A Programmable Logic Device Family
Figure 144-Pin TQFP Package Pin-Out Diagram
Package outline drawn scale.
Indicates location
EPM3128A EPM3256A
Figure 208-Pin PQFP Package Pin-Out Diagram
Package outline drawn scale.
EPM3256A
Altera Corporation
3000A Programmable Logic Device Family
Altera Corporation
3000A Programmable Logic Device Family
Altera Corporation
3000A Programmable Logic Device Family
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Altera, BitBlaster, ByteBlasterMV, Jam, MasterBlaster, MAX, MAX+PLUS MultiVolt, Quartus, Turbo Bit, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: Verilog registered trademark Cadence Design Systems, Inc. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
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Altera Corporation

Programmable Logic Device Family March 2001, ver. Features.

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