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MAX 3000A

Programmable Logic Device Family

MAX 3000A
Programmable Logic Device Family
Data Sheet
March 2001, ver. 2.0
Features..
Table 1. MAX 3000A Device Features Feature
Usable gates Macrocells Logic array blocks Maximum user I / O pins tPD (ns) tSU (ns)
EPM3032A
EPM3064A
EPM3128A
EPM3256A
Altera Corporation
A-DS-M3000A-02.0
MAX 3000A Programmable Logic Device Family Data Sheet
Table 1. MAX 3000A Device Features Feature
tCO1 (ns) fCNT (MHz)
EPM3032A
EPM3064A
EPM3128A
EPM3256A
..and More Features
General Description
MAX 3000A devices are low-cost, high-performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 5, 000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the -4, -5, -6, -7, and -10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 2. MAX 3000A Speed Grades Device -4
EPM3032A EPM3064A EPM3128A EPM3256A Note:
(1) Contact Altera for up-to-date information on the availability of this speed grade.
EPM3032A EPM3064A EPM3128A EPM3256A Notes:
(1) (2) Contact Altera for up-to-date information on available device package options. When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I / O pins become JTAG pins.
Notes (1), (2) 144-Pin TQFP 208-Pin PQFP
44-Pin PLCC
44-Pin TQFP
100-Pin TQFP
MAX 3000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 3000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debugging cycles, and can be programmed and erased up to 100 times.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
f Functional Description
For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet andthe Quartus Programmable Logic Development System & Software Data Sheet. The MAX 3000A architecture includes the following elements:
Logic array blocks (LABs) Macrocells Expander product terms (shareable and parallel) Programmable interconnect array (PIA) I / O control blocks
The MAX 3000A architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I / O pin. Figure 1 shows the architecture of MAX 3000A devices.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 1. MAX 3000A Device Block Diagram
INPUT / GCLK1 INPUT / OE2 / GCLK2 INPUT / OE1
INPUT / GCLRn 6 Output Enables
6 Output Enables
6 to 16 I / O Control Block
Macrocells 1 to 16
Macrocells 17 to 32
I / O Control Block
Macrocells 33 to 48
I / O Control Block
Macrocells 49 to 64
I / O Control Block
Logic Array Blocks
The MAX 3000A device architecture is based on the linking of high-performance LABs. LABs consist of 16-macrocell arrays, as shown in Figure 1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I / O pins, and macrocells. Each LAB is fed by the following signals:
36 signals from the PIA that are used for general logic inputs Global controls that are used for secondary register functions
Macrocells
MAX 3000A macrocells can be individually configured for either sequential or combinatorial logic operation. Macrocells consist of three functional blocks: logic array, product-term select matrix, and programmable register. Figure 2 shows a MAX 3000A macrocell.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 2. MAX 3000A Macrocell
LAB Local Array Global Clear Parallel Logic Expanders (from other macrocells) Global Clocks 2 Programmable Register Register Bypass To I / O Control Block
ProductTerm Select Matrix
Clock / Enable Select
ENA CLRN
Clear Select
Shared Logic Expanders 36 Signals from PIA 16 Expander Product Terms
To PIA
Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells
The Altera development system automatically optimizes product-term allocation according to the logic requirements of the design.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type the Altera development system software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes:
Global clock signal mode, which achieves the fastest clock-to-output performance. Global clock signal enabled by an active-high clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I / O pins.
Two global clock signals are available in MAX 3000A devices. As shown in Figure 1, these global clock signals can be the true or the complement of either of the two global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figure 2, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear from the register are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn).
Expander Product Terms
Although most logic functions can be implemented with the five product terms available in each macrocell, highly complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources. However, the MAX 3000A architecture also offers both shareable and parallel expander product terms ("expanders") that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Shareable Expanders
Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. Shareable expanders incur a small delay (tSEXP). Figure 3 shows how shareable expanders can feed multiple macrocells. Figure 3. MAX 3000A Shareable Expanders
Shareable expanders can be shared by any or all macrocells in an LAB.
Macrocell Product-Term Logic
Product-Term Select Matrix
Macrocell Product-Term Logic
36 Signals from PIA
16 Shared Expanders
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
From Previous Macrocell
Preset Producter Select Matrix Clock Clear
Macrocell ProductTerm Logic
Preset ProductT Term Select Matrix Clock Clear
Macrocell ProductTerm Logic
36 Signals from PIA
16 Shared Expanders
To Next Macrocell
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a programmable path that connects any signal source to any destination on the device. All MAX 3000A dedicated inputs, I / O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device. Only the signals required by each LAB are actually routed from the PIA into the LAB. Figure 5 shows how the PIA signals are routed into the LAB. An EEPROM cell controls one input to a two-input AND gate, which selects a PIA signal to drive into the LAB. Figure 5. MAX 3000A PIA Routing
To LAB
PIA Signals
I / O Control Blocks
The I / O control block allows each I / O pin to be individually configured for input, output, or bidirectional operation. All I / O pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or VCC. Figure 6 shows the I / O control block for MAX 3000A devices. The I / O control block has six global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I / O pins, or a subset of the I / O macrocells.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 6. I / O Control Block of MAX 3000A Devices
6 Global Output Enable Signals
OE Select Multiplexer
To Other I / O Pins From Macrocell
Open-Drain Output Slew-Rate Control
To PIA
When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance), and the I / O pin can be used as a dedicated input. When the tri-state buffer control is connected to VCC, the output is enabled. The MAX 3000A architecture provides dual I / O feedback, in which macrocell and pin feedbacks are independent. When an I / O pin is configured as an input, the associated macrocell can be used for buried logic.
In-System Programmability
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
For more information on using the Jam STAPL programming and test language, see Application Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor), Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded Processor) and AN 111 (Embedded Programming Using the 8051 and Jam Byte-Code). The ISP circuitry in MAX 3000A devices is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors.
Programming with External Hardware f
MAX 3000A devices can be programmed on Windows-based PCs with an Altera Logic Programmer card, MPU, and the appropriate device adapter. The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device. For more information, see the Altera Programming Hardware Data Sheet. The Altera software can use text- or waveform-format test vectors created with the Altera Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional device behavior with the results of simulation. Data I / O, BP Microsystems, and other programming hardware manufacturers also provide programming support for Altera devices.
For more information, see Programming Hardware Manufacturers.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
MAX 3000A devices include the JTAG BST circuitry defined by IEEE Std. 1149.1-1990. Table 4 describes the JTAG instructions supported by MAX 3000A devices. The pin-out tables found on the Altera web site (http://www.altera.com) or the Altera Digital Library show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I / O pins.
Table 4. MAX 3000A JTAG Instructions JTAG Instruction
SAMPLE / PRELOAD EXTEST BYPASS
Description
Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation Selects the IDCODE register and places it between the TDI and TDO pins, allowing the IDCODE to be serially shifted out of TDO Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE value to be shifted out of TDO These instructions are used when programming MAX 3000A devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL file, JBC file, or SVF file via an embedded processor or test equipment
IDCODE USERCODE ISP Instructions
The instruction register length of MAX 3000A devices is 10 bits. The IDCODE and USERCODE register length is 32 bits. Tables 5 and 6 show the boundary-scan register length and device IDCODE information for MAX 3000A devices.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 5. MAX 3000A Boundary-Scan Register Length Device
EPM3032A EPM3064A EPM3128A EPM3256A
Boundary-Scan Register Length
Table 6. 32-Bit MAX 3000A Device IDCODE Value Device Version (4 Bits)
EPM3032A EPM3064A EPM3128A EPM3256A Notes:
Note (1)
IDCODE (32 bits) Part Number (16 Bits)
The most significant bit (MSB) is on the left. The least significant bit (LSB) for all JTAG IDCODEs is 1.
See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) for more information on JTAG BST.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 7 shows the timing information for the JTAG signals. Figure 7. MAX 3000A JTAG Waveforms
TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH
tJSZX
tJSCO
tJSXZ
Table 7 shows the JTAG timing parameters and values for MAX 3000A devices. Table 7. JTAG Timing Parameters & Values for MAX 3000A Devices Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance 20 45 25 25 25
Parameter
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Programmable Speed / Power Control
Output Configuration
MAX 3000A device outputs can be programmed to meet a variety of system-level requirements.
MultiVolt I / O Interface
The MAX 3000A device architecture supports the MultiVolt I / O interface feature, which allows MAX 3000A devices to connect to systems with differing supply voltages. MAX 3000A devices in all packages can be set for 2.5-V, 3.3-V, or 5.0-V I / O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I / O output drivers (VCCIO). The VCCIO pins can be connected to either a 3.3-V or 2.5-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 2.5-V power supply, the output levels are compatible with 2.5-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels lower than 3.0 V incur a nominally greater timing delay of tOD2 instead of tOD1. Inputs can always be driven by 2.5-V, 3.3-V, or 5.0-V signals. Table 8 summarizes the MAX 3000A MultiVolt I / O support. Table 8. MAX 3000A MultiVolt I / O Support VCCIO Voltage 2.5
2.5 3.3 Note:
(1) When VCCIO is 3.3 V, a MAX 3000A device can drive a 2.5-V device that has 3.3-V tolerant inputs.
Input Signal (V) 3.3 v v 5.0 v v v v
Output Signal (V) 2.5 v v v v 3.3 5.0
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Open-Drain Output Option
MAX 3000A devices provide an optional open-drain (equivalent to open-collector) output for each I / O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-OR plane. Open-drain output pins on MAX 3000A devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high VIH. When the open-drain pin is active, it will drive low. When the pin is inactive, the resistor will pull up the trace to 5.0 V, thereby meeting CMOS requirements. The open-drain pin will only drive low or tri-state it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The IOL current specification should be considered when selecting a pull-up resistor
Slew-Rate Control
The output buffer for each MAX 3000A I / O pin has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. When the configuration cell is turned off, the slew rate is set for low-noise performance. Each I / O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. The slew rate control affects both the rising and falling edges of the output signal.
Design Security
Generic Testing
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 8. MAX 3000A AC Test Conditions
Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast- ground-current transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Numbers in brackets are for 2.5-V outputs. Numbers without brackets are for 3.3-V devices or outputs.
VCC 703 521 Device Output
To Test System
C1 (includes jig capacitance)
Operating Conditions
Tables 9 through 12 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for MAX 3000A devices. Note (1) Min
-0.5 -2.0 -25 No bias Under bias PQFP and TQFP packages, under bias -65 -65
Table 9. MAX 3000A Device Absolute Maximum Ratings Symbol
VCC VI IOUT TSTG TA TJ
Parameter
Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature
Conditions
With respect to ground (2)
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 10. MAX 3000A Device Recommended Operating Conditions Symbol
VCCINT VCCIO
Parameter
Supply voltage for internal logic and (9) input buffers Supply voltage for output drivers, 3.3-V operation Supply voltage for output drivers, 2.5-V operation
Conditions
3.6 3.6 2.7 3.6 5.75 VCCIO 70 90 40 40
VCCISP VI VO TA TJ tR tF
Supply voltage during ISP Input voltage Output voltage Ambient temperature Junction temperature Input rise time Input fall time For commercial use For commercial use (3)
Table 11. MAX 3000A Device DC Operating Conditions Symbol
VIH VIL VOH
Note (4) Min
Parameter
High-level input voltage Low-level input voltage 3.3-V high-level TTL output voltage 3.3-V high-level CMOS output voltage 2.5-V high-level output voltage
Conditions
2.4 VCCIO - 0.2 2.1 2.0 1.7 0.4 0.2 0.2 0.4 0.7 -10 -10 20 10 10 74
Input leakage current Tri-state output off-state current Value of I / O pin pull-up resistor when programming in-system or during power-up
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 12. MAX 3000A Device Capacitance Symbol
Note (8) Conditions Min Max
Parameter
Input pin capacitance I / O pin capacitance
Notes to tables:
Figure 9 shows the typical output drive characteristics of MAX 3000A devices.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 9. Output Drive Characteristics of MAX 3000A Devices
Typical IO Output Current (mA)
VO Output Voltage (V)
Typical IO Output Current (mA)
VO Output Voltage (V)
Power Sequencing & Hot-Socketing
Because MAX 3000A devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. The VCCIO and VCCINT power planes can be powered in any order. Signals can be driven into MAX 3000A devices before and during power-up without damaging the device. In addition, MAX 3000A devices do not drive out during power-up. Once operating conditions are reached, MAX 3000A devices operate as specified by the user.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Timing Model
MAX 3000A device timing can be analyzed with the Altera software, with a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 10. MAX 3000A devices have predictable internal delays that enable the designer to determine the worst-case timing of any design. The software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation.
Figure 10. MAX 3000A Timing Model
Internal Output Enable Delay t IOE Input Delay t IN PIA Delay t PIA Global Control Delay t GLOB Logic Array Delay t LAD Register Control Delay t LAC tIC t EN Shared Expander Delay t SEXP
Parallel Expander Delay t PEXP
Register Delay t SU tH t PRE t CLR t RD t COMB
The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. Figure 11 shows the timing relationship between internal and external delay parameters.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 11. MAX 3000A Switching Waveforms
Combinatorial Mode
Input Pin
PIA Delay
tSEXP
Shared Expander Delay
tLAC , tLAD
Logic Array Input
tPEXP
Parallel Expander Delay
tCOMB
Logic Array Output
Output Pin
Global Clock Mode
Global Clock Pin Global Clock at Register
tR tIN
tCH tGLOB tH
Data or Enable (Logic Array Output)
Array Clock Mode
Input or I / O Pin
tACH tIN tIO
Clock into PIA Clock into Logic Array Clock at Register Data from Logic Array
tIC tSU tH
Register to PIA to Logic Array
tPIA tOD
tCLR , tPRE tOD
Register Output to Pin
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Tables 13 through 20 show EPM3032A, EPM3064A, EPM3128A, and EPM3256A timing information. Table 13. EPM3032A External Timing Parameters Symbol Parameter Conditions -4 Min
Note (1) Speed Grade -7 Max
Unit -10
10 10 ns ns ns ns 6.7 ns ns ns ns ns 9.4 ns ns ns ns 9.7 ns MHz ns MHz
Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2)
Maximum internal (2), (4) array clock frequency
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 14. EPM3032A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -4 Min
Note (1) Speed Grade -7 Max
Unit -10
1.5 1.5 4.0 1.0 3.3 1.2 0.0 1.8 ns ns ns ns ns ns ns ns
tXZ tSU tH tRD tCOMB tIC tEN tGLOB tPRE
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 14. EPM3032A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -4 Min
tCLR tPIA tLPA Register clear time PIA delay Low-power adder (2) (5)
Note (1) Speed Grade -7 Max
Unit -10
2.6 2.1 5.0 ns ns ns
Table 15. EPM3064A External Timing Parameters Symbol Parameter Conditions
Note (1) Speed Grade -4 Min Max
Unit -10
-7 Min Max
10.0 10.0 ns ns ns ns 7.0 ns ns ns ns ns 9.6 ns ns ns ns 10.0 ns MHz ns MHz
tPD1 tPD2 tSU tH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT
Input to non-registered output
Minimum array clock period (2) (2), (4)
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 16. EPM3064A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -4 Min
Note (1) Speed Grade -7 Max
Unit -10
1.4 1.4 3.9 0.9 3.2 1.2 0.0 1.8 ns ns ns ns ns ns ns ns
tXZ tSU tH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 16. EPM3064A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -4 Min
tLPA Low-power adder (5)
Note (1) Speed Grade -7 Max
Unit -10
5.0 ns
Table 17. EPM3128A External Timing Parameters Symbol Parameter Conditions
Note (1) Speed Grade -5 -7 Max
Unit -10
10 10 ns ns ns ns 6.6 ns ns ns ns ns 9.4 ns ns ns ns 10.2 ns MHz 10.2 ns MHz
Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2) 192.3 192.3
Maximum internal (2), (4) array clock frequency
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 18. EPM3128A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -5 Min
Note (1) Speed Grade -7 Max
Unit -10
1.4 1.4 3.8 0.9 3.1 1.3 0.0 1.6 ns ns ns ns ns ns ns ns
tXZ tSU tH tRD tCOMB tIC tEN tGLOB tPRE tCLR
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 18. EPM3128A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -5 Min
tPIA tLPA PIA delay Low-power adder (2) (5)
Note (1) Speed Grade -7 Max
Unit -10
2.6 5.0 ns ns
Table 19. EPM3256A External Timing Parameters Symbol Parameter Conditions
Note (1) Speed Grade -5 -7 Max
Unit -10
10 10 ns ns ns ns 6.4 ns ns ns ns ns 9.7 ns ns ns ns 10.5 ns MHz 10.5 ns MHz
Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2) 172.4 172.4
Maximum internal (2), (4) array clock frequency
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 20. EPM3256A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -5 Min
Note (1) Speed Grade -7 Max
Unit -10
1.2 1.2 3.7 0.6 2.8 1.3 0.0 1.6 ns ns ns ns ns ns ns ns
tXZ tSU tH tRD tCOMB tIC tEN tGLOB tPRE
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Table 20. EPM3256A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -5 Min
tCLR tPIA tLPA Register clear time PIA delay Low-power adder (2) (5)
Note (1) Speed Grade -7 Max
Unit -10
3.0 3.2 5.0 ns ns ns
Notes to tables:
(1) (2) (3) These values are specified under the recommended operating conditions, as shown in Table 10 on page 19. These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. These parameters are measured with a 16-bit loadable, enabled, up / down counter programmed into each LAB. The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in low-power mode.
Power Consumption
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
MCTON MCDEV MCUSED fMAX togLC A, B, C
Table 21. MAX 3000A ICC Equation Constants Device
EPM3032A EPM3064A EPM3128A EPM3256A
The ICCINT calculation provides an ICC estimate based on typical conditions using a pattern of a 16-bit, loadable, enabled, up / down counter in each LAB with no output load. Actual ICC should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions.
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figures 12 and 13 show the typical supply current versus frequency for MAX 3000A devices. Figure 12. ICC vs. Frequency for MAX 3000A Devices
EPM3032A
Typical ICC Active (mA) 40
High Speed
227.3 MHz
144.9 MHz
Non-Turbo
Frequency (MHz)
EPM3064A
Typical ICC Active (mA) 80
High Speed
222.2 MHz
125.0 MHz
Non-Turbo
Frequency (MHz)
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 13. ICC vs. Frequency for MAX 3000A Devices
EPM3128A
High Speed
192.3 MHz
Typical ICC Active (mA)
108.7 MHz
Non-Turbo
Frequency (MHz)
EPM3256A
172.4 MHz
Typical ICC Active (mA) 200
High Speed
102.0 MHz
Non-Turbo
Frequency (MHz)
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Device Pin-Outs
See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Figures 14 through 17 show the package pin-out diagrams for MAX 3000A devices.
Figure 14. 44-Pin PLCC / TQFP Package Pin-Out Diagram
Package outlines not drawn to scale.
INPUT / OE2 / GCLK2 INPUT / OE2 / GCLK2
INPUT / GCLRn
INPUT / GCLK1
INPUT / OE1
Pin 34
EPM3032A EPM3064A
Pin 12
Pin 23
44-Pin PLCC
44-Pin TQFP
Figure 15. 100-Pin TQFP Package Pin-Out Diagram
Package outline not drawn to scale.
Pin 1 Pin 76
EPM3064A EPM3128A
Pin 26
Pin 51
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 16. 144-Pin TQFP Package Pin-Out Diagram
Package outline not drawn to scale.
Indicates location of Pin 1
Pin 109
EPM3128A EPM3256A
Pin 37
Pin 73
Figure 17. 208-Pin PQFP Package Pin-Out Diagram
Package outline not drawn to scale.
Pin 1 Pin 157
EPM3256A
Pin 53
Pin 105
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Printed on Recycled Paper.
Altera Corporation