8K-Bit Microwire Serial EEPROM FEATURES High speed operation: 3MH

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8K-Bit Microwire Serial EEPROM FEATURES High speed operation: 3MH

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CAT93C76 (Rev.
8K-Bit Microwire Serial EEPROM FEATURES
High speed operation: 3MHz power CMOS technology volt operation Selectable memory organization Self-timed write cycle with auto-clear Software write protection
E
2.5V
Power-up inadvertant write protection 1,000,000 Program/erase cycles year data retention Industrial extended temperature ranges Sequential read "Green" package option available
DESCRIPTION
CAT93C76 8K-bit Serial EEPROM memory device which configured either registers bits (ORG Connected) bits (ORG GND). Each register written read) serially using pin. CAT93C76 manufactured using Catalyst's advanced CMOS EEPROM floating gate technology. device designed endure 1,000,000 program/erase cycles data retention years. device available 8-pin DIP, SOIC, TSSOP 8-pad TDFN packages.
CONFIGURATION
Package
FUNCTIONAL SYMBOL
SOIC Package
TSSOP Package (U,Y)
FUNCTIONS
Name Function Chip Select Serial Clock Input Serial Data Input Serial Data Output +1.8 5.5V Power Supply Ground Memory Organization Connection
TDFN Package (RD4, ZD4)
View
Note: When connected VCC, organization selected. When connected ground, organization selected. left unconnected, then internal pull-up device will select organization.
2004 Catalyst Semiconductor, Inc. Characteristics subject change without notice.
Doc. 1090, Rev.
CAT93C76 ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage with Respect Ground(1) -2.0V +VCC +2.0V with Respect Ground -2.0V +7.0V Lead Soldering Temperature secs) 300°C Output Short Circuit Current(2)
*COMMENT
Stresses exceeding those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability.
RELIABILITY CHARACTERISTICS
Symbol NEND(3) TDR(3) VZAP(3) ILTH(3)(4) Parameter Endurance Data Retention Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 1,000,000 2000 Units Cycles/Byte Years Volts
D.C. OPERATING CHARACTERISTICS +1.8V +5.5V, unless otherwise specified.
Symbol ICC1 ICC2 ISB1 ISB2 ILORG VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current Leakage Current Input Voltage Input High Voltage Input Voltage Input High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Test Conditions 1MHz 5.0V 1MHz 5.0V ORG=GND CS=0V ORG=Float VOUT VCC, 4.5V 5.5V 4.5V 5.5V 1.8V 4.5V 1.8V 4.5V 4.5V 5.5V 2.1mA 4.5V 5.5V -400µA 1.8V 4.5V 100µA 1.8V 4.5V -100µA -0.1 0(5) 0(5) 0(5) VCC+1 Units
Note: minimum input voltage -0.5V. During transitions, inputs undershoot -2.0V periods less than Maximum voltage output pins +0.5V, which overshoot +2.0V periods less than Output shorted more than second. These parameters tested initially after design process change that affects parameter. Latch-up protection provided stresses pins from +1V. defined less than
Doc. 1090, Rev.
CAT93C76
CAPACITANCE Symbol COUT
Test Output Capacitance (DO) Input Capacitance (CS, ORG)
Conditions VOUT=0V VIN=0V
Units
CIN(1)
INSTRUCTION SET(2) Address Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Start Opcode A10-A0 A10-A0 A10-A0 A9-A0 A9-A0 A9-A0 D7-D0 Data Comments Read Address Clear Address D15-D0 Write Address Write Enable Write Disable Clear Addresses D7-D0 D15-D0 Write Addresses
11XXXXXXXXX 11XXXXXXXX 00XXXXXXXXX 00XXXXXXXX 10XXXXXXXXX 10XXXXXXXX 01XXXXXXXXX 01XXXXXXXX
A.C. CHARACTERISTICS Limits 1.8V-2.5V Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tCSMIN tSKHI tSKLOW SKMAX Parameter Setup Time Hold Time Setup Time Hold Time Output Delay Output Delay Output Delay High-Z Program/Erase Pulse Width Minimum Time Minimum High Time Minimum Time Output Delay Status Valid Maximum Clock Frequency 1000 100pF Test Conditions 3000 2.5V-5.5V Units
NOTE: These parameters tested initially after design process change that affects parameter. Address 1,024x8 org. 512x16 org. "don't care" bits, must kept either READ, WRITE ERASE commands. input levels timing reference points shown Test Conditions" table.
Doc. 1090, Rev.
CAT93C76
POWER-UP TIMING (1)(2) Symbol tPUR tPUW Parameter Power-up Read Operation Power-up Write Operation Units
A.C. TEST CONDITIONS Input Rise Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages
50ns 0.4V 2.4V 0.8V, 2.0V 0.2VCC 0.7VCC 0.5VCC
4.5V 5.5V 4.5V 5.5V 1.8V 4.5V 1.8V 4.5V
NOTE: These parameters tested initially after design process change that affects parameter. tPUR tPUW delays required from time stable until specified operation initiated.
DEVICE OPERATION
CAT93C76 8192-bit nonvolatile memory intended with industry standard microprocessors. CAT93C76 organized either registers bits bits. When organized X16, seven 13-bit instructions control read, write erase operations device. When organized seven 14-bit instructions control read, write erase operations device. CAT93C76 operates single power supply will generate chip, high voltage required during write operation. Instructions, addresses, write data clocked into rising edge clock (SK). normally high impedance state except when reading data from device, when checking ready/busy status after write operation. ready/busy status determined after start write operation selecting device high) polling pin; indicates that write operation completed, while high indicates that device ready next instruction. necessary, placed back into high impedance state during chip select shifting dummy into pin. will enter high impedance state falling edge clock (SK). Placing into high impedance state recommended applications where tied together form common DI/O pin. format instructions sent device logical start bit, 2-bit 4-bit) opcode, 10-bit address additional when organized write operations 16-bit data field (8-bit organizations). most significant address "don't care" must present.
Read Upon receiving READ command address (clocked into pin), CAT93C76 will come high impedance state and, after sending initial dummy zero bit, will begin shifting data addressed (MSB first). output data bits will toggle rising edge clock stable after specified time delay (tPD0 tPD1). CAT93C76, after initial data word been shifted remains asserted with clock continuing toggle, device will automatically increment next address shift next data word sequential READ mode. long continuously asserted continues toggle, device will keep incrementing next address automatically until reaches address space, then loops back address sequential READ mode, only initial data word preceeded dummy zero bit. subsequent data words will follow without dummy zero bit. Write After receiving WRITE command, address data, (Chip Select) must deselected minimum tCSMIN. falling edge will start self clocking clear data store cycle memory location specified instruction. clocking necessary after device entered self clocking mode. ready/busy status CAT93C76 determined selecting device polling pin. Since this device features AutoClear before write, necessary erase memory location before written into.
Doc. 1090, Rev.
CAT93C76
Figure Sychronous Data Timing
tSKHI tDIS tCSS tDIS tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW
Figure Read Instruction Timing
Don't Care AN-1
HIGH-Z
Dummy
Address
Address
Address
Figure Write Instruction Timing
tCSMIN HIGH-Z BUSY READY HIGH-Z AN-1 STATUS VERIFY STANDBY
Doc. 1090, Rev.
CAT93C76
Erase Upon receiving ERASE command address, (Chip Select) must deasserted minimum tCSMIN. falling edge will start self clocking clear cycle selected memory location. clocking necessary after device entered self clocking mode. ready/busy status CAT93C76 determined selecting device polling pin. Once cleared, content cleared location returns logical state. Erase/Write Enable Disable CAT93C76 powers write disable state. writing after power-up after EWDS (write disable) instruction must first preceded EWEN (write enable) instruction. Once write instruction enabled, will remain enabled until power device removed, EWDS instruction sent. EWDS instruction used disable CAT93C76 write clear instructions, will prevent accidental writing clearing device. Data read normally from device regardless write enable/disable status. Erase Upon receiving ERAL command, (Chip Select) must deselected minimum tCSMIN. falling edge will start self clocking clear cycle memory locations device. clocking necessary after device entered self clocking mode. ready/busy status CAT93C76 determined selecting device polling pin. Once cleared, contents memory bits return logical state. Write Upon receiving WRAL command data, (Chip Select) must deselected minimum tCSMIN. falling edge will start self clocking data write memory locations device. clocking necessary after device entered self clocking mode. ready/busy status CAT93C76 determined selecting device polling pin. necessary memory locations cleared before WRAL command executed. Note After last data been sampled, Chip Select (CS) must brought before next rising edge clock (SK) order start self-timed high voltage cycle. This important because brought before after this specific frame window, addressed location will programmed erased. Power-On Reset (POR) CAT93C76 incorporates Power-On Reset (POR) circuitry which protects device against malfunctioning while lower than recommended operating voltage. device will power into read-only state will power-down into reset state when crosses level ~1.3
Figure Erase Instruction Timing
HIGH-Z AN-1
STATUS VERIFY
STANDBY
BUSY READY HIGH-Z
Doc. 1090, Rev.
CAT93C76
Figure EWEN/EWDS Instruction Timing
STANDBY
ENABLE=11 DISABLE=00
Figure ERAL Instruction Timing
STATUS VERIFY
STANDBY
BUSY READY HIGH-Z
HIGH-Z
Figure WRAL Instruction Timing
STATUS VERIFY tCSMIN
STANDBY
BUSY READY HIGH-Z
Doc. 1090, Rev.
CAT93C76 ORDERING INFORMATION
Prefix Optional Company Device 93C76 Suffix Temperature Range Industrial (-40°C +85°C) Extended (-40°C +125°C) TE13
Product Number
Tape Reel
Revision Package PDIP SOIC (JEDEC) TSSOP TDFN (3x3mm) PDIP (Lead free, Halogen free) SOIC, JEDEC (Lead free, Halogen free) TSSOP (Lead free, Halogen free) TDFN (3x3mm, Lead free, Halogen free)
Notes: device used above example 93C76SI-TE13 (SOIC, Industrial Temperature, Volt Volt Operating Voltage, Tape Reel) Product revision letter marked package suffix production date code (e.g., AYWWA.) additional information, please contact your Catalyst sales office.
Doc. 1090, Rev.
CAT93C76 REVISION HISTORY
Date 08/11/04 Revision Comments Initial Issue
Doc. 1090, Rev.
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Catalyst Semiconductor been issued U.S. foreign patents patent applications pending that protect products. complete list patents issued Catalyst Semiconductor contact Company's corporate office 408.542.1000.
CATALYST SEMICONDUCTOR MAKES WARRANTY, REPRESENTATION GUARANTEE, EXPRESS IMPLIED, REGARDING SUITABILITY PRODUCTS PARTICULAR PURPOSE, THAT PRODUCTS WILL INFRINGE INTELLECTUAL PROPERTY RIGHTS RIGHTS THIRD PARTIES WITH RESPECT PARTICULAR APPLICATION SPECIFICALLY DISCLAIMS LIABILITY ARISING SUCH APPLICATION, INCLUDING LIMITED CONSEQUENTIAL INCIDENTAL DAMAGES.
Catalyst Semiconductor products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Catalyst Semiconductor product could create situation where personal injury death occur. Catalyst Semiconductor reserves right make changes discontinue product service described herein without notice. Products with data sheets labeled "Advance Information" "Preliminary" other products described herein production offered sale. Catalyst Semiconductor advises customers obtain current version relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com
Publication Revison: Issue date:
1090 08/11/04

8K-Bit Microwire Serial EEPROM FEATURES High speed operation: 3MH

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