1-kb Dual Mode Serial EEPROM VESA"Plug-and-Play" FEATURES DDC1TM/

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1-kb Dual Mode Serial EEPROM VESA"Plug-and-Play" FEATURES DDC1TM/

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CAT24C21
1-kb Dual Mode Serial EEPROM VESA"Plug-and-Play" FEATURES
DDC1TM/DDC2interface compliant power CMOS technology 1,000,000 program/erase cycles year data retention
E
monitor identification
compatible* volt operation 16-byte page write buffer Hardware write protect
8-pin DIP, SOIC, TSSOP, MSOP TDFN
packages
Industrial temperature range
DESCRIPTION
CAT24C21 1-kb Serial CMOS EEPROM internally organized words bits each. device complies with Video Electronics Standard Association's (VESATM), Display Data Channel (DDCTM) standards "Plug-and-Play" monitors. "transmitonly" mode (DDC1TM) controlled VCLK clock input "bi-directional" mode (DDC2TM) controlled clock input, with both modes sharing common input/output (I/O). transmit-only mode read-only mode, while bi-directional mode read write mode following protocol. write mode CAT24C21 features 16-byte page write buffer. device available 8-in DIP, SOIC, TSSOP, MSOP TDFN packages.
CONFIGURATION
Package
VCLK
FUNCTIONAL SYMBOL
SOIC Package
VCLK
CAT24C21
MSOP Package
VCLK
TDFN Package (RD4, ZD4)
VCLK
VCLK
View
FUNCTIONS
Name VCLK Function Connect Serial Data/Address Serial Clock (bi-directional mode) Serial Clock (transmit-only mode) Power Supply Ground
TSSOP Package
VCLK
Catalyst Semiconductor licensed Philips Corporation carry Protocol.
2004 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. 1032, Rev.
CAT24C21
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage with Respect Ground(1) -2.0 with Respect Ground -2.0 +7.0 Package Power Dissipation Capability 25°C) Lead Soldering Temperature seconds) 300°C Output Short Circuit Current(2) RELIABILITY CHARACTERISTICS Symbol NEND(3)(*)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability.
Parameter Endurance Data Retention Susceptibility Latch-up
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard
1,000,000 2000
Units Program/Erase Cycles Years Volts
VZAP(3) ILTH(3)(4)
Page Mode, 25°C
D.C. OPERATING CHARACTERISTICS
unless otherwise specified. Industrial temperature range.
Symbol
Parameter Power Supply Current Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Input Voltage (VCLK) Input High Voltage (VCLK)
Test Conditions fSCL VOUT
Units
VOL1
CAPACITANCE 25°C, MHz, Symbol CI/O(3)
Parameter Input/Output Capacitance (SDA) Input Capacitance (VCLK, SCL)
Conditions VI/O
Units
Note: minimum input voltage -0.5 During transitions, inputs undershoot -2.0 periods less than Maximum voltage output pins which overshoot periods less than Output shorted more than second. This parameter tested initially after design process change that affects parameter. Latch-up protection provided stresses pins from Maximum standby current (ISB) 10µA Extended Automotive temperature range.
Doc. 1032, Rev.
CAT24C21
A.C. CHARACTERISTICS
unless otherwise specified. Industrial temperature range.
Symbol
Parameter
Units
Transmit-only Mode TVAA TVHIGH TVLOW TVHZ TVPU Output valid from VCLK VCLK high VCLK Mode transition Transmit-only power-up
Read Write Cycle Limits FSCL TI(1) tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF(1) tSU:STO Clock Frequency Noise Suppression Time Constant SCL, Inputs Data Time Must Free Before Transmission Start Start Condition Hold Time Clock Period Clock High Period Start Condition Setup Time Data Hold Time Data Setup Time Rise Time Fall Time Stop Condition Setup Time Data Hold Time
Power-Up Timing(1)(2) tPUR tPUW Power-up Read Operation Power-up Write Operation
Write Cycle Limits Write Cycle Time
write cycle time time from valid stop condition write sequence internal program/ erase cycle. During write cycle, interface
circuits disabled, allowed remain high, device does respond slave address.
Note: This parameter tested initially after design process change that affects parameter. tPUR tPUW delays required from time stable until specified operation initiated.
Doc. 1032, Rev.
CAT24C21
DESCRIPTION
serial clock input used clock data transfers into device when bi-directional mode. bi-directional serial data/address used transfer data into device. open drain output wire-ORed with other open drain open collector outputs.
TRANSMIT-ONLY MODE: (DDC1)
Upon power-up, CAT24C21 will output valid data only after been initialized. During initialization, data will available until after first nine clocks sent device (Figure starting address transmit-only mode determined during initialization. high during first eight clocks, starting address will 7FH. during first eight clocks, starting address will 00H. During ninth clock, will high impedance state. Data transmitted words with most significant first, followed 'don't care' which will high impedance state (Figure CAT24C21 will continuously sequence through entire memory array long VCLK present falling edges detected. When maximum address (7FH) reached, addressing will wrap around zero location (00H) transmitting will continue. bi-directional mode clock (SCL) must held high device remain transmit-only mode.
FUNCTIONAL DESCRIPTION
CAT24C21 modes operation: transmitonly mode bi-directional mode. There separate 2-wire protocol support each mode, each having separate clock input (VCLK respectively) both modes sharing common bidirectional data line (SDA). CAT24C21 enters transmit-only mode upon power begins outputting data with each clock signal VCLK pin. device will remain transmit-only mode until there valid HIGH transition pin, when will switch bi-directional mode (Figure Once bi-directinal mode, only return transmit-only mode powering down device. VCLK serial clock input used clock data device when transmit-only mode. When held low, bi-directional mode, will inhibit write operations. Figure Mode Transition
Transmit-Only Mode
TVHZ
Bi-Directional Mode
VCLK
Figure Device Initialization Transmit-only Mode
high impedance clock cycles
Bit8 Bit7 Bit6 Bit5 Bit4
VCLK
TVPU
TVAA
Doc. 1032, Rev.
CAT24C21
BI-DIRECTIONAL MODE (DDC2)
following defines features protocol bi-directional mode (Figure Data transfer initiated only when busy. During data transfer, data line must remain stable whenever clock line high. changes data line while clock line high will interpreted START STOP condition. When bi-directional mode, inputs VCLK ignored, except when logic high required enable write capability. START Condition START condition (Figure precedes commands device, defined HIGH transition when HIGH. CAT24C21 monitors lines will respond until this condition met.
STOP Condition HIGH transition when HIGH determines STOP condition. operations must with STOP condition. Device Addressing Master begins transmission sending START condition. Master then sends address particular slave device requesting. four most significant bits 8-bit slave address fixed 1010 CAT24C21 (see Fig. next three significant bits "don't care". last slave address specifies whether Read Write operation performed. When this Read operation selected, when Write operation selected. After Master sends START condition slave address byte, CAT24C21 monitors responds with acknowledge line) when address matches transmitted slave address. CAT24C21 then performs Read Write operation depending state bit.
Figure Transmit-only Mode
must remain high transmit-only mode
Bit8 (MSB) Bit1 (LSB) Don't Care
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit8
Bit7
VCLK
TVHIG
TVLOW
Doc. 1032, Rev.
CAT24C21
Acknowledge After successful data transfer, each receiving device required generate acknowledge (ACK). acknowledging device pulls down line during ninth clock cycle, signaling that received bits data (Figure CAT24C21 responds with after receiving START condition slave address. device been selected along with write operation, responds with after receiving each 8-bit byte. When CAT24C21 READ mode transmits bits data, releases line, monitors line ACK. Once receives this ACK, CAT24C21 will continue transmit data. sent Master, device terminates data transmission waits STOP condition.
Write Operations VCLK must held high order program device. This applies byte write page write operation. Once device self-timed program cycle, VCLK affect programming. Byte Write Byte Write mode (Figure Master device sends START condition slave address information (with zero) Slave device. After Slave generates ACK, Master sends byte address that written into address pointer CAT24C21. After receiving another from Slave, Master device transmits data byte written into addressed memory location. CAT24C21 acknowledges once more Master generates STOP condition, which time device begins internal programming cycle nonvolatile memory (Figure While this internal cycle progress, device will respond request from Master device.
Figure Timing
tLOW tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW
tBUF
Figure Write Cycle Timing
Byte
STOP CONDITION START CONDITION ADDRESS
Doc. 1032, Rev.
CAT24C21
Page Write CAT24C21 writes bytes data single write cycle, using Page Write operation. Page Write operation (Figure initiated same manner Byte Write operation, however instead terminating after initial word transmitted, Master allowed send fifteen additional bytes. After each byte been transmitted CAT24C21 will respond with ACK, internally increment order address bits one. high order bits remain unchanged. Master transmits more than sixteen bytes prior sending STOP condition, address counter `wraps around', previously transmitted data will overwritten.
Once sixteen bytes received STOP condition been sent Master, internal programming cycle begins. this point received data written CAT24C21 single write cycle. Acknowledge Polling disabling inputs used take advantage typical write cycle time. Once stop condition issued indicate host's write operation, CAT24C21 initiates internal write cycle. polling initiated immediately. This involves issuing start condition followed slave address write operation. CAT24C21 still busy with write operation, will returned. CAT24C21 completed write operation, will returned host then proceed with next read write operation.
Figure Start/Stop Timing
START STOP
Figure Acknowledge Timing
FROM MASTER
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure Slave Address Bits
Doc. 1032, Rev.
CAT24C21
Write Protection When VCLK connected CAT24C21 bi-directional mode, entire memory protected becomes "read only". Read Operations READ operation CAT24C21 initiated same manner write operation with exception that one. Three different READ operations possible: Immediate Address READ, Selective READ Sequential READ. Immediate Address Read CAT24C21's address counter contains address last byte accessed, incremented one. other words, last READ WRITE access address READ immediately following would access data from address (Figure 11). 127, then counter will 'wrap around' address continue clock data. Selective Read Selective READ operations allow Master device select random memory location READ operation (Figure 12). Master device first performs `dummy' write operation sending START condition, slave address byte address location wishes read. After CAT24C21 acknowledges word address, Master device resends START condition slave address, this time with one. CAT24C21 then responds with sends 8-bit byte requested. master device does send will generate STOP condition. Sequential Read Sequential READ operation (Figure initiated either Immediate Address READ Selective READ operation. After CAT24C21 sends first 8-bit byte, Master responds with ACK, which tells Slave that more data being requested. CAT24C21 will continue output 8-bit byte each sent Master. entire memory content thus read sequentially. memory reached process, then addressing will 'wrap-around' beginning memory. Data output will stop when Master fails acknowledge sends STOP condition.
Figure Byte Write Timing
ACTIVITY: MASTER LINE
SLAVE ADDRESS
BYTE ADDRESS
DATA
Figure Page Write Timing
ACTIVITY: MASTER LINE
SLAVE ADDRESS
BYTE ADDRESS
DATA
DATA
DATA
nMAX CAT24WC21 Don't care
Doc. 1032, Rev.
CAT24C21
Figure Immediate Address Read Timing
ACTIVITY: MASTER LINE
SLAVE ADDRESS
DATA
DATA STOP
Figure Selective Read Timing
DATA
ACTIVITY: MASTER LINE
SLAVE ADDRESS
BYTE ADDRESS
SLAVE ADDRESS
Figure Sequential Read Timing
ACTIVITY: MASTER LINE SLAVE ADDRESS DATA DATA DATA DATA
Doc. 1032, Rev.
CAT24C21
ORDERING INFORMATION
Prefix Device 24C21 Suffix TE13 B(2)
Optional Company
Product Number
Temperature Range Industrial (-40 Extended (-40
Tape Reel TE13: 2000/Reel
*available upon request
Package PDIP SOIC (JEDEC) TSSOP MSOP RD4: TDFN (3mm 3mm) PDIP (Lead free, Halogen free) SOIC (Lead free, Halogen free) MSOP (Lead free, Halogen free) TSSOP (Lead free, Halogen free) ZD4: TDFN (3mm 3mm, Lead free, Halogen free)
Revision
Notes: device used above example CAT24C21JI-TE13 (SOIC, Industrial Temperature, Volt Volt Operating Voltage, Tape Reel) Product revision letter marked package suffix production date code (e.g., AYWWB). additional information, please contact your Catalyst sales office.
Doc. 1032, Rev.
CAT24C21
REVISION HISTORY
Date 9/29/2003 Rev. Reason Replaced Block Diagram with Functional Symbol Eliminated commercial temperature range Updated marking 10/15/2003 Added TDFN package Updated Descriptions Updated Operating Characteristics Updated Characateristics Updated Byte Write Timing Figure Updated Page Write Timing Figure Updated Immediate Address Read Timing Figure 10/22/2003 Updated Reliability Characteristics Updated D.C. Operating Characteristics Updated Capacitance 10/24/2003 11/12/2003 12/23/2003 7/7/2004 7/27/2004 Formatting Change Corrected Operating Characteristics Corrected Characteristics Changed Industrial temp range from "Blank" Ordering Information Added revision Ordering Information Updated Operating Characteristics table notes
Doc. 1032, Rev.
CAT24C21
Copyrights, Trademarks Patents Trademarks registered trademarks Catalyst Semiconductor include each following:
trademark Philips. DDC, DDC1, DDC2 VESA trademarks Video Electronics Standards Association. Catalyst Semiconductor been issued U.S. foreign patents patent applications pending that protect products. complete list patents issued Catalyst Semiconductor contact Company's corporate office 408.542.1000.
CATALYST SEMICONDUCTOR MAKES WARRANTY, REPRESENTATION GUARANTEE, EXPRESS IMPLIED, REGARDING SUITABILITY PRODUCTS PARTICULAR PURPOSE, THAT PRODUCTS WILL INFRINGE INTELLECTUAL PROPERTY RIGHTS RIGHTS THIRD PARTIES WITH RESPECT PARTICULAR APPLICATION SPECIFICALLY DISCLAIMS LIABILITY ARISING SUCH APPLICATION, INCLUDING LIMITED CONSEQUENTIAL INCIDENTAL DAMAGES.
Catalyst Semiconductor products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Catalyst Semiconductor product could create situation where personal injury death occur. Catalyst Semiconductor reserves right make changes discontinue product service described herein without notice. Products with data sheets labeled "Advance Information" "Preliminary" other products described herein production offered sale. Catalyst Semiconductor advises customers obtain current version relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com
Publication Revison: Issue date:
1032 7/27/04
Doc. 1032, Rev.

1-kb Dual Mode Serial EEPROM VESA"Plug-and-Play" FEATURES DDC1TM/

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