PowerPC® processor core operating 500MHz with 32KB D-caches On-chip SR

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PowerPC® processor core operating 500MHz with 32KB D-caches On-chip SR

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PowerPC 440GP Embedded Processor Data Sheet
PowerPC® processor core operating 500MHz with 32KB D-caches On-chip SRAM Selectable processor:bus clock ratios 3:1, 4:1, 5:1, 5:2, Double Data Rate (DDR) Synchronous DRAM (SDRAM) 32/64-bit interface operating 133MHz External Peripheral eight devices with external mastering support external peripherals, internal UART memory PCI-X V1.0a interface bits, 133MHz) with support conventional V2.2 Programmable Interrupt Controller supports interrupts from variety sources. Programmable General Purpose Timers (GPT) serial ports (16750 compatible UART) interfaces General Purpose (GPIO) interface available JTAG interface board level testing Internal Processor Local (PLB) runs SDRAM interface frequency Processor boot from memory Available ceramic plastic packages Ethernet 10/100Mbps half- full-duplex interfaces. Operational modes supported MII, RMII, SMII.
Designed specifically address high-end embedded applications, PowerPC 440GP (PPC440GP) provides high-performance, power solution that interfaces wide range peripherals incorporating on-chip power management features lower power dissipation. This chip contains high-performance RISC processor core, SDRAM controller,8KB SRAM, PCI-X interface, Ethernet interfaces, control external peripherals, with scatter-gather support, serial ports, interface, general purpose I/O. Technology: CMOS SA-27E, 0.18µm (0.11 Leff), 5-layer metal Packages: 25mm, 552-ball Ceramic Ball Grid Array (CBGA) Plastic Ball Grid Array (PBGA) Power (estimated): Less than: 4.0W normal mode sleep mode Supply voltages required: 3.3V, 2.5V, 1.8V
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PowerPC 440GP Embedded Processor Data Sheet
Contents
Ordering Information Address Maps PowerPC Processor Core Internal Buses PCI-X Interface SDRAM Memory Controller On-Chip SRAM External Peripheral Controller (EBC) Ethernet Controller Interface Controller Serial Port Interface General Purpose Timers (GPT) General Purpose (GPIO) Controller Universal Interrupt Controller (UIC) JTAG Signal Lists Signal Description Heat Sink Mounting Information (Ceramic Package Only) Test Conditions Spread Spectrum Clocking SDRAM Specifications SDRAM Write Operation SDRAM Read Operation Initialization Strapping EEPROM
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PowerPC 440GP Embedded Processor Data Sheet
Figures
PPC440GP Functional Block Diagram 25mm, 552-Ball CBGA Package 25mm, 552-Ball FC-PBGA Package Heat Sink Attached With Spring Clip Heat Sink Attached With Adhesive Timing Waveform Input Setup Hold Waveform Output Delay Float Timing Waveform SDRAM Signal Termination SDRAM Write Cycle Timing SDRAM MemClkOut0 Read Clock Delay SDRAM Read Data Path SDRAM Read Cycle Timing-Example SDRAM Read Cycle Timing-Example SDRAM Read Cycle Timing-Example
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PowerPC 440GP Embedded Processor Data Sheet
Tables
System Memory Address Address Signals Listed Alphabetically Signals Listed Ball Assignment Summary Signal Functional Description Absolute Maximum Ratings Package Thermal Specifications Recommended Operating Conditions Input Capacitance Power Supply Loads Clocking Specifications Peripheral Interface Clock Timings Specifications-All Speeds Specifications-400, 466, 500MHz SDRAM Output Driver Specifications Timing-DDR SDRAM Timing-DDR SDRAM TSK, TSA, Timing-DDR SDRAM Timing-DDR SDRAM TSIN TDIN Strapping Assignments
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PowerPC 440GP Embedded Processor Data Sheet
Ordering Information
information availability following parts, contact your local sales office.
Product Name PPC440GP PPC440GP PPC440GP PPC440GP PPC440GP PPC440GP PPC440GP PPC440GP PPC440GP PPC440GP PPC440GP PPC440GP PPC440GP PPC440GP PPC440GP PPC440GP Notes:
Order Part Number1 IBM25PPC440GP-3CC400C IBM25PPC440GP-3CC400CZ IBM25PPC440GP-3CC400E IBM25PPC440GP-3CC400EZ IBM25PPC440GP-3CC466C IBM25PPC440GP-3CC466CZ IBM25PPC440GP-3CC500C IBM25PPC440GP-3CC500CZ IBM25PPC440GP-3FC400C IBM25PPC440GP-3FC400CZ IBM25PPC440GP-3FC400E IBM25PPC440GP-3FC400EZ IBM25PPC440GP-3FC466C IBM25PPC440GP-3FC466CZ IBM25PPC440GP-3FC500C IBM25PPC440GP-3FC500CZ
Processor Frequency 400MHz 400MHz 400MHz 400MHz 466MHz 466MHz 500MHz 500MHz 400MHz 400MHz 400MHz 400MHz 466MHz 466MHz 500MHz 500MHz
Package 25mm, CBGA 25mm, CBGA 25mm, CBGA 25mm, CBGA 25mm, CBGA 25mm, CBGA 25mm, CBGA 25mm, CBGA 25mm, PBGA 25mm, PBGA 25mm, PBGA 25mm, PBGA 25mm, PBGA 25mm, PBGA 25mm, PBGA 25mm, PBGA
Level
Value 0x40120481 0x40120481 0x40120481 0x40120481 0x40120481 0x40120481 0x40120481 0x40120481 0x40120481 0x40120481 0x40120481 0x40120481 0x40120481 0x40120481 0x40120481 0x40120481
JTAG 0x22052049 0x22052049 0x22052049 0x22052049 0x22052049 0x22052049 0x22052049 0x22052049 0x22052049 0x22052049 0x22052049 0x22052049 0x22052049 0x22052049 0x22052049 0x22052049
Order Part Number indicates tape-and-reel shipping package. Otherwise, chips shipped tray.
Each part number contains revision code. This mask revision number included part number identification purposes only. (Processor Version Register) JTAG register software accessible (read-only) contain information that uniquely identifies part. Refer PPC440GP User's Manual details accessing these registers. Order Part Number
IBM25PPC440GP-3CC500Ex
Shipping Package: Blank Tray Tape reel Part Number Case Temperature Range -40°C +85°C -40°C +105°C Processor Speed Revision Level
Grade Reliability Package Ceramic Plastic
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PowerPC 440GP Embedded Processor Data Sheet
PPC440GP Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Timers PPC440 Processor Core JTAG 32KB D-Cache Trace 32KB I-Cache On-chip Peripheral (OPB) Timers GPIO UART Power Mgmt DCRs
internal external
SRAM
Controller (4-Channel)
Bridge
Processor Local (PLB) Ethernet External External Master Controller Controller 66MHz 32-bit addr 32-bit data
SDRAM Controller 133MHz 13-bit addr 32/64-bit data
PCI-X Bridge
133MHz
RMII SMII
PPC440GP designed using Microelectronics Blue Logicmethodology which major functional blocks integrated together create application-specific product (ASIC). This approach provides consistent create complex ASICs using CoreConnect BusArchitecture. Note: CoreConnect buses provide: 128-bit interfaces 133.33MHz, 2.1GB/s 32-bit interfaces 66.66MHz, 266MB/s
Address Maps
PPC440GP incorporates address maps. first fixed processor system memory address map. This address defines possible contents various address regions which processor access. second address Device Configuration Registers (DCRs). DCRs accessed software running PPC440GP processor through mtdcr mfdcr instructions.
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PowerPC 440GP Embedded Processor Data Sheet
System Memory Address
Function SDRAM Local Memory1 SRAM Reserve Reserved UART0 Reserved UART1 Reserved IIC0 Reserved IIC1 Reserved Arbiter Internal Peripherals Reserved GPIO Controller Ethernet ZMII Ethernet GMII Reserved Ethernet Controller Ethernet Controller General Purpose Timer Reserved Expansion ROM2 Boot ROM2, Reserved PCI-X Reserved PCI-X External Configuration Registers PCI-X Reserved PCI-X Bridge Core Configuration Registers Reserved PCI-X Special Cycle PCI-X Memory Notes: SDRAM on-chip SRAM located anywhere Local Memory area memory map. Boot Expansion areas memory intended Flash-type devices. While locating volatile SDRAM SRAM this region supported, these regions this purpose recommended. When optional boot from PCI-X memory selected, PCI-X Boot address space begins FFFE 0000 (128 KB). Function Start Address 0000 0000 8000 0000 8000 2000 0000 0000 4000 0000 4000 0200 4000 0208 4000 0300 4000 0308 4000 0400 4000 0420 4000 0500 4000 0520 4000 0600 4000 0640 4000 0700 4000 0780 4000 0790 4000 0790 4000 0800 4000 0900 4000 0A00 4000 0B00 F000 0000 FFE0 0000 0000 0000 0800 0000 0C00 0000 0EC0 0000 0EC0 0008 0EC8 0000 0EC8 0100 0ED0 0000 0EE0 0000 Address 7FFF FFFF 8000 1FFF FFFF FFFF 3FFF FFFF 4000 01FF 4000 0207 4000 02FF 4000 0307 4000 03FF 4000 041F 4000 04FF 4000 051F 4000 05FF 4000 063F 4000 06FF 4000 077F 4000 078F 4000 079F 4000 07FF 4000 08FF 4000 09FF 4000 0AFF EFFF FFFF FFDF FFFF FFFF FFFF 07FF FFFF 0BFF FFFF 0EBF FFFF 0EC0 0007 0EC7 FFFF 0EC8 00FF 0EC8 00FF 0EDF FFFF FFFF FFFF 55.76 256B 64MB 254MB 256B 256B 256B 128B Size
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PowerPC 440GP Embedded Processor Data Sheet
Address Device Configuration Registers
Function Total Address Space1 function: Reserved Memory Controller External Controller External Master Performance Monitor SRAM Reserved Bridge Reserved Bridge Power Management Reserved Interrupt Controller Interrupt Controller Clock, Control, Reset Reserved Controller Reserved Ethernet Reserved Notes: address space addressable with bits (1024 unique addresses). Each unique address represents single 32-bit (word) register. kiloword (1024W) equals (4096 bytes). 128W 512W Start Address Address Size (4KB)1
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PowerPC 440GP Embedded Processor Data Sheet
PowerPC Processor Core
PowerPC processor core designed high-end applications: RAID controllers, routers, switches, printers, set-top boxes, etc. first processor core implement Book PowerPC embedded architecture first 128-bit version IBM's on-chip CoreConnect Architecture. Features include: 500MHz operation PowerPC Book architecture 32KB I-cache, 32KB D-cache Three logical regions D-cache: locked, transient, normal D-cache full line flush capability 41-bit virtual address, 36-bit (64GB) physical address Superscalar, out-of-order execution 7-stage pipeline execution pipelines Dynamic branch prediction Memory management unit 64-entry, full associative, unified Separate instruction data micro-TLBs Storage attributes write-through, cache-inhibited, guarded, little endian Debug facilities Multiple instruction data range breakpoints Data value compare Single step, branch, trap events Non-invasive real-time trace interface instructions Single cycle multiply multiply-accumulate integer multiply 32-bit
Internal Buses
PowerPC 440GP features three standard on-chip buses: Processor Local (PLB), OnChip Peripheral (OPB), Device Control Register (DCR). high performance, high bandwidth cores such PowerPC processor core, SDRAM memory controller, PCI-X bridge connect PLB. hosts lower data rate peripherals. daisy-chained provides lower bandwidth path passing status control information between processor core other on-chip cores. Features include: 128-bit implementation architecture Separate simultaneous read write data paths 36-bit address Simultaneous control, address, data phases Four levels pipelining Byte enable capability supporting unaligned transfers 64-byte burst transfers 133MHz, maximum 4.2GB/s (simultaneous read write) Processor:bus clock ratios 3:1, 4:1, 5:1, 5:2,
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PowerPC 440GP Embedded Processor Data Sheet
Dynamic sizing 32-, 16-, 8-bit data path Separate simultaneous read write data paths 36-bit address 66.66MHz, maximum 266MB/s 32-bit data path address
On-Chip SRAM
Features include: physical bank Memory cycles supported: Single beat read write, bytes 64-byte burst transfers Guarded memory accesses Sustainable 2.1GB/s peak bandwidth 133MHz
PCI-X Interface
PCI-X interface allows connection PCI-X devices PowerPC processor local memory. This interface designed Version 1.0a PCI-X Specification supports 64-bit PCI-X buses. 32/64-bit conventional mode, compatible with Version 2.2, also supported. Reference Specifications: PowerPC CoreConnect (PLB) version PLB4 Specification Version Power Management Interface Specification Version Features include: PCI-X 1.0a Split transactions Frequency 133MHz 64-bit backward compatibility Frequency 66MHz 64-bit Host Bridge Adapter Device's interface Internal arbitration function, supporting external devices, that disabled with external arbiter Support Message Signaled Interrupts Simple message passing capability Asynchronous Power Management register addressable both from on-chip processor device sides Ability boot from PCI-X memory Error tracking/status
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PowerPC 440GP Embedded Processor Data Sheet
Supports initiation transfer following address spaces: Single beat reads writes Single beat burst memory reads writes Single beat configuration reads writes (type type Single beat special cycles
SDRAM Memory Controller
Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMs other discrete devices. four 512MB logical banks supported limited configurations. Global memory timings, address bank sizes, memory addressing modes programmable. Features include: Registered non-registered industry standard DIMMs other discrete devices 64-bit memory interface with optional 8-bit (SEC/DED) Sustainable 2.1GB/s peak bandwidth 133MHz SSTL_2 logic chip selects latencies supported PC200/266 support Page mode accesses eight open pages) with configurable paging policy Programmable address mapping timing Hardware software initiated self-refresh Power management (self-refresh, suspend, sleep)
External Peripheral Controller (EBC)
Features include: eight ROM, EPROM, SRAM, Flash memory, slave peripheral banks supported 66.66MHz operation (266MB/s) Burst non-burst devices 16-, 32-bit byte-addressable data 32-bit address, address space Peripheral Device pacing with external "Ready" Latch data Ready, synchronous asynchronous Programmable access timing device Wait States non-burst Burst Wait States first access Wait States subsequent accesses Programmable CSon, CSoff relative address Programmable OEon, WEon, WEoff clock cycles) relative Programmable address mapping External master interface Write posting from external master Read prefetching external master reads Bursting capable from external master Allows external master access non-EBC slaves External master control slaves access control
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PowerPC 440GP Embedded Processor Data Sheet
Ethernet Controller Interface
Ethernet support provided PPC440GP interfaces physical layer, included chip. Features include: interfaces running full- half-duplex modes 10Mb/s 100Mb/s full Media Independent Interface (MII) with 4-bit parallel data transfer Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer Serial Media Independent Interfaces (SMII)
Controller
Features include: Supports following transfers: Memory-to-memory transfers Buffered peripheral memory transfers Buffered memory peripheral transfers Four channels Scatter/Gather capability programming multiple operations 16-, 32-bit peripheral support (OPB external) 64-bit addressing Address increment decrement Supports internal external peripherals Support memory mapped peripherals Support peripherals running slower frequency buses
Serial Port
Features include: 8-pin UART 4-pin UART interface provided Selectable internal external serial clock allow wide range baud rates Register compatibility with 16750 register Complete status reporting capability Fully programmable serial-interface characteristics Supports using internal engine
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PowerPC 440GP Embedded Processor Data Sheet
Interface
Features include: interfaces provided Support Philips® Semiconductors Specification, dated 1995 Operation 100kHz 400kHz 8-bit data 7-bit address Slave transmitter receiver Master transmitter receiver Multiple masters Supports fixed interface independent byte data buffers Twelve memory-mapped, fully programmable configuration registers programmable interrupt request signal Provides full management protocols Programmable error recovery
General Purpose Timers (GPT)
Provides separate time base counter additional system timers addition those defined processor core. 32-bit Time Base Counter driven clock Five 32-bit compare timers
General Purpose (GPIO) Controller
Controller functions GPIO registers programmed accessed memory-mapped master accesses. GPIOs pin-shared with other functions. DCRs control whether particular that GPIO capabilities acts GPIO used another purpose. Each GPIO output separately programmable emulate open drain driver (that drives zero, tri-stated output
Universal Interrupt Controller (UIC)
TwoUniversal Interrupt Controllers (UIC) available. They provide control, status, communications necessary between external internal sources interrupts on-chip PowerPC processor. Note: Processor specific interrupts (for example, page faults) resources. Features include: external interrupts internal interrupts Edge triggered level-sensitive Positive negative active Non-critical critical interrupt on-chip processor core Programmable interrupt priority ordering Programmable critical interrupt vector faster vector processing
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PowerPC 440GP Embedded Processor Data Sheet
JTAG
Features include: IEEE 1149.1 Test Access Port RISCWatch Debugger support JTAG Boundary Scan Description Language (BSDL)
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PowerPC 440GP Embedded Processor Data Sheet
25mm, 552-Ball CBGA Package
View
Corner
Chip
Capacitor Note: dimensions
Bottom View
25.0 23.0 25.0 0.04 SOLDERBALL 1.00
1.95 1.65
8.04
3.80
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PowerPC 440GP Embedded Processor Data Sheet
25mm, 552-Ball FC-PBGA Package
View
Corner
Note: dimensions
Bottom View
25.0 23.0 0.66 SOLDERBALL 1.00
1.214
25.0
7.75
23.0
3.191 0.17
0.508
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PowerPC 440GP Embedded Processor Data Sheet
Signal Lists
following table lists external signals alphabetical order shows ball (pin) number which signal appears. Multiplexed signals shown with default signal (following reset) brackets alternate signal brackets. Multiplexed signals appear alphabetically multiple times list-once each signal name ball. page number listed gives page "Signal Functional Description" page where signals indicated interface group begin. cases where signals same interface group (for example, Ethernet) have different names distinguish variations mode operation, names separated comma with primary name appearing first. These signals listed only once, appear alphabetically primary name.
Signals Listed Alphabetically
Signal Name AGND AGND AGND AMVDD APVDD ASVDD BankSel0 BankSel1 BankSel2 BankSel3 [BE0]PCIXC0 [BE1]PCIXC1 [BE2]PCIXC2 [BE3]PCIXC3 [BE4]PCIXC4 [BE5]PCIXC5 [BE6]PCIXC6 [BE7]PCIXC7 BusReq ClkEn0 ClkEn1 ClkEn2 ClkEn3 Ball AA11 AB11 AA16 AD09 AB15 AD11 AD05 AA24 AB05 AD17 AB10 AA18 AB14 AA09 AA07 AC05
(Part
Interface Group Power-Analog ground Power-MemClkOut analog voltage Power-PCI-X analog voltage Power-SysClk analog voltage SDRAM Page
SDRAM
PCI-X
External Master Peripheral SDRAM
SDRAM
SDRAM
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name DMAAck0 DMAAck1 DMAAck2 DMAAck3 DMAReq0 DMAReq1 DMAReq2 DMAReq3 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DrvrInh1 DrvrInh2 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCCD, EMC1RxErr EMCCrS, EMC0CrSDV EMCMDClk EMCMDIO EMCRxClk EMCRxD0, EMC0RxD0, EMC0RxD EMCRxD1, EMC0RxD1, EMC1RxD EMCRxD2, EMC1RxD0 EMCRxD3, EMC1RxD1 EMCRxDV, EMC1CrSDV EMCRxErr, EMC0RxErr EMCTxClk, EMCRefClk EMCTxD0, EMC0TxD0, EMC0TxD EMCTxD1, EMC0TxD1, EMC1TxD EMCTxD2, EMC1TxD0 EMCTxD3, EMC1TxD1 EMCTxEn, EMC0TxEn, EMCSync EMCTxErr, EMC1TxEn Ball AC20 AC16 AC14 AB13 AC11 AC09 AA05 AB07 AB06 AD06 AC03 AB04 AD04 Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet SDRAM System System SDRAM External Slave Peripheral External Slave Peripheral
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name EOT0/TC0 EOT1/TC1 EOT2/TC2 EOT3/TC3 ExtAck ExtReq ExtReset Ball AA22 AB23 Power External Master Peripheral External Master Peripheral External Master Peripheral External Slave Peripheral
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name Ball AA02 AA06 AA10 AA13 AA17 AA21 AC04 AC08 AC12 AC15 AC19 Power
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name [GPIO00]IRQ00 [GPIO01]IRQ01 [GPIO02]IRQ02 [GPIO03]IRQ03 [GPIO04]IRQ04 [GPIO05]IRQ05 [GPIO06]IRQ06 [GPIO07]IRQ07 [GPIO08]IRQ08 [GPIO09]IRQ09 [GPIO10]IRQ10 GPIO11 [GPIO12]UART1_Rx [GPIO13]UART1_Tx [GPIO14]UART1_DSR/CTS [GPIO15]UART1_RTS/DTR [GPIO16]IIC1SClk [GPIO17]IIC1SDA [GPIO18]TrcBS0 [GPIO19]TrcBS1 [GPIO20]TrcBS2 [GPIO21]TrcES0 [GPIO22]TrcES1 [GPIO23]TrcES2 [GPIO24]TrcES3 [GPIO25]TrcES4 [GPIO26]TrcTS0 [GPIO27]TrcTS1 [GPIO28]TrcTS2 [GPIO29]TrcTS3 [GPIO30]TrcTS4 [GPIO31]TrcTS5 Halt HoldAck HoldReq IIC0SClk IIC0SDA IIC1SClk[GPIO16] IIC1SDA[GPIO17] Ball System External Master Peripheral External Master Peripheral Peripheral Peripheral Peripheral Peripheral System
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name IRQ00[GPIO00] IRQ01[GPIO01] IRQ02[GPIO02] IRQ03[GPIO03] IRQ04[GPIO04] IRQ05[GPIO05] IRQ06[GPIO06] IRQ07[GPIO07] IRQ08[GPIO08] IRQ09[GPIO09] IRQ10[GPIO10] [IRQ11]PCIReq1 [IRQ12]PCIGnt1 MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut0 Ball AD20 AB20 AD18 AD16 AB18 SDRAM SDRAM Interrupts
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Ball AD21 AB21 AC22 AA20 AD19 AB19 AB16 AC18 AB17 AA14 AD15 AD13 AD14 AB12 SDRAM
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 MemData59 MemData60 MemData61 MemData62 MemData63 MemVRef1 MemVRef2 Ball AD12 AD10 AB08 AD08 AC07 AB09 AA01 AA03 AB02 AB03 SDRAM SDRAM
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball Ball AB01 AB24 AC01 AC02 AC23 AC24 AD01 AD02 AD03 AD22 AD23 AD24 physical ball does exist these ball coordinates.
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD PCIX133Cap PCIXAck64 Ball AA23 PCI-X PCI-X Power
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIXAD00 PCIXAD01 PCIXAD02 PCIXAD03 PCIXAD04 PCIXAD05 PCIXAD06 PCIXAD07 PCIXAD08 PCIXAD09 PCIXAD10 PCIXAD11 PCIXAD12 PCIXAD13 PCIXAD14 PCIXAD15 PCIXAD16 PCIXAD17 PCIXAD18 PCIXAD19 PCIXAD20 PCIXAD21 PCIXAD22 PCIXAD23 PCIXAD24 PCIXAD25 PCIXAD26 PCIXAD27 PCIXAD28 PCIXAD29 PCIXAD30 PCIXAD31 Ball PCI-X
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIXAD32 PCIXAD33 PCIXAD34 PCIXAD35 PCIXAD36 PCIXAD37 PCIXAD38 PCIXAD39 PCIXAD40 PCIXAD41 PCIXAD42 PCIXAD43 PCIXAD44 PCIXAD45 PCIXAD46 PCIXAD47 PCIXAD48 PCIXAD49 PCIXAD50 PCIXAD51 PCIXAD52 PCIXAD53 PCIXAD54 PCIXAD55 PCIXAD56 PCIXAD57 PCIXAD58 PCIXAD59 PCIXAD60 PCIXAD61 PCIXAD62 PCIXAD63 PCIXC0[BE0] PCIXC1[BE1] PCIXC2[BE2] PCIXC3[BE3] PCIXC4[BE4] PCIXC5[BE5] PCIXC6[BE6] PCIXC7[BE7] PCIXCap PCIXClk PCIXDevSel PCIXFrame Ball PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIXGnt0 PCIXGnt1[IRQ12] PCIXGnt2 PCIXGnt3 PCIXGnt4 PCIXGnt5 PCIXIDSel PCIXINT PCIXIRDY PCIXM66En PCIXParHigh PCIXParLow PCIXPErr PCIXReq0 PCIXReq1[IRQ11] PCIXReq2 PCIXReq3 PCIXReq4 PCIXReq5 PCIXReq64 PCIXReset PCIXSErr PCIXStop PCIXTRDY Ball PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X PCI-X
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerAddr00 PerAddr01 PerAddr02 PerAddr03 PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0 PerCS1 PerCS2 PerCS3 PerCS4 PerCS5 PerCS6 PerCS7 Ball External Slave Peripheral External Slave Peripheral External Master Peripheral External Slave Peripheral Note: PerAddr00 most significant (msb) this bus.
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerErr PerOE PerPar0 PerPar1 PerPar2 PerPar3 PerReady[RcvrInh] PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 PerWE Ball External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral External Master Peripheral External Slave Peripheral External Slave Peripheral Note: PerData00 most significant (msb) this bus.
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name [RcvrInh]PerReady RefVEn Reserved Reserved SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SysClk SysErr SysReset TestEn TmrClk TrcBS0[GPIO18] TrcBS1[GPIO19] TrcBS2[GPIO20] TrcClk TrcES0[GPIO21] TrcES1[GPIO22] TrcES2[GPIO23] TrcES3[GPIO24] TrcES4[GPIO25] TrcTS0[GPIO26] TrcTS1[GPIO27] TrcTS2[GPIO28] TrcTS3[GPIO29] TrcTS4[GPIO30] TrcTS5[GPIO31] TrcTS6 TRST UART0_CTS UART0_DCD Ball AD07 AA08 AA15 AC06 AC13 AC21 AB22 Trace Trace Trace Trace Trace Trace Trace JTAG UART Peripheral UART Peripheral Note: Used initialization strapping input. Trace Trace Trace System System System JTAG JTAG JTAG System System JTAG Power SDRAM System System Reserved
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_DSR/CTS[GPIO14] UART1_RTS/DTR[GPIO15] UART1_Rx[GPIO12] UART1_Tx[GPIO13] UARTSerClk Ball
(Part
Interface Group UART Peripheral Note: Used initialization strapping input. UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral UART Peripheral Page
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name Ball AA04 AA12 AA19 AC10 AC17 SDRAM Power
(Part
Interface Group Page
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PowerPC 440GP Embedded Processor Data Sheet
following table, only primary (default) signal name shown each pin. Multiplexed multifunction signals marked with asterisk (*). determine what signals functions multiplexed those pins, look primary signal name "Signals Listed Alphabetically" page
Signals Listed Ball Assignment
Ball Signal Name ball ball ball PCIXAD51 DrvrInh2 PCIXAD58 EMCRxD2 PCIXAD42 UARTSerClk PCIXAD05 PCIXFrame PerAddr03 PerAddr12 PCIXM66En PCIXAD09 PerAddr11 PCIXPErr PCIXSErr PerAddr04 PCIXAD21 PCIXAD22 ball ball ball Ball ball ball PCIXAD46 OVDD PCIXAD54 PCIXAD62 PCIXAD01 PerAddr02 OVDD PerAddr13 PCIXAD13
(Part
Ball Signal Name ball PCIXAD41 PCIXC5 PCIXAD50 EMCTxErr PCIXAD57 PerBLast PCIXC4 PCIXAD55 PCIXAD04 PerAddr01 PCIXTRDY UART0_CTS PerAddr14 PCIXAD10 PCIXAD14 PCIXAD00 UART1_Rx PCIXC2 PerAddr10 PCIXAD23 PCIXGnt1 PCIXAD28 ball Ball Signal Name PCIXAD36 OVDD PCIXAD45 PCIXAD53 PCIXAD61 PCIXAck64 OVDD PerAddr00 PerAddr15 PCIXAD15 OVDD PerAddr05 PCIXAD20 PCIXAD30 PCIXAD31
Signal Name
UART0_DTR OVDD PerAddr16 PCIXAD25 ball ball
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name EMCRxD1 PCIXAD40 PCIXClk PCIXAD49 UART1_RTS/DTR PCIXAD56 PCIXAD60 PCIXAD63 PCIXReq64 PCIXAD03 PerAddr06 PCIXIRDY PCIXDevSel PerAdd09 PCIXAD11 PCIXC1 PerCS0 PCIXAD16 PCIXAD17 PCIXReq2 PCIXReq1 PCIXGnt0 PCIXAD27 PCIXReq0 Ball PCIXAD35 PCIXAD44 PCIXAD52 PCIXAD59 OVDD PCIXC7 PCIXAD06 PCIXC0 OVDD PCIXParLow PCIXAD18 PCIXC3 PCIXAD24 OVDD PCIXAD29
(Part
Ball Signal Name APVDD PCIXAD39 EMCRxD0 PCIXAD48 PCIXAD43 UART1_DSR/CTS PCIXIDSel PCIX133Cap PCIXC6 PCIXAD02 IIC0SClk PCIXAD07 IIC0SDA PCIXAD08 PCIXAD12 UART0_RTS UART0_Rx PCIXAD19 PerData04 PerData03 PCIXAD26 SysClk PCIXReq4 ASVDD SysClk Ball Signal Name PCIXAD33 PCIXAD32 PCIXAD38 OVDD PCIXAD47 EMCRxD3 OVDD IIC1SClk OVDD IIC1SDA UART0_RI PerData05 PerData02 OVDD PerData01 PerData00
Signal Name
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name AGND EMCRxClk EMCTxD3 EMCTxD2 PCIXAD37 EMCTxClk EMCCD EMCMDClk PerData19 PerData18 PerData17 PerData16 PerData15 PerData14 PerData13 UART1_Tx PerData12 PerData11 PerData10 PerData9 PerData8 PerData7 PerData6 AGND Ball
(Part
Ball Signal Name Reserved RefVEn PerCS4 PCIXParHigh EMCMDIO EMCTxEn DrvrInh1 PCIXAD34 EMCTxD0 PerCS1 UART0_Tx PCIXStop PerCS6 PerData20 PerAddr17 PerData31 PerData30 IRQ03 PerData29 IRQ01 PerAddr18 PerAddr19 PCIXCap PerAddr22 Ball Signal Name PerAddr21 OVDD PerAddr07 TestEn PCIXINT PerOE DMAReq1 IRQ06 EOT3/TC3 OVDD PCIXGnt3 IRQ05 PerAddr20 PCIXReset
Signal Name EMCRxDV EMCRxErr OVDD EMCTxD1 EMCCrS OVDD PerData28 PerData27 PerData26 PerData25 PerData24 OVDD PerData23 PerData22 PerData21
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name PerAddr08 PerAddr28 DMAAck0 PerReady OVDD TrcES2 DMAReq2 IRQ04 TrcBS0 IRQ00 IRQ08 PCIXGnt2 OVDD TRST Ball DMAReq3 PerWE TrcTS1 Reserved PerR/W DMAAck2 DMAAck1 TrcES3 TrcTS3 SysReset DMAAck3 MemData28 GPIO11 EOT1/TC1 EOT2/TC2 TrcBS1 IRQ07 PCIXGnt5 IRQ02 PerErr IRQ09 TrcES1 PerAddr23
(Part
Ball Signal Name TrcTS6 DMAReq0 TrcClk OVDD TrcTS2 TrcTS4 MemData42 MemData14 EOT0/TC0 OVDD PCIXReq5 PCIXReq3 OVDD PCIXGnt4 PerAddr25 Ball Signal Name DQS7 SysErr PerCS5 TrcTS0 TrcES4 TrcTS5 MemData61 MemData56 MemVRef2 MemData38 MemData37 MemData35 MemData22 MemVRef1 MemData18 ExtReset PerWBE0 PerAddr24 TrcBS2 TrcES0 PerPar1 PerPar0 PerCS3
Signal Name
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Signals Listed Ball Assignment
Ball Signal Name TmrClk PerCS7 OVDD MemData63 MemData57 ECC4 MemData36 SVDD MemData21 SVDD MemData04 PerClk OVDD PerPar3 PerAddr26 PerAddr27 Ball MemData55 UART0_DSR PerCS2 Halt MemData60 MemData54 MemClkOut0 MemClkOut0 MemAddr12 MemAddr9 MemData31 MemAddr8 MemData26 MemData19 MemData09 MemData05 IRQ10 PerWBE1 PerAddr29 PerAddr31 PerAddr30 UART0_DCD
(Part
Ball Signal Name MemData58 OVDD MemData59 MemData62 ECC3 ClkEn3 SVDD MemData32 BankSel1 MemAddr10 SVDD MemData08 PerPar2 PerWBE2 PerWBE3 Ball Signal Name MemData51 MemData53 DQS6 MemData46 MemData43 MemData47 ClkEn2 MemData34 MemAddr11 MemData30 MemData27 MemAddr7 MemData23 MemData20 MemData10 MemData13 MemAddr00 MemAddr02 HoldAck HoldReq
Signal Name
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PowerPC 440GP Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 Signal Name MemData48 MemData49 DQS8 SVDD AGND MemData16 SVDD MemData03 ExtAck OVDD BusReq Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 ball MemData50 MemData52 ECC6 ECC1 ECC0 MemData40 MemData45 ClkEn1 AMVDD MemClk MemData29 DQS3 BankSel0 MemData11 MemData15 MemAddr6 MemData07 MemAddr3 MemData01 ExtReq ball
(Part
Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 Signal Name ball ball ECC5 SVDD MemData44 DQS5 DQS4 SVDD DQS2 DQS1 MemData12 DQS0 SVDD MemData02 ball ball Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 Signal Name ball ball ball ECC7 BankSel3 ECC2 MemData41 MemData39 BankSel2 MemData33 MemData24 MemData25 MemData17 MemAddr5 ClkEn0 MemAddr4 MemData06 MemAddr01 MemData00 ball ball ball
Signal Name
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PowerPC 440GP Embedded Processor Data Sheet
Signal PPC440GP embedded controller provided 552-ball, ball grid array package. following tables describe package level pinout.
Summary
Group
Signal pins, non-multiplexed Signal pins, multiplexed Total Signal Pins AxVDD AGnd OVDD SVDD Total Power Pins Reserved Total Pins
Pins
table "Signal Functional Description" page each signal listed along with short description function. Active-low signals (for example, RAS) marked with overline. Please "Signals Listed Alphabetically" page (ball) number which each signal assigned. Multiplexed Signals Some signals multiplexed same that used different functions. most cases, signal names shown this table accompanied signal names that multiplexed same pin. need know what, any, signals multiplexed with particular signal, look name "Signals Listed Alphabetically" page expected that single application particular will always programmed serve same function. flexibility multiplexing allows single chip offer richer selection than would otherwise possible. Multipurpose Signals addition multiplexing, some pins also multi-purpose. example, peripheral controller address pins (PerAddr00:31) used outputs PPC440GP broadcast address external slave devices when PPC440GP control external bus. When during course normal chip operation external master gains ownership external bus, these same pins used inputs which driven external master received PPC440GP. this example, pins also bidirectional, serving both inputs outputs. Multimode Signals some cases (for example, Ethernet) function vary with different modes operation. When multiple signal names assigned distinguish different modes operation, names shown. Strapping Pins group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Strapping" page 70). Note that these multiplexed pins since function pins programmable. 5/13/04 Page
PowerPC 440GP Embedded Processor Data Sheet
Signal Functional (Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name PCI-X Interface PCIXAD00:63 PCIXC0:7[BE0:7] PCIXCap PCIX133Cap Address/Data (bidirectional). PCI-X Command[Byte Enables]. Capable PCI-X operation. PCI-X devices capable. Provides timing interface transactions. PCIXClk Note: PCI-X interface being used, drive this with 3.3V clock signal frequency between 66MHz Indicates driving device decoded address target current access. Driven current master indicate beginning duration access. Indicates that specified agent granted access bus. Indicates that specified agent granted access bus. Indicates that specified agent granted access bus. Used chip select during configuration read write transactions. Level sensitive interrupt. Indicates initiating agent's ability complete current data phase transaction. Capable 66MHz operation. Even parity across PCIAD32:63 PCIXC0:3[BE4:7]. Even parity across PCIAD0:31 PCIXC0:3[BE0:3]. Reports data parity errors during transactions except Special Cycle. indication PCI-X arbiter that specified agent wishes bus. indication PCI-X arbiter that specified agent wishes bus. Asserted current master, indicating 64-bit transfer. Indicates target transfer data using bits. 3.3V 3.3V 3.3V tolerant 3.3V LVTTL 3.3V Description Type
Notes
PCIXDevSel PCIXFrame PCIXGnt0 PCIXGnt1 PCIXGnt2:5 PCIXIDSel PCIXINT PCIXIRDY PCIXM66En PCIXParHigh PCIXParLow PCIXPErr PCIXReq0 PCIXReq1:5 PCIXReq64 PCIXAck64
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V tolerant 3.3V LVTTL 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
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Signal Functional (Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name PCIXReset Description Brings device registers logic consistent state. Reports address parity errors, data parity errors Special Cycle command, other catastrophic system errors. Indicates current target requesting master stop current transaction. Type 3.3V
Notes
PCIXSErr
3.3V
PCIXStop PCIXTRDY SDRAM Interface BA0:1 BankSel0:3 ClkEn0:3 DM0:8 DQS0:8 ECC0:7 MemAddr00:12 MemClkOut0 MemClkOut0 MemData00:63 MemVRef1:2 Ethernet Interface EMCCD, EMC1RxErr EMCCrS, EMC0CrSDV EMCMDClk EMCMDIO
3.3V 3.3V
Indicates target agent's ability complete current data phase transaction.
Bank Address supporting four internal banks. Selects four external SDRAM banks. Column Address Strobe. Clock Enable. each bank. Memory write data byte lane masks. MEMDM8 byte lane mask byte lane. Byte lane data strobe. DQS8 data strobe byte lane. check bits 0:7. Memory address bus. Subsystem clock. Memory data bus. Memory reference voltage (SVREF) input. Address Strobe. Write Enable.
2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 Voltage Receiver 2.5V SSTL_2 2.5V SSTL_2
MII: Collision detection RMII Receive error MII: Carrier sense RMII Carrier sense data valid RMII: Management data clock RMII: Transfer command status information between
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
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PowerPC 440GP Embedded Processor Data Sheet
Signal Functional (Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name EMCRxD0:3, EMC0RxD0:1, EMC1RxD0:1, EMC0RxD, EMC1RxD EMCRxDV, EMC1CrSDV EMCRxClk EMCRxErr, EMC0RxErr EMCTxClk, EMCRefClk EMCTxD0:3, EMC0TxD0:1, EMC1TxD0:1, EMC0TxD, EMC1TxD EMCTxEn, EMC0TxEn, EMCSync EMCTxErr, EMC1TxEn MII: Receive data RMII Receive data RMII Receive data SMII Receive data SMII Receive data MII: Receive data valid RMII Carrier sense data valid MII: Receive clock MII: Receive error RMII Receive error MII: Transmit clock RMII SMII: Reference clock MII: Transmit data RMII Transmit data RMII Transmit data SMII Transmit data SMII Transmit data MII: Transmit data enabled RMII Transmit data enabled SMII: Sync signal MII: Transmit error: RMII: Transmit data enabled Description Type
Notes
tolerant 3.3V LVTTL
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
tolerant 3.3V LVTTL
tolerant 3.3V LVTTL tolerant 3.3V LVTTL
External Slave Peripheral Interface DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 Used PPC440GP indicate that data transfers have occurred. Used slave peripherals indicate they prepared transfer data. Transfer/Terminal Count. Peripheral address used PPC440GP when external master mode, otherwise used external master. Note: PerAddr00 most significant (msb) this bus. External peripheral data byte enables. Used either peripheral controller, controller, external master indicates last transfer memory access. External peripheral device select. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerAddr00:31
tolerant 3.3V LVTTL
PerWBE0:3
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerBLast
PerCS0:7
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PowerPC 440GP Embedded Processor Data Sheet
Signal Functional (Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Description Peripheral data used PPC440GP when external master mode, otherwise used external master. Note: PerData00 most significant (msb) this bus. Used either peripheral controller controller depending upon type transfer involved. When PPC440GP master, enables selected SDRAMs drive bus. External peripheral data byte parity. Used peripheral slave indicate ready transfer data. Used PPC440GP when external master mode, output either peripheral controller controller depending upon type transfer involved. High indicates read from memory, indicates write memory. Otherwise, used external master input indicate direction transfer. Write Enable. when four PerWBE0:3 signals low. Type
Notes
PerData00:31
tolerant 3.3V LVTTL
PerOE
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerPar0:3 PerReady
PerR/W
tolerant 3.3V LVTTL
PerWE
tolerant 3.3V LVTTL
External Master Peripheral Interface BusReq Request. Used when PPC440GP needs regain control peripheral interface from external master. External Acknowledgement. Used PPC440GP indicate that data transfer occurred. External Request. Used external master indicate prepared transfer data. Peripheral Reset. Used external master synchronous peripheral slaves. Hold Acknowledge. Used PPC440GP transfer ownership peripheral external master. Hold Request. Used external master request ownership peripheral bus. Peripheral Clock. Used external master synchronous peripheral slaves. External Error. Used input record external master errors external slave peripheral errors. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
ExtAck ExtReq ExtReset HoldAck HoldReq PerClk PerErr
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Signal Functional (Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name UART Peripheral Interface Serial clock input that provides alternative internally generated serial clock. Used cases where allowable internally generated clock rates satisfactory. This input individually connected either both UART0 UART1. UART0 Receive data. UART0 Transmit data. UART0 Data Carrier Detect. UART0 Data Ready. UART0 Clear Send. UART0 Data Terminal Ready. UART0 Request Send. UART0 Ring Indicator. UART1 Receive data. UART1 Transmit data. UART1 Data Ready Clear Send. choice determined register setting. UART1 Request Send Data Terminal Ready. choice determined register setting. Description Type
Notes
UARTSerClk
tolerant 3.3V LVTTL
UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RTS UART0_RI UART1_Rx UART1_Tx UART1_DSR/CTS UART1_RTS/DTR Peripheral Interface IIC0SClk IIC0SDA IIC1SClk IIC1SDA
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
IIC0 Serial Clock. IIC0 Serial Data. IIC1 Serial Clock. IIC1 Serial Data.
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
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PowerPC 440GP Embedded Processor Data Sheet
Signal Functional (Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Interrupts Interface IRQ00:10 IRQ11:12 JTAG Interface TRST System Interface SysClk SysErr Main system clock input. when machine check generated. Main system reset. External logic drive this bidirectional (minimum cycles) initiate system reset. system reset also initiated software. Implemented open-drain output (two states; open circuit). Processor timer external input clock. Halt from external debugger. General purpose through access these functions, software must register bits. Test Enable. Receiver Inhibit. Active only when TestEn active. Reference Voltage Enable. Used wafer testing. connect normal operation. Driver Inhibit. Used test purposes only. normal operation Clock tolerant 3.3V LVTTL tolerant 3.3V LVTTL Test Clock. Test Data Test Data Out. Test Mode Select. Test Reset. 3.3V CMOS w/pull-up 3.3V CMOS w/pull-up 3.3V LVTTL 3.3V CMOS w/pull-up 3.3V CMOS w/pull-up External interrupt Requests through External interrupt Requests through tolerant 3.3V LVTTL 3.3V Description Type
Notes
SysReset
tolerant 3.3V LVTTL
TmrClk Halt GPIO00:31 TestEn RcvrInh RefVEn DrvrInh1:2
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL 1.8V CMOS w/pull-down tolerant 3.3V LVTTL 1.8V CMOS w/pull-down tolerant 3.3V LVTTL
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PowerPC 440GP Embedded Processor Data Sheet
Signal Functional (Part Notes: Receiver input hysteresis Must pull (recommended value 3.3V, Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Trace Interface TrcBS0:2 TrcClk TrcES0:4 TrcTS0:6 Power Pins AGND AxVDD OVDD SVDD (analog) voltage ground. Ground. 1.8V-Filtered voltages input PLLs (analog circuits) Note: separate filter each three voltages recommended. 3.3V supply-I/O (except SDRAM) 2.5V supply-DDR SDRAM 1.8V supply-Logic voltage. Trace branch execution status. Trace data capture clock, runs frequency processor. Trace Execution Status presented every fourth processor clock cycle. Additional information trace execution branch status. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL Description Type
Notes
Reserved Pins
Reserved connect signals, voltage, ground these balls.
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PowerPC 440GP Embedded Processor Data Sheet
Absolute Maximum Ratings
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device. None performance specification contained this document guaranteed when operating these maximum ratings.
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface, except SDRAM) Supply Voltages Supply Voltage (DDR SDRAM Logic) Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Notes: OVDD 0.4V, required that 0.4V. Supply excursions meeting this criteria must limited less than 25ms duration during each power power down event. analog voltages used on-chip PLLs derived from logic voltage, must filtered before entering PPC440GP. separate filter, shown below, recommended each voltage: AxVDD Symbol OVDD AxVDD SVDD TSTG Value +1.95 +3.6 +1.95 +2.7 +3.6 +5.5 +150 +120 Unit Notes
ferrite bead chip, Murata BLM31A700S ceramic
This value specification operational temperature range, stress rating only.
Package Thermal Specifications
Thermal resistance values CBGA PBGA packages convection environment follows:
Parameter Symbol Package Junction-to-case thermal resistance Case-to-ambient thermal resistance (w/o heat sink) Junction-to-ball (typical) Notes: Case temperature, measured center case surface with device soldered circuit board. case-to-ambient thermal resistance measured JEDEC JESD51-6 standard environment; accurately predict thermal performance production equipment environments. operational case temperature must maintained. Modeled standard JEDEC 2S2P card, 50x50mm Ceramic Plastic Ceramic Plastic Ceramic Plastic <0.1 18.9 Airflow ft/min (m/sec) (0.51) <0.1 17.7 20.8 (1.02) <0.1 16.3 °C/W °C/W °C/W °C/W °C/W °C/W Unit Notes
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PowerPC 440GP Embedded Processor Data Sheet
Heat Sink Mounting Information (Ceramic Package Only)
Proper thermal design primarily dependent upon multiple system-level effects; that effects heat sink, flow, thermal interface material. reduce die-junction temperature, heat sinks attached package several methods: adhesive, spring clips printed-circuit board package, mounting clip screw assembly. When attaching heat sinks, important avoid placing excessive mechanical stress bonding chip substrate package board.
Heat Sink Attached With Spring Clip
Heat sink Heat sink clip Thermal grease CBGA package Printed circuit board Spring clip package Static compression (spring force)-2.27kg maximum
Heat sink Heat sink clip Thermal grease CBGA package Printed circuit board Spring clip board Static compression (spring force)-2.27kg maximum1
Note Force limited allowable compression die. Allowable package compression force 4.4kg.
Heat Sink Attached With Adhesive
Heat sink Adhesive CBGA package Printed circuit board Printed circuit board CBGA package Adhesive
Heat sink
Weight force Weight force Heat sink weight force-60g maximum
Important: guidelines indicated above diagrams must evaluated adjusted account shock vibration effects particular application.
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PowerPC 440GP Embedded Processor Data Sheet
Recommended Operating Conditions
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Logic Supply Voltage Supply Voltage SDRAM Supply Voltage Supply Voltages SDRAM Reference Voltage Input Logic High (2.5V SSTL) Input Logic High (3.3V PCI-X) Input Logic High (3.3V LVTTL, tolerant receiver) Input Logic (2.5V SSTL) Input Logic (3.3V PCI-X) Input Logic (3.3V LVTTL, tolerant receiver) Output Logic High (2.5V SSTL) Output Logic High (3.3V PCI-X) Output Logic High (3.3V LVTTL, tolerant receiver) Output Logic (2.5V SSTL) Output Logic (3.3V PCI-X) Output Logic (3.3V LVTTL, tolerant receiver) Input Leakage Current pull-up pull-down) Input Leakage Current Pull-Down Input Leakage Current Pull-Up Input Allowable Overshoot (3.3V LVTTL, tolerant receiver) Input Allowable Undershoot (3.3V LVTTL, tolerant receiver) Output Allowable Overshoot (3.3V LVTTL, tolerant receiver) Output Allowable Undershoot (3.3V LVTTL, tolerant receiver) Case Temperature 500MHz) Case Temperature (400MHz only) Notes: PCI-X drivers meet PCI-X specifications. SVREF SVDD/2 analog voltages used on-chip PLLs derived from logic voltage, must filtered before entering PPC440GP. "Absolute Maximum Ratings" page chip voltages should begin ramp within each other. There should never voltage present before OVDD within operating range. LPDL least positive down level; MPUL most positive level. Case temperature, measured center case surface with device soldered circuit board. IIL1 IIL2 IIL3 VIMAO VIMAU VOMAO VOMAU3 -0.6 +105 -0.6 +5.5 Symbol OVDD SVDD AxVDD SVREF Minimum +1.7 +3.0 +2.3 +1.65 +1.15 SVREF+0.18 0.5OVDD +2.0 -0.3 -0.5 +1.95 0.9OVDD +2.4 Typical +1.8 +3.3 +2.5 +1.8 +1.25 Maximum +1.9 +3.6 +2.7 +1.95 +1.35 SVDD+0.3 OVDD+0.5 +5.5 SVREF-0.18 0.35OVDD +0.8 SVDD OVDD OVDD 0.55 0.1OVDD (LPDL) -150 (LPDL) +0.4 (MPUL) (MPUL) +5.5 Unit Notes
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PowerPC 440GP Embedded Processor Data Sheet
Input Capacitance
Parameter Group (2.5V SSTL I/O) Group tolerant LVTTL I/O) Group (PCI-X I/O) Group (Receivers) Symbol CIN1 CIN2 CIN3 CIN4 Maximum Unit Notes
Power Supply Loads
Parameter (1.8V) active operating current OVDD (3.3V) active operating current SVDD (2.5V) active operating current AxVDD (1.8 input current Symbol IODD ISDD IADD Minimum Typical Maximum Unit Notes
Notes: "Absolute Maximum Ratings" page filter recommendations. current values listed above guaranteed highest obtainable. These values dependent many factors including type applications running, clock rates, internal functional capabilities, external interface usage, case temperature, power supply voltages. Your specific application produce significantly different results. (logic) current power primarily dependent applications running internal chip functions (DMA, PCI, Ethernet, on). OVDD (I/O) current power primarily dependent capacitive loading, frequency, utilization external buses.
Test Conditions
Clock timing switching characteristics specified accordance with operating conditions shown table "Recommended Operating Conditions." specifications characterized with 1.8V, rated temperature 50pF test load shown figure right.
Output 50pF
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PowerPC 440GP Embedded Processor Data Sheet
Clocking Specifications
Symbol SysClk Input Processor Clock MemClkOut Frequency Period High time nominal period 133.33 nominal period Frequency Period Frequency Period 1000 Frequency Period Edge stability High time time 33.33 nominal period nominal period 66.66 0.15 nominal period nominal period Parameter Units
Note: Input slew rate 1V/ns
Timing Waveform
2.0V 1.5V 0.8V
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PowerPC 440GP Embedded Processor Data Sheet
Spread Spectrum Clocking
Care must taken when using spread spectrum clock generator (SSCG) with PPC440GP. This controller uses clock generation inside chip. accuracy with which follows SSCG referred tracking skew. bandwidth phase angle determine much tracking skew there between SSCG given frequency deviation modulation frequency. When using SSCG with PPC440GP following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating PPC440GP with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation cannot exceed -3%, modulation frequency cannot exceed 40kHz. some cases, on-board PPC440GP peripherals impose more stringent requirements. Peripheral Clock logic that synchronous peripheral since this clock tracks modulation. SDRAM MemClkOut since also tracks modulation. Notes: serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur. 1.5% tolerance assumes that connected device running precise baud rates. Ethernet operation unaffected. operation unaffected. Important: system designer ensure that SSCG used with PPC440GP meets above requirements does adversely affect other aspects system.
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PowerPC 440GP Embedded Processor Data Sheet
Peripheral Interface Clock Timings
Parameter PCIXClk input frequency (asynchronous mode) PCIXClk period (asynchronous mode) PCIXClk input high time PCIXClk input time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output time EMCTxClk input frequency MII(RMII) EMCTxClk period MII(RMII) EMCTxClk input high time EMCTxClk input time EMCRxClk input frequency MII(RMII) EMCRxClk period MII(RMII) EMCRxClk input high time EMCRxClk input time GMCRefClk input frequency GMCRefClk period GMCRefClk input high time GMCRefClk input time PerClk output frequency (for ext. master sync. slaves) PerClk period PerClk output high time PerClk output time UARTSerClk input frequency UARTSerClk period UARTSerClk input high time UARTSerClk input time TmrClk input frequency TmrClk period TmrClk input high time TmrClk input time Notes: TOPB period clock. internal clock runs 1/2the frequency clock. maximum clock frequency 66.66 MHz. When PCI-X interface used support legacy interface, maximum PCIXClk frequency 66.66MHz. nominal period nominal period 2.5(5) 40(20) nominal period nominal period 2.5(5) 40(20) nominal period nominal period nominal period nominal period nominal period nominal period 2TOPB+2 TOPB+1 TOPB+1 nominal period nominal period nominal period nominal period 66.66 nominal period nominal period 1000/(2TOPB nominal period nominal period
1+2ns)
133.33 nominal period nominal period 25(50) 400(200) 25(50) 400(200)
Units
Notes
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PowerPC 440GP Embedded Processor Data Sheet
Input Setup Hold Waveform
Clock
Inputs Valid
Output Delay Float Timing Waveform
Clock
Outputs
High (Drive) Float (High-Z) (Drive) Valid Valid
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PowerPC 440GP Embedded Processor Data Sheet
Specifications-All Speeds
(Part Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz. clock frequency RMII operation 50MHz 100ppm. clock frequency SMII operation 125MHz 100ppm. These signals that change both positive negative clock transitions.
Input (ns) Signal PCI-X Interface PCIXAD00:63 PCIXC3:0[BE3:0] PCIXParLow PCIParHigh PCIXFrame PCIXINT PCIXIRDY PCIXTRDY PCIXStop PCIXDevSel PCIXIDSel PCIXPErr PCIXSErr PCIXClk PCIXReset PCIXReq64 PCIXAck64 PCIXCap PCIX133Cap PCIXM66En PCIXReq0:5 PCIXGnt0:5 Ethernet Interface EMCRxD0:3 EMCRxDV EMCRxClk EMCRxErr EMCTxD0:3 EMCTxEn EMCTxClk EMCTxErr EMCCrS EMCCD EMCMDIO EMCMDClk 10.3 10.3 10.3 10.3 10.3 EMCMDClk EMCTxClk EMCRxClk EMCTxClk EMCTxClk EMCRxClk EMCRxClk async async async async async Note Note n/a) Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk PCIXClk async async Setup Time Hold Time (TIS min) (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
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PowerPC 440GP Embedded Processor Data Sheet
Specifications-All Speeds
(Part Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz. clock frequency RMII operation 50MHz 100ppm. clock frequency SMII operation 125MHz 100ppm. These signals that change both positive negative clock transitions.
Input (ns) Signal Setup Time Hold Time (TIS min) (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) 10.3 10.3 10.3 10.3 10.3 10.3 10.3 15.3 15.3 10.3 10.3 10.3 10.3 10.3 15.3 (minimum) 10.2 10.2 10.2 async async async async async EMCRxClk EMCTxClk Clock Notes
Ethernet RMII Interface EMC0RxD0:1 EMC0RxErr EMC0CrSDV EMC0TxD0:1 EMC0:1TxEn EMC1RxD0:1 EMC1RxErr EMC1CrSDV EMC1TxD0:1 EMCRefClk Ethernet SMII Interface EMC0:1RxD EMC0:1TxD IICxSClk IICxSDA UARTSerClk UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RI UART0_RTS UART1_Rx UART1_Tx UART1_DSR/CTS UART1_RTS/DTR Interrupts Interface IRQ00:12 JTAG Interface TRST EMCRxClk EMCRxClk EMCRxClk EMCTxClk EMCTxClk EMCRxClk EMCRxClk EMCRxClk EMCTxClk async
Internal Peripheral Interface
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PowerPC 440GP Embedded Processor Data Sheet
Specifications-All Speeds
(Part Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. PCI-X timings asynchronous operation 133MHz. PCI-X input setup time requirement 1.2ns 133MHz 1.7ns 66MHz. timings parentheses) asynchronous operation 66MHz. output hold time requirement 66MHz 33MHz. clock frequency RMII operation 50MHz 100ppm. clock frequency SMII operation 125MHz 100ppm. These signals that change both positive negative clock transitions.
Input (ns) Signal System Interface SysClk TmrClk SysReset Halt SysErr TestEn DrvrInh1:2 GPIO00:31 Trace Interface TrcClk TrcBS0:2 TrcES0:4 TrcTS0:6 10.3 10.3 10.3 10.3 10.3 10.3 async async async async async Setup Time Hold Time (TIS min) (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
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PowerPC 440GP Embedded Processor Data Sheet
Specifications-400, 466, 500MHz
Notes: PerClk rising edge package with 10pF load trails internal clock approximately 1.3ns.
Input (ns) Signal Setup Time Hold Time (TIS min) (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 (minimum) 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk Clock Notes
External Slave Peripheral Interface PerData00:31 PerAddr00:31 PerPar0:3 PerWBE0:3 PerCS0:7 PerOE PerWE PerBLast PerReady[RcvrInh] PerR/W DMAReq0:3 DMAAck0:3 EOT0:3/TC0:3 PerClk ExtReset HoldReq HoldAck ExtReq ExtAck BusReq PerErr PerClk PerClk PerClk PerClk PerClk PerClk
External Master Peripheral Interface
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PowerPC 440GP Embedded Processor Data Sheet
SDRAM Specifications
SDRAM controller times operation with internal clock signals generates MemClkOut0 from clock. clock internal signal that cannot directly observed. However MemClkOut0 same frequency clock signal phase with clock signal. Note: MemClkOut0 advanced with respect clock means SDRAM0_CLKTR programming register. typical system, users advance MemClkOut 90°. This depends specific application requires thorough understanding memory system general (refer SDRAM controller chapter PowerPC 440GP User's Manual). following sections, label MemClkOut0(0) refers MemClkOut0 when been phase-shifted, MemClkOut0(90) refers MemClkOut0 when been phase-advanced 90°. Advancing MemClkOut0 creates cycle setup time cycle hold time address control signals relation MemClkOut0(90). rising edge MemClkOut0(90) aligns with first rising edge signal. following data generated means simulation includes logic, driver, package RLC, lengths. Values calculated over best case worst case processes with speed, temperature, voltage follows: Best Case Fast process, -40°C, +1.9V Worst Case Slow process, +85°C, +1.7V Note: following tables timing diagrams, maximum values measured under worst case conditions. minimum values (best case) estimates based comparable timing similar chip different technology. signals terminated indicated figure below timing data following sections. SDRAM Signal Termination
MemClkOut0 10pF 10pF MemClkOut0 VDD/2
PPC440GP
Addr/Ctrl/Data/DQS
10pF
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PowerPC 440GP Embedded Processor Data Sheet
SDRAM Output Driver Specifications
Signal Path Write Data MemData00:07 MemData08:15 MemData16:23 MemData24:31 MemData32:39 MemData40:47 MemData48:55 MemData56:63 ECC0:7 DM0:8 MemClkOut0 MemAddr00:12 BA0:1 BankSel0:3 ClkEn0:3 DQS0:8 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 Output Current (mA) (maximum) (minimum)
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PowerPC 440GP Embedded Processor Data Sheet
SDRAM Write Operation
following diagram illustrates relationship among signals involved with write operation. SDRAM Write Cycle Timing
MemClkOut0
MemClkOut0(90)
Addr/Cmd MemData
Delay from rising edge MemClkOut0(0) rising/falling edge signal (skew) Setup time address command signals MemClkOut0(90) Hold time address command signals from MemClkOut0(90) Setup time data signals (minimum time data valid before rising/falling edge DSQ) Hold time data signals (minimum time data valid after rising/falling edge DSQ) Delay from rising/falling edge clock rising/falling edge
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PowerPC 440GP Embedded Processor Data Sheet
Notes: signals referenced MemClkOut0(0). Clock speed 133MHz. values table include cycle 133MHz (7.5ns 0.75 5.625 ns). obtain adjusted values lower clock frequencies, subtract 5.625 from values table cycle time lower clock frequency (TDS 5.625 0.75TCYC).
Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 (ns) Minimum Maximum 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25 6.25
Timing-DDR SDRAM
Notes: Clock speed 133MHz. referenced MemClkOut0(0). referenced MemClkOut0(90). obtain adjusted values lower clock frequencies, cycle time lower clock frequency subtract maximum (0.75TCYC TSKmax). obtain adjusted values lower clock frequencies, cycle time lower clock frequency minimum (0.25TCYC TSKmin).
Signal Name MemAddr00:12 BA0:1 BankSel0:3 ClkEn0:3 (ns) Minimum Maximum (ns) Minimum 4.425 4.425 4.425 4.425 4.425 4.425 4.425 (ns) Minimum 2.275 2.275 2.275 2.275 2.275 2.275 2.275
Timing-DDR SDRAM TSK, TSA,
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PowerPC 440GP Embedded Processor Data Sheet
Timing-DDR SDRAM
Notes: measured under worst case conditions. Clock speed values table 133MHz. time values table include cycle 133MHz (7.5ns 0.25 1.875 ns). obtain adjusted values lower clock frequencies, subtract 1.875 from values table cycle time lower clock frequency (e.g., 1.875 0.25TCYC).
Signal Names MemData00:07, MemData08:15, MemData16:23, MemData24:31, MemData32:39, MemData40:47, MemData48:55, MemData56:63, ECC0:7, Reference Signal DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 (ns) 1.375 1.375 1.375 1.375 1.375 1.375 1.375 1.375 1.375 (ns) 1.375 1.375 1.375 1.375 1.375 1.375 1.375 1.375 1.375
SDRAM Read Operation
following examples timing SDRAM read operations based relationship between incoming data clock signal. Since clock cannot directly observed, delay MemClkOut(0) relative clock (TMD) provided. internal Read Clock signal, like MemClkOut0, derived from clock delayed relative clock programming RDCT RDCD fields SDRAM0_TR1 register. delay programmed from cycle steps using RDCT. Setting RDCD results cycle delay plus value RDCT. delay Read Clock relative clock (TRD) shown below assumes programmable Read Clock delay zero. SDRAM MemClkOut0 Read Clock Delay
MemClkOut0(0) TMDmin 850ps TMDmax 2600ps
Read Clock TRDmin TRDmax 300ps
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PowerPC 440GP Embedded Processor Data Sheet
operation, following receipt address read command from PPC440GP, SDRAM generates data signals coincident with MemClkOut0. data latched into PPC440GP using signal that delayed cycle. order accommodate timing variations introduced system designs using this chip, three-stage data path shown below used eliminate metastability allow data sampling adjusted minimum latency. This adjustment requires programming Read Clock delay selection Stage Stage Stage data sampling RDSP. SDRAM Read Data Path
Package pins
RDSP
Stage
Stage
Stage
Data
Cycle Delay Clock
Programmed Read Clock Delay
Read Select (SDRAM0_TR1)
Timing: Input setup time 0.2ns Input hold time 0.1ns Propagation delay 0.6ns maximum
Flip-Flop Transparent Latch
Timing-DDR SDRAM TSIN TDIN
Notes: TSIN Delay from package Stage TDIN Delay from data package Stage Clock speed values table 133MHz. time values TSIN include cycle 133MHz (7.5ns 0.25 1.875 ns).
Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 TSIN (ns) minimum 2.775 2.775 2.775 2.775 2.775 2.775 2.775 2.775 2.775 TSIN (ns) maximum 3.775 3.775 3.775 3.775 3.775 3.775 3.775 3.775 3.775 Signal Name MemData00:07 MemData08:151 MemData16:23 MemData24:31 MemData32:39 MemData40:47 MemData48:55 MemData56:63 ECC0:7 TDIN (ns) minimum TDIN (ns) maximum
following examples, data strobes (DQS) data shown coincident. There actually slight skew specified SDRAM specifications, there additional skew loading signal routing. recommended that signal length eight signals matched.
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PowerPC 440GP Embedded Processor Data Sheet
Example data-to-PLB clock timing shown example below, then read clock delayed Stage data sampled (1). Except small, frequency memory systems with memory located physically close PPC440GP, unlikely that Stage data sampled. When data comes later, necessary sample Stage Stage data. (see Examples Another desired data-to-PLB timing allow Stage sampling buffer MemClkOut0 skew enough guarantee timing. this example 1.5ns worst case conditions. SDRAM Read Cycle Timing-Example
Data TSIN Stage
Data Stage TDIN
High
Data Stage
Data RDSP with
High
Clock
High Data RDSP
TSIN Delay from package Stage Propagation delay through TDIN Delay from data package Stage Propagation delay, Stage input RDSP input
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PowerPC 440GP Embedded Processor Data Sheet
Example this example Read Clock delayed almost cycle. Without ECC, Stage data sampled (2). enabled, Stage data must sampled (see Example this example, 1.5ns 4.3ns worst case conditions. SDRAM Read Cycle Timing-Example
Data TSIN
Stage Data Stage TDIN
High Data Stage
Clock Read Clock Delayed High Data Stage High Data RDSP with High
Data RDSP without
Data RDSP without
High
Propagation delay from Stage input RDSP input Propagation delay from Stage input RDSP input with
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PowerPC 440GP Embedded Processor Data Sheet
Example this example, enabled. This requires that Stage data sampled (3). disabled, system will still work, there will more latency before data sampled into RDSP. Again, 1.5ns 4.3ns worst case conditions. SDRAM Read Cycle Timing-Example
Data TSIN
Stage Data Stage TDIN
High Data Stage
Clock Read Clock Delayed High Data Stage High Data RDSP with High
Data Stage with
Data RDSP with
High
Propagation delay from Stage input RDSP input Propagation delay from Stage input RDSP input with
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PowerPC 440GP Embedded Processor Data Sheet
Initialization
PPC440GP provides option setting initial parameters based default values reading them from slave PROM attached IIC0 (see "EEPROM" below). Some default values altered strapping external pins (see "Strapping" below).
Strapping
While SysReset input (system reset), state certain pins read enable certain default initial conditions prior PPC440GP start-up. actual capture instant nearest reference clock edge before deassertion reset. These pins must strapped using external pull-up (logical pulldown (logical resistors select desired default conditions. They used strap functions only during reset. Following reset they used normal functions. following table lists strapping pins along with their functions strapping options:
Strapping Assignments
Function Option Ball Strapping (UART0_DCD) Bootstrap controller Disabled Enabled (UART0_DSR) IIC0 slave address that will respond with boot data 0x54 0x50
EEPROM
During reset, initial conditions other than those obtained from strapping pins read from device connected IIC0 port. de-assertion reset, bootstrap controller enabled, PPC440GP sequentially reads bytes from device IIC0 port uses first bytes SYS0 SYS1 registers accordingly. Otherwise, default values STRP0 STRP1 registers used initialization. initialization settings their default values covered detail PowerPC 440GP Embedded Processor User's Manual.
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PowerPC 440GP Embedded Processor Data Sheet
Revision
Date 08/07/2002 08/30/2002 09/11/2002 10/22/2002 11/20/2002 01/07/2003 01/22/2003 03/25/2003 06/16/2003 08/22/2003 01/21/2004 02/12/2004 05/12/2004 revision log. Change EMC0:1TxD0:1 EMC0:1TxEn from Update parts heat sink mounting information additional part numbers temperature range. Update timing data. Update PCI-X voltage specification. Correct description SysReset signal. Update SDRAM timing. Change setup specification from 3ns. Remove references 2xPLB SDRAM timing section. Update SDRAM timing section consistent 440GX presentation. Restore VDD/OVDD voltage sequence restriction. plastic package data update part number list. Contents Modification
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PowerPC 440GP Embedded Processor Data Sheet
Copyright International Business Machines Corporation 1999, 2004
Rights Reserved Printed United States America, 2004 following trademarks International Business Machines Corporation United States, other countries, both: Blue Logic PowerPC CoreConnect Logo
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information contained this document subject change withdrawal time without notice being provided basis without warranty indemnity kind, whether express implied, including without limitation, implied warranties non-infringement, merchantability, fitness particular purpose. products, services, programs discussed this document sold licensed under IBM's standard terms conditions, copies which obtained from your local representative. Nothing this document shall operate express implied license indemnity under intellectual property rights third parties. Without limiting generality foregoing, performance data contained this document determined specific controlled environment submitted formal test. Therefore, results obtained other operating environments vary significantly. Under circumstances will liable damages whatsoever arising resulting from document information contained herein.
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PowerPC® processor core operating 500MHz with 32KB D-caches On-chip SR

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