Abstract IDT75T54100 designed used applications that require high

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Binary Co-PROCESSOR Entries
Abstract
IDT75T54100 designed used applications that require high speed data searching such routers, high layer switching applications involved convergence voice, data video. IDT's Co-Processors (IPCs) expedite multi level routing (Internet Protocol) includes chip logic facilitate various types header lookups processing results. features this device address performance requirements communication systems, which require sustained bandwidth tens millions lookups second. IDT's Co-Processor designed provide scalable solution major bottlenecks facing bandwidth challenge Internet traffic.
Advance Information IDT75T54100
Features
Data Cells Binary content addressable memory 36/72/144/288 multiple width lookups sustained lookups second width lookups Synchronous pipeline operation Dual interface Cascadable devices with glue logic latency penalty Glueless interface standard ZBTor Synchronous Pipelined Burst SRAMs Boundary Scan JTAG Interface (IEEE 1149.1 compliant) 2.5V core power supply User selectable 3.3V 2.5V supply 1.5V match supply Packaged JEDEC standard, thermally enhanced, profile Ball Grid Array (BGA)
Overview
IDT's 75T54100 high performance pipelined, synchronous Co-Processor (IPC). utilizes content addressable memory (CAM) technology perform pattern recognition functions. Each location Data entry with total array size entries. IDT75T54100 72-bit bi-directional bus, which 16-bit multiplexed address 72-bit data that support million sustained searches second. This device developed wide range communication networking applications, giving ability support requirements multiple networks. IPC's used applications that require high speed data searching routers, high layer switching convergence voice, data, video. IDT's increases throughput demanding networking Internet systems. IDT75T54100 utilizes IDT's latest high-performance 0.18 CMOS processing technology packaged JEDEC Standard, thermally enhanced, profile, Ball Grid Array (BGA).
75T54100 S66BS304
2001
©2001 Integrated Device Technology, Inc. DSC-5324/00
IDT75T54100 Binary Co-Processor Entries
Advance Information Commercial Temperature Ranges
Block Diagram
CONFIGIN MATCHIN [6:0]
CONFIGOUT
Configuration Registers Control Circuits
RDACK
VALID
HITACK
CLK2X PHASEN
CCLK
REQSTB [3:0] Command [6:4]
INST Decode
Decode
INDX
[20:0]
Index
Request
REQDATA [71:0]
Address [15:0]
BYPASS
MATCHOUT
DATA [71:0]
Global Mask Registers
5324 Search Result Registers
TRST
JTAG
IDT75T54100 Binary Co-Processor Entries
Advance Information mercial Temperature Ranges
Datasheet Features
System Configurations Functional Highlights Signal Descriptions Pinout Operating Characteristics Register Description Configuration Registers Reply Width Registers (RWRs) Search Result Registers (SRRs) Global Mask Registers (GMRs) Description Command Format Select Request Format Index Format Additional Signals Initialization Operating Characteristics Timing Diagrams Sequence Diagrams JTAG Interface Specifications Package Diagram Outline Ordering Information
Figure 1.0B ASIC Co-Processor configuration
Functional Highlights
Data Array IDT75T54100 Data cell entries shown Fig. 1.1. data cell entries store making binary array CoProcessor. During lookup operation, data used along with Global Mask Register find match requested data word. Figure
Data
Network Interface
ASIC FPGA
Co-Processor
A5324
System Configurations
IDT75T54100 designed fulfill needs various types Networking systems. solutions requiring data searching such routers, network interface shown 1.0A realized. Here Co-Processor (IPC) interfaces directly ASIC/ FPGA lookups routes index associated SRAM device, that supplies next address SRAM Data ASIC. also provides required control signals directly hookup ZBTor Synchronous Pipeline Burst SRAM. Figure 1.0A ASIC Co-Processor SRAM configuration Interface Co-Processor utilizes dual interface consisting Request Index Bus. bi-directional Request functions multiplexed address data bus, which performs writing reading Co-Processor resources, well presenting lookup data device. Index independent unidirectional which drives result lookup index) either SRAM device ASIC. addition driving Index, also drives associated SRAM control signals (CE/OE, either ZBTor Synchronous Pipeline Burst SRAM devices. Reading data register entries will always result bits data driven Request Bus. Writes will also bits data. Command IDT75T54100 carries 7-bit Command Bus, which loads specific instructions into Co-Processor. These include: Read Write Read Write instruction placed Command operates specified data entry register. During initiation Read command, Request will driven with address, fixed number clock cycles later this same will driven with respective data back. During initiation Write command, Request will receive address during cycle followed respective data cycle. reads writes 72-bit entities.
IDT's also configured without using SRAM interface shown Fig. 1.0B Here IDT75T54100 processes lookups submitted controller feeds result directly back ASIC/ FPGA. this manner, full capabilities fully utilized without requiring external SRAM. provides user control associated handshake signals adapt either configuration.
Network Interface
ASIC FPGA
Co-Processor
Sync SRAM
A5324 drw02a
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System Configurations Functional Highlights
IDT75T54100 Binary Co-Processor Entries
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Functional Highlights continued
IDT75T54100 also provide address control signals read write associated SRAM memory. pipelines address from Request Index Bus, driving associated SRAM. ASIC/FPGA handles pipelining data from SRAM. SRAM Wait Read SRAM Wait Read Read instruction external SRAM that pipelined within series operations. standard Read instruction external SRAM requires read complete prior submitting next instruction. However, SRAM Wait Read instruction does require user wait Read complete. next instruction loaded sequentially following cycle. Lookup lookup requested 72-bit, 144-bit 288-bit widths. 36-bit lookup accomplished using GMRs refer application note (AN-270), "Implementing x36-bit Lookups". Command identifies specific registers used with particular lookup. instructions associated commands described "Command Format" "GMR Select" sections. Please refer these sections further definition instruction code. Width Capability IDT75T54100 capable performing lookups comparisons data structures bits, bits bits. internal memory bank device used three standard width arrays, shown Figure 1.2. x144 x288 Figure Registers IDT75T54100 utilizes registers provide additional features convenience. There four basic types registers supported: Configuration Registers Reply width Registers (RWRs) Search Result Registers (SRRs) Global Mask Registers (GMRs) GMRs provided support Lookup instructions mask individual bits during search. Initialization uses Configuration Registers define timing outputs SRAM interface configuration. Configuration registers also used specify certain parameters when IDT75T54100 used multiple implementation. Further details each type register their specific implementation discussed sections titled under their respective register type. Also refer "Command Format, Select" "Initialization" sections addressing setup these registers. SRAM Interface IDT75T54100 provides required address control signals glueless SRAM interface. When user reads from writes external SRAM, provides pipelined bypass path that takes Address bits Request drives them Index Bus. Refer Request Format Index Format more information. ASIC/FPGA handles pipelining data from SRAM. Control signal timing programmed accommodate standard SRAMs, well Synchronous Pipelined Burst SRAMs. More detailed information, along with configure this interface discussed "Initialization" section.
16KX
A5324
Functional Highlights
IDT75T54100 Binary Co-Processor Entries
Advance Information mercial Temperature Ranges
Signal Descriptions
Symbol Buses: Command Request Input Input/Output Three State Output Three State Input Command defines operation performed IPC. also specifies lookup type Global Mask Register select. qualified Request Strobe signal define valid operation. Request multiplexed address/data used perfo reads (and writes) from (to) IPC, present search data lookups. This used rive ress external SRAM, back okup result information directly IPC's controller. Bits [15:0] Index contain encoded location which compare found. This input signifies valid input request. active high signal that indicates start operation cycle, must active CLK2X cycles. Function Pins Description
REQDATA
INDX
Index
REQSTB
Request Strobe
SRAM Control: This active high signal that sent back with data being read from Request Data Bus, with data being read from associated external SRAM. case SRAM Read, RDACK sent with Index, cycles after Index efined Pipeline Delay (PD) field. depth expanded configuration, last (lowest priority) device system must have will drive RDACK signal. Refer System Configuration Register details bits. This active high signal that sent with Index, CLK2X cycles after Index defined Pipeline Delay (PD) field. depth expanded configuration, only last (lowest priority) device system must have will drive HITACK signal. This signal will driven there match, high match found. Refer System Configuration Register details bits. This active high signal that sent with Index, CLK2X cycles after Index defined Pipeline Delay (PD) field. depth expanded configuration, only last west priority) device syste must have will drive VALID signal. will driven high upon completion lookup, even lookup result hit. Refer System Configuration Register details bits. This active output signal that driven along with Index Bus. connected SRAM PBSRAM. depth expanded configuration, only last (lowest priority) device group must have will drive CE/OE signal. Refer System Configuration Register tails bit. This active output signal which driven along with Index bus. used assert external SRAM. depth expanded configuration, only last (lowest priority) device group must have will drive signal. Refer System Configuration Register details bit.
RDACK
Read Acknowledge
Output
HITACK
Match Acknowledge
Output
VALID
Valid Lookup
Output
Chip Enable/ Output Enable
Output Three State
Write Enable
Output Three State
Clock Initialization: CLK2X PHASEN Clock Input Clock Phase Enable Configuration Address Configuration Address Input Input inputs outputs referenced positive edge this clock. This signal used generate internal clock frequency CLK2X. similar external clock optionally generated clock external synchronous SRAM. This used Device internally power whenever held low. depth expanded configuration, only first device system needs high. This used power when active Device depth expanded nfig uration, CONFIGOUT signal cted CONFIGIN signal next subsequent downstream device. This must active (low) during power This will force outputs high impedence ndition, well clearing enable (EN) System Configuration Register. This function does initialize contents entries.
B5324
CONFIGIN
Input
CONFIGOUT
Ouput
Reset
Input
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Signal Descriptions Pinout
IDT75T54100 Binary Co-Processor Entries
Advance Information Commercial Temperature Ranges
Signal Descriptions continued
Symbol Function Pins Description Depth Expansion: Match Output Match Output active high signal that driven cycle before Index driven bus. This signal signifies that match occurred IPC. Match Output signal active high into Match Input line lower priority IPC(s).The Match Output signal reference 2.5V operating characteristic, regardless selected VDDQ. Match Input signal driven upstream Match Output signals. This indicates down stream IPCs that higher priority occurred. This will prevent lower priority from driving Index higher priority encountered match.
MATCHOUT
Output
MATCHIN JTAG Signals: TRST Power Supply: VDDQ VMATCH VDDQ Select Other:
Match Input
Input
Test Mode Select Test Data Input Test Data Output Test Clock JTAG Reset
Input Input Output Tristate Input Input
JTAG instruction input. This 1149 compliant Input levels same other input pins device. 2.5V 3.3V VDDQ This internal pullup JTAG data input. This internal pullup JTAG Data output pin. This driven high edge Test Clock. maximum 10Mhz test clock. This internal pullup Asynchronous JTAG Reset. This active signal that will reset only JTAG associated logic. This will have affect other functional logic. This internal pullup
Core Power Power Match Power Power Ground
Supply Supply Supply Input Supply
2.5V core power supply pins device 2.5V 3.3V supply voltages device 1.5V match supply voltage device This signal that defines output drive either 3.3V 2.5V. select 3.3V output drive VDDQ Select (Vss), 2.5V output drive VDDQ Select High (VDDQ). Common pins supply voltages
Connect
connect these pins This conne cted left floating connected minimize thermal impedance
B5324
Signal Descriptions Pinout
IDT75T54100 Binary Co-Processor Entries
Advance Information mercial Temperature Ranges
Configuration -304 Ball Grid Array
DATA
VDDQ
DATA
VMATCH
DATA
VMATCH VMATCH VMATCH
TRST
DATA DATA DATA VMATCH VDDQ
VDDQ DATA DATA
VMATCH VMATCH VMATCH
VMATCH
2.5V
DATA DATA DATA DATA DATA DATA DATA VDDQ
VMATCH VMATCH VMATCH
VMATCH
VDDQ
CONFIG
DATA DATA VDDQ DATA VDDQ VMATCH DATA DATA DATA DATA DATA DATA DATA DATA DATA
VDDQ VMATCH SELE VMATCH
VMATCH TCLK
RDACK
DATA
VALID
DATA VDDQ
DATA DATA VDDQ DATA
CONFIG
VDDQ
VMATCH VMATCH VMATCH
VMATCH VMATCH VMATCH
VDDQ
VDDQ DATA DATA REQSTB
INDX INDX
DATA DATA
75T54100
304-BGA
VDDQ
INDX INDX
INDX
CLK2X
MATCH
INDX
VDDQ
INDX INDX
PHA-
INDX
DATA DATA
INDX INDX
VDDQ DATA DATA
2.5V
INDX INDX VDDQ
VMATCH VMATCH VMATCH
VMATCH VMATCH VMATCH
DATA DATA VDDQ DATA DATA
INDX INDX INDX VDDQ
VDDQ
MATCH
DATA VDDQ
INDX
INDX
DATA DATA
DATA
MATCH
INDX INDX
DATA DATA VDDQ DATA VDDQ VMATCH DATA DATA DATA DATA DATA DATA
MATCH MATCH MATCH
VMATCH
VMATCH
VMATCH
INDX
DATA
DATA DATA DATA DATA DATA DATA DATA VDDQ
VMATCH VMATCH VMATCH
VMATCH
MATCH
DATA DATA DATA VMATCH VDDQ DATA
VDDQ DATA DATA DATA
VMATCH VMATCH VMATCH
VMATCH
MATCH
VDDQ
VMATCH VMATCH VMATCH
VMATCH
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Signal Descriptions Pinout
IDT75T54100 Binary Co-Processor Entries
Advance Information Commercial Temperature Ranges
Recommended Operating Conditions with VDDQ 2.5V
Symbol Parameter Core Supply Voltage Min. 2.375 1.425 2.375 -0.3
Recommended Operating Conditions with VDDQ 3.3V
Unit
C5324
Typ.
Max. 2.625 1.575 2.625 VDDQ +0.3(2) VDDQ +0.3
Symbol
Parameter Core Supply Voltage
Min. 2.375 1.425 3.135 -0.3
Typ.
Max. 2.625 1.575 3.465 VDDQ VDDQ
Unit
C5324
VMATCH Match Supply Voltage VDDQ Supply Voltage Ground Input High Voltage Inputs Input High Voltage Input Voltage
VMATCH Match Supply Voltage VDDQ Supply Voltage Ground Input High Voltage Inputs Input High Voltage Input Voltage
NOTES: (min.) -1.0V pulse width less than tCYC/2, once cycle. (max.) VDDQ+1.0V pulse width less than tCYC/2, once cycle.
NOTES: (min.) -1.0V pulse width less than tCYC/2, once cycle. (max.) VDDQ+1.0V pulse width less than tCYC/2, once cycle.
Absolute Maximum Ratings(1)
Symbol VTERM
(VDD)
Parameter Terminal Voltage with Respect VDDQ Terminal Voltage with Respect Input Terminal Voltage with Respect Terminal Voltage with Respect Temperature Under Bias Storage Temperature Power Dissipation Output Current
Commercial -0.5 3.575 -0.5 VDDQ +0.5 -0.5 VDDQ +0.5 -0.5 VDDQ +0.5 +125 +125
Unit
Recommended Operating Temperature Supply Voltage
Symbol Temperature Parameter Case Temperature Ambient Temperature Ground Core Supply Voltage Supply Voltage 3.3V VMATCH Match Supply Voltage 1.5V±75mV
C5324
Commercial 2.5V
Unit
VTERM(2)
(VDDQ)
VTERM(2)
(INPUTS)
VTERM
(I/O)
VDDQ
TBIAS TSTG IOUT
C5324
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. This steady-state parameter that applies after power supply reached nominal operating value. Power sequencing necessary; however, voltage input cannot exceed VDDQ during power supply ramp
Capacitance
+25°C, 1.0MHz)
Symbol CI/O Parameter(1) Input Capacitance Capacitance Conditions VOUT Max. Unit
C5324 tbl05
NOTE: This parameter guaranteed device characterization, production tested.
Operating Characteristic
IDT75T54100 Binary Co-Processor Entries
Advance Information mercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range
(VDD 2.5V ±5%, VDDQ= 2.5V VDDQ 3.3V
|ILI| |ILO 2.5V
aram eter Curre Curre Curre ltag ltag ltag ltag
Test Conditions 2.625V, 2.625V, tate 2.375V 2.375V 3.135V 3.135V
Unit
C5324
2.5V )(2) 3.3V 3.3V
NOTE: TMS, TDI, TCK, TRST pins will internally pulled actively driven application. MATCHOUT signal referenced 2.5V operating characteristics, regardless selected VDDQ.
Electrical Characteristics Over Operating Temperature Supply Voltage Range(1)
(VDD 2.5V ±5%, VDDQ= 2.5V VDDQ 3.3V ±5%)
Symbol IDD1 Parameter Operating Core Power Supply Current 3.3V VDDQ Supply IDD2 Operating Power Supply Current 2.5V VDDQ Supply IMATCH Operation Match Power Supply Current Test Conditions Outputs Open, 2.625V, VIL, fMAX(2) Outputs Open, 3.465V, VIL, f=fMAX(2) Outputs Open, 2.625V, VIL, f=fMAX(2) Outputs Open, MATCH 1.575V, VIL, f=fMAX(2) 66MLookups/sec 50MLookups/sec Unit
C5324
NOTES: values maximum guaranteed values. fMAX, inputs cycling maximum frequency.
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Operating Characteristics
IDT75T54100 Binary Co-Processor Entries
Advance Information Commercial Temperature Ranges
Register Description
IDT75T54100 utilizes registers provide additional features convenience. registers their respective addresses shown Table 2.0. There four basic types registers: Configuration Registers Reply Width Registers (RWRs) Search Result Registers (SRRs) Global Mask Registers (GMRs) These registers discussed following sections.
Table Register Addressing
Address 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 0000 1110 0000 1111 Register Identification Register Size Register Depth Expansion Register System Configuration Register Reply Width Register Reply Width Register Reply Width Register Reply Width Register Search Result Register Search Result Register Search Result Register Search Result Register Search Result Register Search Result Register Search Result Register Search Result Register Function Read only Read only Device Initialization Device Initialization Device Operation Device Operation Device Operation Device Operation Read only Read only Read only Read only Read only Read only Read only Read only
D5324
Address 0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101 0001 0110 0010 0000 0010 0001 0010 0100 0010 0101 0011 0000 0011 0001 0011 0010 0011 0011
Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register
Function Lookup Write Lookup Write Lookup Write Lookup Lookup Lookup Lookup Lookup Lookup Lookup Lookup Lookup Lookup Lookup Lookup
D5324
Register Description
IDT75T54100 Binary Co-Processor Entries
Advance Information mercial Temperature Ranges
Identification Register (IDR)
Address [0000 0000] Identification Register 32-bit read only register. information stored Identification Register encoded device during manufacturing. Bits used Revision code. first released revision code 75T54100 "0000 0001", this code will change with each revision. Bits 8-15 define Implementation number, 75T54100 code "0000 0001". Bits 16-31 designated IDT's manufacturers code, "0000 0000 1011 0011" assigned JEDEC. Figure 2.6a shows assignments Identification Register.
Depth Expansion Register (DER)
Address [0000 0010] Depth Expansion Register 32-bit read only register. information stored Depth Expansion Register hardware controlled user power CONFIGIN signal used Device depth expanded configuration, each device will have unique Device that represents position system. Bits used define position depth expansion. Bits 8-31 Reserved will read zero's. Figure 2.6c shows assignments Depth Expansion Register.
Figure 2.6a Format
5324
Figure 2.6c Format
D5324
NOTE: reserved bits read "0's".
Internal Test Register (ITR)
Address [0000 0001] Internal Test Register 32-bit read only register. information stored Internal Test Register encoded device during manufacturing used device internal operations only. There need user this register normal operation device. register read code will read following 0x0008 0040. Figure 2.6b shows Internal Test Register Format.
Figure 2.6b Format
Inte rnal ratio Only
D5324
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Configuration Registers
IDT75T54100 Binary Co-Processor Entries
Advance Information Commercial Temperature Ranges
Reply Width Registers (RWRs)
There four 64-bit read/write Reply Width Registers. four RWRs addresses listed Table 2.1. Each register divided into five fields. There field assigned each lookup widths shown Figure 2.6d. Bits [31:24] used 288-bit lookups; bits [7:0] used 144-bit lookups; bits [15:8] used 72-bit lookups. lower five bits requested Lookup width used specify Index bits [19:15] specify Lookup operation. other fields reserved, Reserved Bits [63:32] [23:16] need written proper operation device.
Figure 2.6d Format
D5324
NOTE: reserved bits should "0's".
During Lookup operation, bits [65:64] Request used select which four RWRs will supply information requested Lookup Index Bus. Table shows Reply Width Registers selected. multiple width data lookup i.e., 144/ 288, only last least significant) word Lookup data used define which use.
Table Addresses
Request Data Lookup Address 0000 0100 0000 0101 0000 0110 0000 0111 Register Reply Width Register Reply Width Register Reply Width Register Reply Width Register
D5324
IDT75T54100 Binary Co-Processor Entries
Advance Information mercial Temperature Ranges
System Configuration Register (SCR)
Address [0000 0011] System Configuration Register 40-bit read/write register divided into nine fields used configure IPC. defines system Pipeline Delay (PD), configuration (LC, Grp), SRAM configuration (SR, Enable (EN). These functions described below. Figure shows assignments System Configuration Register.
Figure 2.7- System Configuration Register Format
Reserved Reserved Reserved
D5324
Reserved Bits [39:32] These bits reserved future upgrades. These bits should "0". Enable [31]. This cleared when pulled low, which forces outputs Index into tri-state. Index remains tri-stated until enable "1". addition CE/OE, VALID, HITACK MATCHOUT signals will remain un-driven until "1". SRAM type [30]. This defines type SRAM driven IPC. this means that SRAM Index means that Synchronous SRAM Index Bus. Last SRAM [29]. defines which device group will drive signals associated SRAM. also defaults this device driving Index when there ongoing operation preventing Index from floating. This that last (lowest priority) device group sole device group have this set. group defined either single device multiple devices that hooked specific bank SRAM. Last [28]. defines which devices system will drive RDACK, VALID, HITACK signals. This device that last (lowest priority) device system sole device have this set. system have eight IPC's system.
Reserved Bits [27:12] These bits reserved future upgrades. These bits should "0". group Bits [11:5]. These seven bits allow user define groups within system. system have eight IPC's system. group defined either single device multiple devices that hooked specific bank SRAM. case single device (one group within system), bits [14:8] should "0". multiple devices, refer Initialization Application Note (AN-269) setting these seven bits. Reserved Bits [4:2] These bits reserved future upgrades. These bits should "0". Pipeline Delay Bits [1:0]. These bits allow user pipeline delay VALID HITACK signals. This will define number additional clock cycles after Index sent before VALID HITACK signals will driven. case SRAM Read, will also define when RDACK signal driven. Each pipeline delay consists CLK2X cycles. This allows user either receive these signals with Index delay these signals two, four CLK2X clock cycles after Index SRAM read cycle. Driven with Index pipeline delay CLK2X cycles) pipeline delays CLK2X cycles) pipeline delays CLK2X cycles)
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Configuration Registers
IDT75T54100 Binary Co-Processor Entries
Advance Information Commercial Temperature Ranges
Search Result Registers (SRRs)
Co-Processor contains eight read only Search Result Registers storage resulting Index search. Search Result Register contains information stored after Lookup completed. This information includes 16-bit Index result, Lookup Type, lookup resulted valid hit. Figure shows assignments SRR. Bits used Index associated search result. Bits 16-27 reserved these bits will return read command. Bits 28-30 define Lookup Type shown Table 2.2. used define valid detected, signals that Lookup resulted valid hit. user also read contents particular Search Result Register directly using address shown Table 2.3.
Table SRRs Addresses
Address 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 0000 1110 0000 1111 Register Search Result Register Search Result Register Search Result Register Search Result Register Search Result Register Search Result Register Search Result Register Search Result Register Function Read only Read only Read only Read only Read only Read only Read only Read only
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Figure Format
Valid
D5324
NOTE: reserved bits read "0's".
Table Lookup Type
Result Register [30:28] Lookup Type x288 Lookup Lookup x144 Lookup other combinations reserved
D5324
Search Result Registers used with Lookup instructions. During initiation Lookup instructions, INST bits [6:4] Command will identify which Result registers will used store resulted Index. Table shows Search Result Registers selected.
Search Result Registers
IDT75T54100 Binary Co-Processor Entries
Advance Information mercial Temperature Ranges
Global Mask Registers (GMRs)
There total fifteen read/write Global Mask Registers that used during Lookup Write operations. lookups this will enable compare look this bit, this becomes don't care lookup. writing data presented device data pins will written into desired location. data that already exists this stored location will remain unchanged. writes only will only GMRs Table shows mask functions Lookup Write operations. user also read contents particular Global Mask Register directly using address shown Table 2.5.
Table GMRs Addresses
Address 0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101 0001 0110 0010 0000 0010 0001 Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Global Mask Register Function Lookup Write Lookup Write Lookup Write Lookup Lookup Lookup Lookup Lookup Lookup Lookup Lookup Lookup Lookup Lookup Lookup
D5324
Table Mask Function
Operation Lookup Write Unaltered
D5324
0010 0100 0010 0101
Mask Values
Function Compare Don't Care Write
0011 0000 0011 0001 0011 0010 0011 0011
GMRs selected using bits [3:0] bits [6:4] Command Bus. Refer Command more detail. Table shows Global Mask Registers selected.
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Global Mask Registers
IDT75T54100 Binary Co-Processor Entries
Advance Information Commercial Temperature Ranges
Description
utilizes Command load specific operational instructions. Command 7-bit which used specify operation Co-Processor. utilizes interfaces data flow: Request Bus, Index Bus. Request 72-bit used reading writing entries presenting Lookup data device. Index 21-bit bus, which used drive result Lookup Index) either SRAM ASIC. Command Request Index Request Strobe used define start operation sequence. Please refer "Instruction/Command Timing Diagrams" which illustrates timing generic operation. Additional signals also provided initialization, SRAM controls depth expansion.
Table Instruction
[3:0] 0010 0011 0100 0101 1010 Instruction Lookup Performs lookup array.
x144 Lookup Performs x144 lookup array. Write Read Write Data cells, Write Registers, Write External SRAM Reads cells, Read Registers, Read External SRAM
x288 Lookup Performs x288 lookup array. This instruction allows direct access associated SRAM Index Bus. this case access core will made. access through this path will mimic same delays allow SRAM accesses pipelined with rest functions. other combinations reserved.
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1011
SRAM Wait Read
Command
Command used specify operation CoProcessor. divided into fields, illustrated 3.0. Instruction field (CMD[3:0]) used designate required Lookup, Write, Read SRAM Wait Read. Select field (CMD[6:4]) used access both Global Mask Register Search Result Register requested Lookup. Instruction Field Instruction field consists bits, defines commands shown Table 3.0. Lookup commands operational nature, whereas Read, Write SRAM Wait Read commands primarily used table maintenance. operational commands utilize additional bits Command define Search Result Register Global Mask Register, while maintenance commands ignore these additional fields. However, there's exception when doing Write Instruction Data Mask cells additional bits (CMD[0:4]) used select Global Mask Registers. with CMOS inputs these pins should always driven pulled up), never left floating. Select Field select field consists bits that define which Global Mask Register Search Result Register used. Table defines which GMRs selected each Lookup mode. Table defines which SRRs selected store Index result.
XXXX
Reserved
Figure Command Format
Select Instruction
E5324
Description Command Format
IDT75T54100 Binary Co-Processor Entries
Advance Information mercial Temperature Ranges
Select
Command bits [6:4] used functions. function specify which Global Mask Register(s) Write (Data/Mask) Lookup commands. other function specify which Search Result Register (SRR) will store resulting Index search. Command bits [6:4] sampled rising edge each CLK2X. Global Mask Register(s) selected CLK2X cycle, followed Search Result Registers CLK2X cycle. Global Mask registers used mask specified bits Request when performing lookups writes. 72-bit lookups there scenarios GMRs Mask), 144-bit lookups there scenarios 288-bit lookups there scenarios available. writes 72-bit only will GMRs only. Search Result Registers used store resulting Index successful lookup specified Command during Lookup command. subsequent Indirect Write Read) command specify which Search Result Register will supply address (Data/Mask) array.
Table Select
(2nd CLK2X rising edge)
Selected Mode [3:0] [6:4] Lookup 0010 x144 Lookup Selected (use Write) (use Write) (use Write) Mask Mask x288 Lookup 1010
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Selected
Table Select
(1st CLK2X rising edge)
Selected Mode [3:0] [6:4] Lookup 0010 x144 Lookup 0011 x288 Lookup 1010
0011
other combinations reserved Mask other combinations reserved
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Select
IDT75T54100 Binary Co-Processor Entries
Advance Information Commercial Temperature Ranges
Request
Request 72-bit bus. main funcitions supply data Lookup command. order data supplied 72-bit, 144-bit 288-bit Lookup commands specified Figure 3.1.
Figure 3.1Request Lookup Commands
Available Clk2x Cycles Lookup Available Clk2x Cycle Lookup Clk2x Clk2x Lookup
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Available Clk2x Cycle
Clk2x
Clk2x
other Read Write Commands, Request used specify address followed relevant data. Read Write commands Data cells, Mask cells Registers. format Request illustrated part Figure 3.2. Each fields described next page. SRAM Read, SRAM Write SRAM Wait Read commands, format Request illustrated bottom part Figure 3.1.
Figure Format Address Request
INSTRUCTION TYPE Read Writes Data entries Registers SRAM Read, Write Wait Read Reserved Reserved Select 0:Direct 1:Indirect Reserved Address Select Address Address
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Reserved
Device
Access Type
Device
Access Type
NOTE: Reserved bits should "0's".
Request Format
IDT75T54100 Binary Co-Processor Entries
Advance Information mercial Temperature Ranges
Device
This feature needed when using multiple IPCs depth expansion. Device defined power automatically assigned after Reset. Table shows which accessed using Device field. case Read IPC's, only IPC0 will drive Request Bus.
Table Select
Request Select Write Operation Masking
E5324
Table Device
Request Device Accessed
Direct/Indirect
"0", indicates that address Data array will come from Address field Request Data bus. "1", indicates that address Data array will come from Search Result Register specified Select field Request Bus.
other combinations reserved
E5324tbl
Select
This field only used indirect addressing, used specify which Search Result Register should used supply address Data array shown Table 3.9.
Table Select
Request Select other combinations reserved
E5324
Access Type
There three possible access types: Data array; SRAM; Register, specified Table 3.7.
Table Access Type
Request Access Type Internal Data Array External SRAM Reserved
E5324
Address
Select
This field only used specify which three GMRs will used write operation. There four possible options GMRs write operation, shown Table 3.8. Write operation, selected defines which bits array will updated. each selected that "1", data from Request corresponding this location will written into array. other bits selected that "0", data array corresponding this location will remain unchanged.
This field specifies address Access Type when using Direct addressing specified Direct/Indirect bit). address used access Data array, external SRAM, internal register. address decode internal registers found Table 2.0.
6.42
Request Format
IDT75T54100 Binary Co-Processor Entries
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Index
Index 21-bit divided into fields. consists following: ADDRESS; illustrated 3.4. ADDRESS Bits [15:0] This location where resulting Index placed from requested search. ADDRESS field contains encoded location which compare found Lookup command. used access corresponding associative memory external SRAM. When wide lookups performed, corresponding least significant bits will always zero (bit 144-bit, bits 288-bit). Bits [20:16] bits associated with Lookup requested. These five lower bits requested Lookup width that programmed Reply Width Registers. CONFIGOUT depth expanded configuration, CONFIGOUT signal used Device following downstream devices. CONFIGOUT signal connected CONFIGIN signal next subsequent downstream device system. CLK2X CLK2X clock that operates device. should twice lookup frequency (133 lookups/sec). Phase Enable (PHASEN) Phase Enable signal used synchronize internal clock clock external SRAM. Please refer Clock Timing diagram illustration this signal. Reset (RST) Reset signal initializes device. must low, remain CLK2X cycles after valid clock been generated device. Read Acknowledge signal (RDACK) Read Acknowledge signal used identify cycle time valid data being driven Read (IPC reg, Data Mask array, external SRAM) command. case SRAM Read, RDACK sent with Index, three Pipeline Delays (PD) after Index. Note: this signal generated conjunction with SRAM Wait Read command. Chip Enable/Output Enable signal (CE/OE) Chip Enable/Output Enable signal designed connected Single Cycle De-select pipelined burst SRAMs (PBSRAMs), SRAMs Double Cycle De-select pipelined burst SRAMs (PBSRAMs). Write Enable signal (WE) Write Enable signal designed connected directly PBSRAMs SRAMs. Valid signal (VALID) Valid signal indicates when Lookup command completed regardless whether lookup resulted match. timing this signal programmable based System Configuration Register. asserted early concurrently with Index, three Pipeline Delays (PD) after Index. Match Acknowledge signal (HITACK) Match Acknowledge signal indicates when Lookup command resulted match. timing this signal programmable based System Configuration Register. asserted early concurrently with Index, three Pipeline Delays (PD) after Index.
Figure Index
DDRE
E5324
Bypass Mode When instructing SRAM Write, SRAM Read, SRAM Wait Read, will grab bits [20:0] Request directly pass them bits [20:0] Index Bus. automatically adds appropriate number pipeline delays needed insure that instruction same pipeline delays other instruction.
Additional Signals
Match Output (MATCHOUT) Match Output signal used depth expanding multiple devices. driven cycle before Index driven, should connected Match Input lower priority devices. downstream devices this signal prevent them from driving Index Bus. Match Input (MATCHIN 0-6) There seven Match Input signals that correspond seven (possible) upstream devices. When using multiple depth expanded configuration, each upstream device must prevent lower priority downstream device from driving external SRAM (and control signals) match found lower priority higher priority device(s) when performing lookup operation. CONFIGIN CONFIGIN signal used Device Depth Expansion Register. This done power whenever held Low. Only first device system should have CONFIGIN signal high. depth expanded configuration, CONFIGIN signal connected CONFIGOUT signal previous upstream device system.
Index Format Additional Signals
IDT75T54100 Binary Co-Processor Entries
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Initialization
requires that Reset signal (RST) active (Low) upon power remain until both power supplies clock signals become stable. addition, power JTAG Reset (TRST) must also Low. will respond signal both asynchronous synchronous manner. Reset, will respond reset asynchronously tristating pins output pins, which prevents contention from occurring between devices another device. will come reset condition synchronously. requires Reset signal active (Low) CLK2X PHASEN signals stable thirty-two clock cycles insure proper initialization. internal logic dependent clock present device initialized. This will affect internal state machines certain registers. Cold Reset cold reset condition occurs whenever power applied IPC. this case will have defined data Data array. addition Depth Expansion Register, Global Mask Registers, Search Result Registers will also have undefined data. Reset affect Identification Size Registers. registers Data Array affected Cold Reset shown Table 4.0.
Reset reset condition occurs when reset pulled low, sometime after device been power sequencing taken place. should held clock cycles complete proper re-initialization. this case data memory corrupted. However state stored Depth Expansion Register, System Configuration Register must re-initialized. These registers will cleared application reset signal. After goes high wait sixteen CLK2X cycles allow Device Expansion Register re-configured, next re-initialize System Configuration Register desired state resume operation. registers Data Array affected Reset shown Table 4.1.
Table Condition after Reset
Array Register Depth Expansion Register Data Array Global Mask Registers Reply Width Registers System Configuration Register Search Results Registers Contents Must Re-programmed affected affected bits Must Re-programmed affected affected
F5324
Table Condition after Cold Reset
Array Register Depth Expansion Register Data Array Global Mask Registers Reply Width Registers System Configuration Register Search Results Registers Identification Register Size Register Contents Undefined Must programmed Undefined Must programmed Undefined Must programmed Undefined Must programmed Undefined affected
F5324
Identification Register Size Register
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Initialization
IDT75T54100 Binary Co-Processor Entries
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Initialization Sequence Single Device
Step After goes high wait CLK2X cycles allow internal circuitry configure Device Expansion Register. Step user must initially System Configuration Register start handshaking signals back ASIC/FPGA. This enables RDACK, HITACK VALID signals driven. Enable (EN) System Configuration Register initially reset zero. ASIC/ FPGA does require handshake signals during initialization then does have enabled until System Configuration Register configured. Step user must initialize entire Data array with 0's. should realized that entire array initialized known state false might realized un-initialized location. Step Global Mask Registers (GMRs) also have defined initialized state. user intends using GMRs then appropriate register(s) must initialized. user does intend using GMRs, initialization required. Step Reply Width Registers (RWRs) also have defined initialized state. there need these registers then user must initialize appropriate register(s). user does intend using RWRs, initialization required. Step final procedure update System Configuration Register enable device operation. Index will remain tri-state until System Configuration Register. After configured device will ready operation. Note: Search Result Registers will dynamically changing device used. fact Search Result Registers read only registers cannot initialized through write operation. important realize that these registers initializes random state should used until after they have been updated from previous Lookup operation. more depth procedure initialize single device multiple devices refer application note (AN-268) "Initialization 75T54100 Co-processor".
Table Initialization Sequence
Step Step Step Step Step Step Wait CLK2X cycles Designate Last setting Write Data Array Configure GMRs that used Configure RWRs needed Finish Configuration
F5324
Initialization
IDT75T54100 Binary Co-Processor Entries
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Electrical Characteristics
(VDD 2.5V +/-5%, 70°C)
Lookups Clock aram eters Output Param eters tCRD tCDC tCLZ(2) tCHZ(2) tCRA tCIV tCDV Param eters Hold aram eters
Lookups Unit
aram eter
ulse
Valid Data Data Chang Outp tive Data ctiv Valid atch Data Valid Data Valid
H5324
NOTES: Measured HIGH above below VIL.
Transition measured 200mV from steady-state. This parameter guaranteed device characterization, production tested. This parameter applies CE/OE, HITACK VALID signals.
Test Load
Test Conditions
(VDDQ 2.5V 3.3V)
Input Pulse Levels VDDQ 1.5ns (VDDQ/2) (VDDQ/2) Figure
H5324
Input Rise/Fall Times Input Timing Reference Levels
Output Timing Reference Levels Test Load
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Operating Characteristics
IDT75T54100 Binary Co-Processor Entries
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Clock Timing
(CLOCKs)
tCYC
CCL2X PHASEN
CCLK(1)
(Note
H5324 drw01
NOTES: CCLK internal signal seen user. Reset/Initialization Sequence Diagram reset.
Timing Diagrams
IDT75T54100 Binary Co-Processor Entries
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Instruction/Command Timing
(Instruction Timing)
CLK2X
CCLK
Note
Note
REQSTB
COMMAND
CMD[3:0]
Note
REGISTER
Note
CMD[6:4]
REGISTER
DATA
REQDATA
DATA
DATA
(Note
H5324d02
NOTES: CCLK internal signal seen user. Request Strobe needs High does initiate command. However time will sampled High will initiate command. Writes Lookups, Data ignored. Depending current following operations these signals driven High, Don't Care.
6.42
Timing Diagrams
IDT75T54100 Binary Co-Processor Entries
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Output Timing (with Read)
(IPC READ)
CLK2X
CCLK
REQSTB
CMD[3:0]
CMD[6:4]
tCRD (MAX.) Address tCLZ (MIN.) Read Data
tCHZ (MAX.)
REQDATA
tCDC (MIN.)
INDX
tCRACK (MAX.)
RDACK
tCRACK (MIN.) Don't Care Driven HIGH LOW, indeterminate state. impedance state.
H5324
Timing Diagrams
IDT75T54100 Binary Co-Processor Entries
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Output Timing (with SRAM)
(OUTPUT TIMING commands except Read Write)
tn+1
tn+2
tn+3
tn+4
tn+5
tn+6
tn+7
tn+8
tn+9
tn+10
CLK2X
CCLK(1)
tCIV (MAX.)
INDX
NOTE
VALID INDEX tCDC (MIN.)
NOTE
tCMDV (MAX.)
MATCHOUT
tCMDV
(MIN.)
tCDV (MAX.)
CE/OE(4)
tCDV tCDV
(MAX.) (MIN.)
NOTE tCDV
(MIN.)
(NOTE
SRAMDATA
SRAM READ WRITE DATA
tCRAK
(MAX.)
RDACK(7)
NOTE tCRAK (MIN.) tCDV (MAX.)
HITACK Pipeline Delay (PD) (NOTE
NOTE tCDC (MIN.)
(MAX.)
PD=0
PD=1
PD=2
PD=3
tCDV
VALID
NOTE tCDC (MIN.)
H5324
NOTES: CCLK internal signal seen user. Index driven indeterminate state. Signal will drive HIGH depending command; sequence diagram state. This will tied input input will tied LOW. Refer SRAM datasheet timing specifications. HITACK VALID signals valid based rising edge CLK2X time tCDV dependent Pipeline Delay (PD) value that programmed into System Configuration Register (SCR). These signals will drive CLK2X cycles. value shown clarity. Typically, would RDACK signal valid based rising edge CLK2X, time tCRAK, dependent Pipeline Delay (PD) value that programmed into System Configuration Register (SCR). This signal will drive CLK2X cycles. value shown clarity. Typically, would
6.42
Timing Diagrams
(Lookup SRAM Read Read Output Timing) tn+7 tn+4 tn+7 tn+3 tn+5 (SRAM rite Output ing) tn-2 tn-1
CLK2X
CCLK(1)
INDEX NOTE NOTE
INDX
VALID INDEX
NOTE
IDT75T54100 Binary Co-Processor Entries
MATCHOUT
CE/OE
(NOTE SRAM READ DATA
Output Timing (with Synchronous Pipeline Burst)
SRAMDATA
SRAM RITE DATA (NOTE
RDACK(7)
HITACK(6)
NOTE
VALID(6)
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NOTES: CCLK internal signal seen user. Index driven indeterminate state. Signal will drive HIGH depending command; sequence diagram state. This will tied input PBSRAM input will tied LOW. Refer SRAM datasheet timing specifications. HITACK VALID signals valid based rising edge CLK2X time tCDV dependent Pipeline Delay (PD) value that programmed into System Configuration Register (SCR). These signals will drive CLK2X cycles. value shown. Refer Output Timing (with SRAM) relative timing values. RDACK signal valid based rising edge CLK2X, time tCRAK, dependent Pipeline Delay (PD) value that programmed into System Configuration Register (SCR). This signal will drive CLK2X cycles. value shown clarity. Typically, would
Timing Diagrams
(RESET INITIALIZATION)
CLK2X
CCLK
IDT75T54100 Binary Co-Processor Entries
Complete Synchronous Reset Begin internal logic initialization (note
RST(1)
Reset/Initialization Sequence
CONFIGIN
I/Os Outputs driven HIGH impedance state (note
Cycles Required
CONFIGOUT
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Cycles Required I/Os Outputs driven HIGH impedance state (note
REQSTB
CMD[3:0]
RITE COMMAND
NEXT COMMAND
CMD[6:4]
REQDATA
CONFIGURATION REGISTER ADDRESS
RITE DATA Begin Initialization (note
NEXT COMMAND ADDRESS DATA
OUTPUT SIGNALS
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Sequence Diagrams
NOTES: Reset input, RST, must driven during power before driving clock inputs. After VDDQ supply ramps (stabilizes), I/O's outputs will driven high impedance state asynchronously. Synchronous reset internal logic specific registers begins after clock stabilization VDDQ supplies ramp operating levels. CLK2X cycles required fully reset internal logic registers. initialization begin after synchronous reset complete drives HIGH. Initialization details. output signals consist INDX, MATCHOUT, OE/CE, RDACK, HITACK VALID.
(IPC READ)
CLK2X
CCLK(1)
IDT75T54100 Binary Co-Processor Entries
REQSTB
next command cannot initiated until Read complete (see note
Read (Register, Data)
CMD[3:0]
READ COMMAND
NEXT COMMAND
CMD[6:4]
Read Data NOTE
REQDATA
READ ADDRESS
Turnaround Cycle
INDX
RDACK
HITACK
VALID
I5324
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Sequence Diagrams
NOTES: CCLK internal signal seen user. Index driven, indeterminate state. Commands initiated from ignored. next command initiated cycle after READ complete. This allows turnaround cycle Request Bus.
IDT75T54100 Binary Co-Processor Entries
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Write (Register, Data)
(IPC WRITE)
CLK2X
CCLK
REQSTB
NOTE
CMD[3:0]
WRITE COMMAND
NEXT COMMAND
CMD[6:4]
REQDATA
WRITE ADDRESS
WRITE DATA
NEXT COMMAND ADDRESS DATA
INDX
NOTE
RDACK
HITACK
VALID
I5324 drw03
NOTES: CCLK internal signal seen user. Index driven, indeterminate state. Next command initiated early cycle
6.42
Sequence Diagrams
(SRAM READ)
CLK2X
CCLK(1)
REQSTB
next command cannot initiated until Read complete. (see note NEXT COMMAND
SRAM Read (ZBT)
IDT75T54100 Binary Co-Processor Entries
CMD[3:0]
SRAM READ COMMAND
CMD[6:4]
REQDATA
READ ADDRESS
ADDRESS DATA NEXT COMMAND
INDX
NOTE NOTE INDEX
MATCHOUT
SRAM READ DATA
CE(4)
SRAM DATA
RDACK(5)
HITACK
VALID
I5324
Advance Information Commercial Temperature Ranges
Sequence Diagrams
NOTES: CCLK internal signal seen user. Commands initiated from ignored. next command initiated t14, following cycle after RDACK drives HIGH (Read complete). Index driven, indeterminate state. SRAM, input tied input driven CE/OE output. RDACK signal valid based rising edge CLK2X, time tCRAK, dependent Pipeline Delay (PD) value that programmed into System Configuration Register (SCR). This signal will drive CLK2X cycles. value shown clarity. Typically, would
(SRAM WRITE)
CLK2X
CCLK(1)
REQSTB
Note
MAND
SRAM Write (ZBT)
IDT75T54100 Binary Co-Processor Entries
CMD[3:0]
SRAM WRITE COMMAND
CMD[6:4]
REQDATA
NEXT COMMAND, ADDRESS DATA
INDX
NOTE
INDEX
NOTE
6.42
MATCHOUT
CE(4)
SRAM DATA
SRAM WRITE DATA
RDACK
HITACK
VALID
I5324
Advance Information mercial Temperature Ranges
Sequence Diagrams
NOTES: CCLK internal signal seen user. next command initiated dead cycles inserted because write commands require dead cycle before next instruction initiates, second cycle insures that contention occurs SRAM Data Bus. next command Read, Write SRAM Write, initiated cycle Index driven, indeterminate state. ZBT, tied LOW, input driven CE/OE output.
(SRAM Wait Read)
CLK2X
CCLK(1)
REQSTB
Next command initiated this cycle. (See note NEXT COMMAND
IDT75T54100 Binary Co-Processor Entries
CMD[3:0]
SRAM ACCESS COMMAND
SRAM Wait Read (ZBT)
CMD[6:4]
REQDATA
READ ADDRESS
ADDRESS DATA NEXT COMMAND
INDX
NOTE INDEX
NOTE
MATCHOUT
CE(4)
SRAM DATA
SRAM READ DATA
RDACK
HITACK(5)
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Sequence Diagrams
VALID(5)
I5324 NOTES: CCLK internal signal seen user. SRAM Wait Read command does require user wait until Read complete. next commands initiated early following cycle Index driven, indeterminate state. ZBT, input tied LOW, input driven CE/OE output. HITACK VALID signals valid based rising edge CLK2X time tCDV dependent Pipeline Delay (PD) value that programmed into System Configuration Register (SCR). These signals will drive CLK2X cycles. value shown. Refer Output Timing (with SRAM) relative timing values.
(SRAM READ)
CLK2X
CCLK(1)
REQSTB
next command cannot initiated until Read complete. (see note NEXT COMMAND
IDT75T54100 Binary Co-Processor Entries
SRAM Read (PBSRAM)
CMD[3:0]
SRAM READ COMMAND
CMD[6:4]
REQDATA
READ ADDRESS
ADDRESS DATA NEXT COMMAND
INDX
NOTE INDEX NOTE
MATCHOUT
6.42
OE(4)
SRAM DATA
SRAM READ DATA
RDACK(5)
HITACK
VALID
I5324
Advance Information mercial Temperature Ranges
Sequence Diagrams
NOTES: CCLK internal signal seen user. Commands initiated from ignored. next command initiated t14, following cycle after RDACK drives HIGH (Read complete). Index driven, indeterminate state. Synchronous Pipelined Burst SRAM, input tied LOW, ADSP tied HIGH, ADSC tied input driven CE/OE output. RDACK signal valid based rising edge CLK2X, time tCRAK, dependent Pipeline Delay (PD) value that programmed into System Configuration Register (SCR). This signal will drive CLK2X cycles. value shown clarity. Typically, would
(SRAM WRITE)
CLK2X
CCLK(1)
REQSTB
NOTE
NEXT COMMAND
IDT75T54100 Binary Co-Processor Entries
SRAM Write (PBSRAM)
CMD[3:0]
SRAM WRITE COMMAND
CMD[6:4]
REQDATA
NEXT MAND, ADDRESS DATA
INDX
NOTE
INDEX
NOTE
MATCHOUT
OE(4)
SRAM DATA
SRAM WRITE DATA
RDACK
HITACK
VALID
I5324
Advance Information Commercial Temperature Ranges
Sequence Diagrams
NOTES: CCLK internal signal seen user. next command initiated during cycle Write commands require dead cycle before next instruction initiates. Index driven, indeterminate state. -Synchronous Pipeline Burst SRAM, tied LOW, ADSP tied HIGH, ADSC tied LOW, input driven CE/OE output.
CLK2X
CCLK
REQSTB
Next command initiated this cycle. (See note
IDT75T54100 Binary Co-Processor Entries
CMD[3:0]
NEXT COMMAND
SRAM ACCESS COMMAND
D[6:4]
DATA
READ ADDRESS
ADDRESS DATA NEXT COMMAND
SRAM Wait Read (PBSRAM)
INDX
INDEX
NOTE
NOTE
ATCHO
6.42
OE(4
SRAM DATA
SRAM READ DATA
RDACK
HITACK
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VALID
Sequence Diagrams
NOTES: I5324 CCLK internal signal seen user. SRAM Wait Read command does require user wait until Read complete. next command SRAM Write, initiated during cycle dead cycles inserted insure that contention occurs SRAM Data Bus. other commands initiated cycle Index driven, indeterminate state. Synchronous Pipeline Burst SRAM, input tied Low, ADSP tied HIGH, ADSC tied LOW, input driven CE/OE output. HITACK VALID signals valid based rising edge CLK2X time tCDV dependent Pipeline Delay (PD) value that programmed into System Configuration Register (SCR). These signals will drive CLK2X cycles. value shown. Refer Output Timing (with SRAM) relative timing values.
LOOKUP)
CLK2X
CCLK
REQS
NOTE NEXT COMMAND
IDT75T54100 Binary Co-Processor Entries
D[3:0]
LOOKUP COMMAND
CMD[6:4]
REGISTER
REGISTER
NEXT REGISTER
NEXT REGISTER
BITS 71:0
NEXT COMMAND ADDRESS DATA
MATCH DATA NOTE INDEX NOTE
72-Bit Lookup (with SRAM)(5)
INDX
ATCHOUT
SRAM READ DATA
CE(4)
DATA
RDACK
HITACK
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VALID
Sequence Diagrams
I5324 NOTES: CCLK internal signal seen user. Next command initiated during cycle Index driven, indeterminate state. SRAM, input tied input driven CE/OE output. Synchronous Pipelined Burst SRAM sequence Output Timing diagram (with PBSRAM). HITACK VALID signals valid based rising edge CLK2X time tCDV dependent Pipeline Delay (PD) value that programmed into System Configuration Register (SCR). These signals will drive CLK2X cycles. value shown. Refer Output Timing (with SRAM) relative timing values.
(144 LOOKUP)
CLK2X
CCLK
REQSTB
NOTE NEXT COMMAND
IDT75T54100 Binary Co-Processor Entries
CMD[3:0]
LOOKUP COMMAND
CMD[6:4]
REGISTER
REGISTER
NEXT REGISTER
NEXT REGISTER
REQDATA
BITS 144:72
BITS 71:0
NEXT COMMAND ADDRESS DATA
MATCH DATA NOTE
INDX
NOTE
144-Bit Lookup (with SRAM)(5)
MATCHOUT
6.42
CE(4)
SRAM DATA
SRAM READ DATA
RDACK
HITACK
VALID
I5324
Advance Information mercial Temperature Ranges
Sequence Diagrams
NOTES: CCLK internal signal seen user. Next command initiated during cycle Index driven, indeterminate state. SRAM, input tied input driven CE/OE output. Synchronous Pipelined Burst SRAM sequence Output Timing diagram (with PBSRAM). HITACK VALID signals valid based rising edge CLK2X time tCDV dependent Pipeline Delay (PD) value that programmed into System Configuration Register (SCR). These signals will drive CLK2X cycles. value shown. Refer Output Timing (with SRAM) relative timing values.
(288BIT LOOKUP)
CLK2X
CCLK(1)
REQSTB
NOTE
IDT75T54100 Binary Co-Processor Entries
CMD[3:0]
NEXT COMMAND
LOOKUP COMMAND
CMD[6:4]
REGISTER
REGISTER
NEXT REGISTER
NEXT REGISTER
REQDATA
MATCH DATA NOTE INDEX
BITS 287:216 BITS 71:0 NEXT COMMAND ADDRESS DATA
BITS 215:144
BITS 143:72
288-Bit Lookup (with SRAM)(5)
INDX
NOTE
MATCHOUT
SRAM READ DATA
CE(4)
SRAM DATA
RDACK
HITACK(6)
VALID(6)
I5324
Advance Information Commercial Temperature Ranges
Sequence Diagrams
NOTES: CCLK internal signal seen user. Next command initiated during cycle Index driven, indeterminate state. SRAM, input tied input driven CE/OE output. Synchronous Pipelined Burst SRAM sequence Output Timing diagram (with PBSRAM). HITACK VALID signals valid based rising edge CLK2X time tCDV dependent Pipeline Delay (PD) value that programmed into System Configuration Register (SCR). These signals will drive CLK2X cycles. value shown. Refer Output Timing (with SRAM) relative timing values.
lookup)
(IPC WRITE)
CLK2X
CCLK(1)
REQSTB
NOTE WRITE WRITE COMMAND COMMAND NEXT COMMAND
IDT75T54100 Binary Co-Processor Entries
CMD[3:0]
72-Bit LOOKUP COMMAND
CMD[6:4]
REGISTER REGISTER
REGISTER REGISTER
REQDATA
WRITE ADDRESS WRITE DATA
72-BIT MATCH DATA
NEXT COMMAND, ADDRESS DATA
INDX
NOTE NOTE
MATCHOUT
Lookup Followed Write (with SRAM)(5)
6.42
SRAM READ DATA
CE(4)
SRAM DATA
RDACK
HITACK(6)
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VALID(6)
Sequence Diagrams
I5324 NOTES: CCLK internal signal seen user. Next command initiated during cycle Index driven, indeterminate state. SRAM, input tied input driven CE/OE output. Synchronous Pipelined Burst SRAM sequence Output Timing diagram (with PBSRAM). HITACK VALID signals valid based rising edge CLK2X time tCDV dependent Pipeline Delay (PD) value that programmed into System Configuration Register (SCR). These signals will drive CLK2X cycles. value shown. Refer Output Timing (with SRAM) relative timing values.
IDT75T54100 Binary Co-Processor Entries
Advance Information Commercial Temperature Ranges
JTAG Interface Specification
tJCYC
tJCL
tJCH
Device Inputs(1)/ TDI/TMS Device Outputs(2)/ tJDC
tJRSR
tJCD
M5324
TRST(3) tJRST
NOTES: Device inputs device inputs except TDI, TRST. Device outputs device outputs except TDO. During power TRST should driven low.
JTAG Electrical Characteristics(1,2,3,4)
Symbol tJCYC tJCH tJCL tJRST tJRSR tJCD tJDC Parameter JTAG Clock Input Period JTAG Clock HIGH JTAG Clock JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery JTAG Data Output JTAG Data Output Hold JTAG Setup JTAG Hold Min.
Max.
Units
I5324
Scan Register Sizes
Register Name Instruction (IR) Bypass (BYR) JTAG Identification (JIDR) Boundary Scan (BSR) Size Note
I5324
3(1) 3(1)
NOTE: Boundary Scan Descriptive Language (BSDL) file this device available contacting your local sales representative.
NOTES: Guaranteed design. Test Load (stated earlier document) external output signals. Refer Test Conditions stated earlier this document. JTAG operations occur speed (10MHz). base device speed specified this datasheet.
JTAG Interface Specification
IDT75T54100 Binary Co-Processor Entries
Advance Information mercial Temperature Ranges
JTAG Identification Register Definitions
Instruction Field Revision Number (31:28) Device (27:12) JEDEC (11:1) Register Indicator (Bit Value 0x200 0x33 Reserved version number Defines part number Allows unique identification device vendor Indicates presence register
I5324
Description
Available JTAG Instructions
Instruction EXTEST Description Forces contents boundary scan cells onto device outputs Places boundary scan register (BSR) between TDO. Places boundary scan register (BSR) between TDO. SAMPLE allows data from device inputs outputs(1) captured boundary scan cells shifted serially through TDO. PRELOAD allows data input serially into boundary scan cells TDI. Loads JTAG register (JIDR) with vendor code places register between TDO. Places bypass register (BYR) between TDO. Forces device output drivers High-Z state.
OPCODE 0000
SAMPLE/PRELOAD
0001
DEVICE_ID HIGHZ RESERVED RESERVED RESERVED RESERVED CLAMP RESERVED UNUSED UNUSED UNUSED VALIDATE UNUSED BYPASS
0010 0011 0100
Several combinations reserved. codes other than those identified EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP, VALIDATE BYPASS instructions.
0101 0110 0111
Uses BYR. Forces contents boundary scan cells onto device outputs. Places bypass register (BYR) between TDO. Same above. unused instructions behaviorally equivalent BYPASS instruction IEEE std. 1149.1 specification. However, user advised explicit BYPASS instruction, internal usage these currently unused instructions could possibly vary future implementations device. Automatically loaded into instruction register whenever controller passes through CAPTURE-IR state. lower bits '01' mandated IEEE std. 1149.1 specification. Same above. BYPASS instruction used truncate boundary scan register single length.
1000 1001 1010 1011 1100 1101 1110 1111
I5324
NOTES: Device outputs device outputs except TDO. Device inputs device inputs except TDI, TMS, TRST.
6.42
JTAG Interface Specification
IDT75T54100 Binary Co-Processor Entries
Advance Information Commercial Temperature Ranges
Package Diagram Outline Ball Grid Array
Package Diagram Outline
IDT75T54100 Binary Co-Processor Entries
Advance Information mercial Temperature Ranges
Ordering Information
Device Type Power Speed Package
BS304
Ball Grid Array (BGA)
Mega Lookups second
75T54100
L5324
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
SALES: 800-345-7015 408-727-6116 fax: 408-492-8674 www.idt.com
6.42
Tech Support: ipchelp@idt.com 800-754-4555
logo registered trademark Integrated Device Technology, Inc.
Ordering Information
IDT75T54100 Binary Co-Processor Entries
Advance Information Commercial Temperature Ranges
Revision History
DATE
05/04/2001
PAGES
DESCRIPTION
Advance Information Datasheet, Public Release
Revision History

Abstract IDT75T54100 designed used applications that require high

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