Features Features Highly Predictable Performance with Percent Aut

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Features Features Highly Predictable Performance with Percent Aut

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Military Field Programmable Gate Arrays
Features Features
Highly Predictable Performance with Percent Automatic Placement Routing Device Sizes from 1200 10,000 gates 25,000 equivalent gates) Fast, Low-Skew Clock Networks User-Programmable Pins More Than Macro Functions Replaces Packages Replaces 20-pin Packages 1153 Dedicated Flip-Flops Drive Devices Available DESC CQFP CPGA Packaging Nonvolatile, User Programmable Logic Fully Tested Prior Shipment
Product Family Profile
Family Device Capacity Gate Array Equivalent Gates Equivalent Gates Equivalent Packages gates) 20-Pin Equivalent Packages (100 gates) Logic Modules S-Modules C-Modules Flip-Flops (maximum) User I/Os (maximum) Packages1 CPGA CQFP Performance System Speed (maximum) count) A1425A 2500 6250 A1460A 6000 15,000
Highest-Performance, Highest-Capacity FPGA Family System Performance over Military Temperature Low-Power 0.8-micron CMOS Technology
Features
Best-Value, High-Capacity FPGA Family System Performance over Military Temperature Low-Power 1.0-micron CMOS Technology
Features
Lowest-Cost FPGA Family System Performance over Military Temperature Low-Power 1.0-micron CMOS Technology
A14100A 10,000 25,000 1377 1493 A1240A 4000 10,000 A1280A 8000 20,000 1232
A1010B 1200 3000 A1020B 2000 6000
Note:
Product Plan page package availability.
1995 Actel Corporation
High-Reliability, Low-Risk Solution
Actel builds most reliable field programmable gate arrays (FPGAs) industry, with overall antifuse reliability ratings less than Failures-In-Time (FITs), corresponding useful life more than years. Actel FGPAs have been production proven, with more than five million devices shipped more than trillion antifuses manufactured. Actel devices fully tested prior shipment, with outgoing defect level only ppm. (Further reliability data available "Actel Reliability Report.")
Percent Tested
Fabrication using low-power CMOS process means cooler junction temperatures. Actel's non-PLD architecture delivers lower dynamic operating current. reliability tests show very failure rate FITs 90°C junction temperature with degradation performance. Special stress testing wafer test eliminates infant mortalities prior packaging.
Security Risk-Reverse engineering programmed
Device functionality fully tested before shipment during device programming. Routing tracks, logic modules, programming, debug, test circuits percent tested before shipment. Antifuse integrity also tested before shipment. Programming algorithms tested when device programmed using Actel's Activator® Activator programming stations.
Benefits
Cost Risk-Once have Designer/Designer
Actel devices from optical electrical data extremely difficult. Programmed antifuses cannot identified from photograph using SEM. antifuse cannot deciphered either electrically microprobing. Each device silicon signature that identifies origins, down wafer fabrication facility.
Testing Risk-Unprogrammed Actel parts fully tested factory. This includes logic modules, interconnect tracks, I/Os. performance ensured special speed path tests, programming circuitry verified test antifuses. During programming process, algorithm ensure that antifuses correctly programmed. addition, Actel's Actionprobe® diagnostic tools allow percent observability internal nodes check debug your design.
AdvantageSystem, Actel's software programming package, produce many chips like just cost device itself, with charges your development budget every time want design.
Time Risk-After entering your design, placement
Actel FPGA Description
routing automatic, programming device takes only about minutes average design. save time design entry process using tools that familiar you. Action Logic System software interfaces with popular packages such Cadence, Mentor Graphics, OrCAD, Viewlogic, running platforms such Sun, addition, synthesis capability provided with support synthesis tools from Synopsys, IST, Exemplar, DATA I/O.
Reliability Risk-The PLICE® antifuse one-time
Actel families FPGAs offer variety packages, speed/performance characteristics, processing levels high-reliability military applications. Devices implemented silicon gate, two-level metal CMOS process, utilizing Actel's PLICE antifuse technology. This unique architecture offers gate array flexibility, high performance, quick turnaround through user programming. Device utilization typically percent available logic modules. Actel devices also provide system designers with on-chip diagnostic probe/debug capability, allowing user observe percent nodes within design, even while device operating in-system. Actel devices include on-chip clock drivers hard-wired distribution network. User-definable I/Os capable driving both CMOS drive levels. Available packages military Ceramic Quad Flat Pack (CQFP) Ceramic Grid Array (CPGA). Product Plan page 2-293 details.
programmable, nonvolatile connection. Since Actel devices permanently programmed, downloading from EPROM SRAM storage required. Inadvertent erasure impossible, there need reload program after power disruptions. Both PLICE antifuses base process radiation tolerant.
Arrays
Actel FPGAs supported Actel Designer Series, which offers automatic user-definable assignment, validation electrical design rules, automatic placement routing, timing analysis, user programming, debug/diagnostic probe capabilities. Designer Series fully supports schematic capture backannotated simulation through design kits Cadence, Mentor Graphics, OrCAD, Viewlogic. Synthesis supported with kits with synthesis tools from Synopsys, IST, Exemplar, DATA I/O. Also available FPGA fitter (ACTmap) that provides logic synthesis optimization from language VHDL description inputs. FPGA macro generator (ACTgen) provided, allowing user easily create higher-level functions such counters adders. Finally, ChipEdit graphical/visual design tool that allows user modify automatic place route results.
Description
Description
family second-generation Actel FPGA family. This family offers best-value, high-capacity devices, ranging from 4,000 8,000 gates, with system performance over military temperature range. devices have routed array clock distribution networks. devices manufactured using micron CMOS technology.
Description
family first Actel FPGA family first antifuse-based FPGA. This family offers lowest-cost logic integration, with devices ranging from 1,200 2,000 gates, with system performance over military temperature range. devices have routed array clock distribution network. devices manufactured using micron CMOS technology.
family third-generation Actel FPGA family. This family offers highest-performance highest-capacity devices, ranging from 2,500 10,000 gates, with system performance over military temperature range. devices have four clock distribution networks, including dedicated array clocks. addition, family offers highest I/O-to-gate ratio available. devices manufactured using micron CMOS technology.
Military Device Ordering Information
A14100
Application (Temperature Range) Commercial +70°C) Military (-55 +125°C) MIL-STD-883 Class Extended Flow (Space Level) Package Lead Count Package Type Ceramic Quad Flatpack (CQFP) Ceramic Grid Array (CPGA) Speed Grade Standard Speed Approximately faster than Standard Device Revision Part Number A1010 A1020 A1240 A1280 A1425 A1460 A14100
1200 Gates-ACT 2000 Gates-ACT 4000 Gates-ACT 8000 Gates-ACT 2500 Gates-ACT 6000 Gates-ACT 10,000 Gates-ACT
DESC SMD/Actel Part Number Cross-Reference
Actel Part Number (Gold Leads) A1010B-PG84B A1010B-1PG84B A1020B-PG84B A1020B-1PG84B A1020B-CQ84B A1020B-1CQ84B A1240A-PG132B A1240A-1PG132B A1280A-PG176B A1280A-1PG176B A1280A-CQ172B A1280A-1CQ172B A1425A A1460A A14100A DESC (Gold Leads) 5962-9096403MXC 5962-9096404MXC 5962-9096503MUC 5962-9096504MUC 5962-9096503MTC 5962-9096504MTC 5962-9322101MXC 5962-9322102MXC 5962-9215601MXC 5962-9215602MXC 5962-9215601MYC 5962-9215602MYC DESC (Solder Dipped) 5962-9096403MXA 5962-9096404MXA 5962-9096503MUA 5962-9096504MUA 5962-9096503MTA 5962-9096504MTA 5962-9322101MXA 5962-9322102MXA 5962-9215601MXA 5962-9215602MXA 5962-9215601MYA 5962-9215602MYA
Arrays
Product Plan
Speed Grade Application
Family
A1425A Device 132-pin Ceramic Quad Flatpack (CQFP) 133-pin Ceramic Grid Array (CPGA) A1460A Device 196-pin Ceramic Quad Flatpack (CQFP) 207-pin Ceramic Grid Array (CPGA) A14100A Device 256-pin Ceramic Quad Flatpack (CQFP) 257-pin Ceramic Grid Array (CPGA)
Speed Grade
Application
Family
A1240A Device 132-pin Ceramic Grid Array (CPGA) A1280A Device 172-pin Ceramic Quad Flatpack (CQFP) 176-pin Ceramic Grid Array (CPGA)
Speed Grade
Application
Family
A1010B Device 84-pin Ceramic Grid Array (CPGA) A1020B Device 84-pin Ceramic Quad Flatpack (CQFP) 84-pin Ceramic Grid Array (CPGA)
Applications: Commercial Military MIL-STD-883 Extended Flow Availability:
Available Speed Grade: Approx. faster than Standard Planned Planned
Device Resources
User I/Os FPGA Device Type A1425A A1460A A14100A Logic Modules 1377 Gate Array Equivalent Gates 2500 6000 10,000 CQFP 132-pin 196-pin 256-pin 133-pin CPGA 207-pin 257-pin
Device Resources
User I/Os FPGA Device Type A1240A A1280A Logic Modules 1232 Gate Array Equivalent Gates 4000 8000 CQFP 172-pin CPGA 132-pin 176-pin
Device Resources
User I/Os FPGA Device Type A1010B A1020B Logic Modules Gate Array Equivalent Gates 1200 2000 CQFP 84-pin CPGA 84-pin
Arrays
Description
Clock (Input)
MODE
Mode (Input)
only. Clock input global clock distribution network. Clock input buffered prior clocking logic modules. This also used I/O.
CLKA Clock (Input)
MODE controls diagnostic pins (DCLK, PRA, PRB, SDI). When MODE HIGH, special functions active. When MODE LOW, pins function I/Os.
Connection
only. Clock input global clock distribution networks. Clock input buffered prior clocking logic modules. This also used I/O.
CLKB Clock (Input)
This connected circuitry within device.
Probe (Output)
only. Clock input global clock distribution networks. Clock input buffered prior clocking logic modules. This also used I/O.
DCLK Diagnostic Clock (Input)
Clock input diagnostic probe device programming. DCLK active when MODE HIGH. This functions when MODE LOW.
Ground
Probe used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when debugging been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. accessible when MODE HIGH. This functions when MODE LOW.
Probe (Output)
supply voltage.
HCLK Dedicated (Hard-wired) Array Clock (Input)
only. Clock input sequential modules. This input directly wired each S-module offers clock speeds independent number S-modules being driven. This also used I/O.
Input/Output (Input, Output)
Probe used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when debugging been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. accessible when MODE HIGH. This functions when MODE LOW.
Serial Data Input (Input)
functions input, output, tristate, bidirectional buffer. Input output levels compatible with standard CMOS specifications. Unused pins automatically driven LOW.
IOCLK Dedicated (Hard-wired) Clock (Input)
Serial data input diagnostic probe device programming. active when MODE HIGH. This functions when MODE LOW.
Supply Voltage
only. Clock input modules. This input directly wired each module offers clock speeds independent number modules being driven. This also used I/O.
IOPCL Dedicated (Hard-wired) Preset/Clear (Input)
HIGH supply voltage.
Programming Voltage
only. Supply voltage used device programming. This must connected during normal operation.
Programming Voltage
only. input preset clear. This global input directly wired preset clear inputs registers. This functions when preset clear macros used.
Supply voltage used device programming. This must connected during normal operation.
Programming Voltage
only. Supply voltage used device programming. This must connected during normal operation.
Actel Military Product Flow
Step Screen Internal Visual Temperature Cycling Constant Acceleration Seal Fine Gross Visual Inspection Pre-burn-in Electrical Parameters Burn-in Test Interim (Post-burn-in) Electrical Parameters Percent Defective Allowable Final Electrical Test Static Tests 25°C (Subgroup Table 5005) -55°C +125°C (Subgroups Table 5005) Dynamic Functional Tests 25°C (Subgroup Table 5005) -55°C +125°C (Subgroups Table 5005) Switching Tests 25°C (Subgroup Table 5005) 11.0 Qualification Quality Confirmation Inspection Test Sample Selection (Group External Visual 5005 833-Class Method 2010, Test Condition 1010, Test Condition 2001, Test Condition (min), Orientation Only 1014 100% 100% 2009 accordance with Actel applicable device specification 1015 Condition hours 125°C Min. accordance with Actel applicable device specification accordance with Actel applicable device specification 100% 100% 100% 100% 100% 100% Lots 100% 100% 100% 100% final test) 833-Class Requirement 100% 100% 100% Military Datasheet Requirement 100% 100% 100%
10.0
100%
100%
100% Lots
100%
12.0
2009
100%
Actel specification
Arrays
Actel Extended Flow
Screen Wafer Acceptance3
Method 5007 with step coverage waiver 2011, condition 2010, condition 1010, condition 2001, condition (min), orientation only 2009 2020, condition 2012 accordance with Actel applicable device specification 1015, condition hours 125°C minimum accordance with Actel applicable device specification 1010, condition hours 150°C minimum accordance with Actel applicable device specification functional parameters 25°C accordance with Actel applicable device specification 5005 5005
Requirement Lots Sample 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% Lots 100% 100%
Destructive In-Line Bond Pull4 Internal Visual Serialization Temperature Cycling Constant Acceleration Visual Inspection Particle Impact Noise Detection Radiographic Pre-burn-in Test Burn-in Test Interim (Post-burn-in) Electrical Parameters Reverse Bias Burn-in Interim (Post-burn-in) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test Static Tests 25°C (Subgroup Table1) -55°C +125°C (Subgroups Table
Dynamic Functional Tests 5005 25°C (Subgroup Table 5005 -55°C +125°C (Subgroups Table Switching Tests 25°C (Subgroup Table 5005) Seal a.Fine b.Gross Qualification Quality Conformance Inspection Test Sample Selection External Visual 5005 2009 5005 1014
100%
100% 100%
Group Group 100%
Note:
Actel offers Extended Flow order satisfy those customers that require additional screening beyond requirements MIL-STD-883, Class Actel compliant requirements MIL-STD-883, Paragraph 1.2.1, MIL-I-38535, Appendix Actel offering this extended flow incorporating majority screening procedures outlined Method 5004 MIL-STD-883 Class exceptions Method 5004 shown notes below. Method 5004 requires percent Radiation latch-up testing Method 1020. Actel will performing radiation testing, this requirement must waived entirety. Wafer acceptance performed Method 5007; however step coverage requirement specified Method 2018 must waived. Method 5004 requires percent, nondestructive bond pull Method 2023. Actel substitutes destructive bond pull Method 2011, condition sample basis only.
Absolute Maximum Ratings
Free temperature range Symbol TSTG Parameter Supply Voltage2, Limits -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +150 Units
Recommended Operating Conditions
Parameter Temperature Range1 Power Supply Tolerance Commercial Military +125 Units %VCC
Input Voltage Output Voltage Source Sink Current5 Storage Temperature
Note:
Ambient temperature (TA) used commercial industrial; case temperature (TC) used military.
Notes:
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Device should operated outside recommended operating conditions. except during device programming. except during device programming. GND, except during device programming. Device inputs normally high impedance draw extremely current. However, when input voltage greater than less than internal protection diode will forward biased draw excessive current.
Package Thermal Characteristics
device junction case thermal characteristic junction ambient characteristic thermal characteristics shown with different flow rates.
Maximum junction temperature 150°C. sample calculation absolute maximum power dissipation allowed CPGA 176-pin package military temperature follows:
Max. junction temp. (°C) Max. military temp. 150°C 125°C (°C/W) 23°C/W
Package Type Ceramic Grid Array
Count
Still
ft/min
Units °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W
Ceramic Quad Flatpack
1-10
Gate Arrays
Electrical Specifications
Commercial Symbol VOH1, VOL1, ICC(S) Parameter HIGH Level Output Test Condition Min. (CMOS) (CMOS) Level Output HIGH Level Input Level Input Input Leakage 3-state Output Leakage Capacitance3, GND, ICC(D) Dynamic Supply Current "Power Dissipation" Section (CMOS) Inputs Inputs -0.3 3.84 0.33 -0.3 Max. Min. Max. Military Units
Standby Supply Current
Notes:
Actel devices drive receive either CMOS signal levels. assignment I/Os CMOS required. Tested output time, min. tested; information only. VOUT
General Power Equation
dissipation achieved. power standby current typically small component overall power. Standby power calculated below commercial, worst-case conditions. Family 5.25 5.25 5.25 Power 15.8 10.5 10.5
[ICCstandby ICCactive] (VCC VOH) Where: ICCstandby current flowing when inputs outputs changing. ICCactive current flowing CMOS switching. IOL, sink/source currents. VOL, level output voltages. equals number outputs driving loads VOL. equals number outputs driving loads VOH. accurate determination problematical because their values depend family type, design details, system I/O. power divided into components-static active.
Static Power Component
static power dissipated loads depends number outputs driving high load current. Again, this value typically small. instance, 32-bit sinking 0.33 will generate with outputs driving low, with outputs driving high.
Active Power Component
Actel FPGAs have small static power components that result power dissipation lower than that PALs PLDs. integrating multiple PALs PLDs into FPGA, even greater reduction board-level power
Power dissipation CMOS devices usually dominated active (dynamic) power dissipation. This component frequency dependent, function logic external I/O. Active power dissipation results from charging internal chip capacitances interconnect, unprogrammed antifuses, module inputs, module outputs, plus external capacitance board traces load device inputs. additional component active power dissipation totem-pole current CMOS transistor pairs. effect associated
1-11
with equivalent capacitance that combined with frequency voltage represent active power dissipation.
Equivalent Capacitance
fq2)routed_Clk2 fq2)routed_Clk2 CEQCD fs1)dedicated_Clk CEQCI fs2)IO_Clk] Where: Number logic modules switching Number input buffers switching Number output buffers switching Number clock loads first routed array clock (all families) Number clock loads second routed array clock (ACT only) Fixed capacitance first routed array clock (all families) Fixed capacitance second routed array clock (ACT only) Fixed number clock loads dedicated array clock (ACT only) Fixed number clock loads dedicated clock (ACT only)
power dissipated CMOS circuit expressed equation Power (uW) VCC2 Where: equivalent capacitance expressed power supply volts. switching frequency MHz. Equivalent capacitance calculated measuring ICCactive specified frequency voltage each circuit component interest. Measurements made over range frequencies fixed value VCC. Equivalent capacitance frequency independent that results used over wide range operating conditions. Equivalent capacitance values shown below.
Values Actel FPGAs
Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR) Dedicated Clock Buffer Loads (CEQCD) Clock Buffer Loads (CEQCI) 22.1 31.2 12.9 23.8 10.4
CEQM Equivalent capacitance logic modules CEQI Equivalent capacitance input buffers CEQO Equivalent capacitance output buffers CEQCR Equivalent capacitance routed array clock CEQCD Equivalent capacitance dedicated array clock CEQCI Equivalent capacitance dedicated clock Output lead capacitance Average logic module switching rate Average input buffer switching rate Average output buffer switching rate Average first routed array clock rate (all families) Average second routed array clock rate (ACT only) Average dedicated array clock rate (ACT only) Average dedicated clock rate (ACT only)
calculate active power dissipated from complete design, switching frequency each part logic must known. Equation shows piecewise linear summation over components, applies devices. Since family only routed array clock, terms labeled routed_Clk2, dedicated_Clk, IO_Clk apply. Similarly, family routed array clocks, dedicated_Clk IO_Clk terms apply. devices, terms will apply. Power VCC2 CEQM* fm)modules CEQI* fn)inputs (CEQO+ fp)outputs CEQCR fq1)routed_Clk1 fq1)routed_Clk1 CEQCR
1-12
Arrays
Fixed Capacitance Values Actel FPGAs (pF)
Fixed Clock Loads -ACT Only)
Device Type A1010B A1020B A1240A A1280A A1425A A1460A A14100A
routed_Clk1
routed_Clk2
Device Type A1425A A1460A A14100A
Clock Loads Dedicated Array Clock
Clock Loads Dedicated Clock
Determining Average Switching Frequency
determine switching frequency design, must have detailed understanding data values input circuit. guidelines table below meant represent worst-case scenarios that they generally used predict upper limits power dissipation.
modules inputs/4 #outputs/4 modules F/10 F/10 modules inputs/4 #outputs/4 sequential modules sequential modules F/10 F/10 modules inputs/4 #outputs/4 sequential modules sequential modules F/10 F/10
Type Logic modules Input switching Outputs switching First routed array clock loads (q1) Second routed array clock loads (q2) Load capacitance (CL) Average logic module switching rate (fm) Average input switching rate (fn) Average output switching rate (fp) Average first routed array clock rate (fq1) Average second routed array clock rate (fq2) Average dedicated array clock rate (fs1) Average dedicated clock rate (fs2)
1-13
Parameter Measurement
Output Buffer Delays
TRIBUFF test loads (shown below)
tDLH tDHL
tENZL tENLZ
tENZH tENHZ
Test Load
Load (Used measure propagation delay)
Load (Used measure rising/falling edges)
output under test
output under test
tPLZ/tPZL tPHZ/tPZH
Input Buffer Delays
Combinatorial Macro Delays
INBUF
tINYH tINYL
tPLH tPHL
tPHL tPLH
1-14
Arrays
Sequential Timing Characteristics
Flip-Flops Latches (ACT
(Positive edge triggered)
tSUD tSUENA tHENA PRE, tWASYN tWCLKA
Note:
represents data functions involving multiplexed flip-flops.
1-15
Sequential ming Characteristics
Flip-Flops Latches (ACT
(Positive edge triggered)
tSUD tSUENA tHENA tCLR tWASYN tWCLKA
Note:
represents data functions involving multiplexed flip-flops.
1-16
Arrays
Sequential Timing Characteristics (continued)
Input Buffer Latches (ACT only)
IBDL
CLKBUF
tINH tINSU tHEXT tSUEXT
Output Buffer Latches (ACT only)
OBDLHS
tOUTSU tOUTH
1-17

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