Delta-sigma Analog-to-digital Converter Linearity Error: 0.0015%F

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Delta-sigma Analog-to-digital Converter Linearity Error: 0.0015%F

Datasheet Thumbnail

Top Searches for this datasheet

CS5529 16-bit, Programmable with 6-bit Latch
Delta-sigma Analog-to-digital Converter
Linearity Error: 0.0015%FS Noise-free Resolution: 16-Bits
General Description
16-bit CS5529 low-power, programmable (Analog-to-Digital Converter), which includes coarse/fine charge buffers, fourth-order modulator, calibration microcontroller, digital filter with programmable decimation rates, 6-bit output latch, threewire serial interface. designed operate from single dual analog supplies single digital supply. digital filter programmable with output update rates between 1.88 Sps. These output rates specified 32.768 kHz. Output word rates increased approximately using kHz. filter designed settle full accuracy selected output word rate conversion. When operated word rates less, filter rejects both simultaneously. power, single conversion settling time, programma-
Bipolar/Unipolar Buffered Input Range 6-bit Output Latch Eight Digital Filters
Selectable Output Word Rates Output Settles Conversion Cycle 50/60 Simultaneous Rejection
Simple Three-wire Serial Interface
SPIand MicrowireCompatible Schmitt Trigger Serial Clock (SCLK)
System/Self-calibration with Registers Power Supply Configurations
output rates, ability handle negative input +2.5 -2.5 signals make this single- dual-supply product ideal solution isolated non-isolated applications. +3.0 -3.0 +3.0
Power Consumption:
ORDERING INFORMATION page
AIN+ AINVREF+ VREF-
DGND
Differential Order Delta-Sigma Modulator
Digital Filter
Calibration Register
SCLK
Control Register Output Register
Latch
Calibration Memory
Calibration
Clock Gen.
XOUT
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved)
DS246F5
CS5529
TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS ANALOG CHARACTERISTICS. ANALOG CHARACTERISTICS. DIGITAL CHARACTERISTICS DIGITAL CHARACTERISTICS DYNAMIC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS SWITCHING CHARACTERISTICS GENERAL DESCRIPTION Analog Input Analog Input Model Voltage Reference Input Model Serial Port Command Register Descriptions Serial Port Interface Serial Port Initialization System Initialization Configuration Register Latch Output Pins Power Consumption Output Word Rate Digital Filter Clock Generator Reset System Port Flag Calibration Calibration Registers Offset Register Gain Register Self Calibration System Calibration Limitations Calibration Range Calibration Tips Configuration Register Descriptions Performing Conversions Performing Conversions with Performing Conversions with Single Conversion Continuous Conversions Output Coding Power Supply Arrangements Getting Started Layout DESCRIPTIONS SPECIFICATION DEFINITIONS ORDERING INFORMATION ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION PACKAGE DIMENSIONS
DS246F5
CS5529
LIST FIGURES
Input models AIN+ AIN- pins. Input model VREF+ VREF- pins. CS5529 Register Diagram. Command Data Word Timing. Filter Response (Normalized Output Word Rate Self Calibration Offset. Self Calibration Gain. System Calibration Offset. System Calibration Gain. CS5529 Configured with +5.0 Analog Supply. CS5529 Configured with ±2.5 Analog Supplies. CS5529 Configured with ±3.0 Supplies.
REVISION HISTORY
Revision Date Changes
Added lead-free device ordering information. Updated legal notice. Added data.
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant infor mation verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, indemnification, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPER ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO BODY, AUTOMOTIVE SAFETY SECURITY DEVICES LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS. INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOM AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners.
DS246F5
CS5529
CHARACTERISTICS SPECIFICATIONS
±2.5 ±5%, ±5%, VREF+ VREF- FCLK 32.768 kHz, (Output Word Rate) Sps, Bipolar Mode, Input Range ±2.5 (See Notes Parameter Accuracy Linearity Error Missing Codes Bipolar Offset Unipolar Offset Offset Drift Bipolar Gain Error Unipolar Gain Error Gain Drift (Note (Note (Note (Notes ±0.0015 ±0.003 Bits LSB16 LSB16 nV/°C ppm/°C Unit
ANALOG CHARACTERISTICS
Noise (Notes Output Word Rate (Hz) 1.88 3.76 7.51 15.0 30.0 61.6 84.5 101.1 Filter Frequency (Hz) 1.64 3.27 6.55 12.7 25.4 50.4 70.7 84.6 Noise (µV) 3000
Notes: Applies after system calibration temperature within Specifications guaranteed design, characterization, and/or test. Specification applies device only does include effects external parasitic thermocouples. Drift over specified temperature range after calibration power-up Wideband noise aliased into baseband. Referred input. Typical values shown peak-to-peak noise multiply ranges output rates. Specifications subject change without notice.
DS246F5
CS5529
ANALOG CHARACTERISTICS (Continued)
Parameter Analog Input Common Mode Signal AIN+ AINSingle Supply Dual Supply Common Mode Rejection Input Capacitance Current AIN+, AIN(Note (Note System Calibration Specifications Full Scale Calibration Range, with VREF Offset Calibration Range Voltage Reference Input Range REF+ REFCommon Mode Rejection Input Capacitance Current Power Supplies Power Supply Currents (Normal Mode) Normal Mode Power Mode Standby Sleep Positive Supplies Negative Supply (Note (Note {(VREF+) (VREF-)} (Note VAVA2.5 ±1.25 (Bipolar/Unipolar Mode) 60Hz (Bipolar/Unipolar Mode) VA120 Unit
Power Consumption
Power Supply Rejection
Notes: section data sheet which discusses Analog Input Models. minimum Full Scale Calibration Range (FSCR) limited maximum allowed gain register value (with margin). maximum FSCR limited modulator's density range. "Analog Input" section details. Also "Limitations Calibration Range". VREF must less than equal supply voltages. outputs unloaded. inputs CMOS levels. Power consumption scales linearly with changes supply voltage.
DS246F5
CS5529
DIGITAL CHARACTERISTICS ±2.5V ±5%, 5%.)(See Notes
11.) Parameter High-level Input Voltage: Pins Except XIN, SCLK SCLK XIN, SCLK SCLK (Note SDO, Iout -5.0mA SDO, Iout 1.6mA SDO, Iout 5.0mA Symbol Cout 0.6VD+ (VD+)-0.9 (VD+)-0.45 (VD+)-1.0 (VD+)-1.0 Unit
Low-level Input Voltage:
Pins Except
High-level Output Voltage: Low-level Output Voltage: Input Leakage Current 3-state Leakage Current
Pins Except Pins Except
Digital Output Capacitance Notes: measurements performed under static conditions.
Iout -100 unless stated otherwise. (VOH Iout µA).
DIGITAL CHARACTERISTICS ±2.5 ±5%, ±5%.)
(See Notes 11.) Parameter High-level Input Voltage: Pins Except XIN, SCLK SCLK XIN, SCLK SCLK SDO, Iout -400 SDO, Iout -5.0 SDO, Iout SDO, Iout Symbol Cout 0.6VD+ (VD+)-0.9 (VD+)-0.45 (VD+)-0.3 (VD+)-1.0 0.16 Unit
Low-level Input Voltage:
Pins Except
High-level Output Voltage: Low-level Output Voltage: Input Leakage Current 3-state Leakage Current
Pins Except Pins Except
Digital Output Capacitance
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Filter Settling Time (Full Scale Step) Symbol Ratio XIN/4 1/fout Units
DS246F5
CS5529
ABSOLUTE MAXIMUM RATINGS (DGND (See Note 13.)
Parameter Power Supplies (Notes Positive Digital Positive Analog Negative Analog (Notes (Note VREF pins Symbol VAIIN IOUT VINA VIND Tstg -0.3 -0.3 -6.0 (VA-) (-0.3) -0.3 +6.0 +6.0 +0.3 (VA+)+0.3 (VD+)+0.3 +150 Unit
Input Current, Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: voltages with respect ground. must satisfy {(VA+) (VA-)} +6.3 |VA-| must VA+. must satisfy {(VD+) (VA-)} +7.75 Applies pins including continuous overvoltage conditions analog input (AIN) pins. Transient current 100mA will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
DS246F5
CS5529
SWITCHING CHARACTERISTICS ±2.5 ±5%, ±5%;
Input Levels: Logic Logic VD+; 50pF) Parameter Master Clock Frequency: Master Clock Duty Cycle Rise Times (Note Digital Input Except SCLK SCLK Digital Output (Note Digital Input Except SCLK SCLK Digital Output XTAL 32.768 (Note trise trise tost tpor 1002 cycles External Clock Internal Oscillator (Note19) Symbol 32.768 Unit
Fall Times
Start-up Oscillator Start-up Time Power-on Reset Period Serial Port Timing Serial Clock Frequency Serial Clock Write Timing Enable Valid Latch Clock Data Set-up Time prior SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior Disable Read Timing Data Valid SCLK Falling Data Rising Hi-Z Pulse Width High Pulse Width SCLK
Notes: Device parameters specified with 32.768 clock, however, clocks used increased throughput. Specified using points waveform interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source.
DS246F5
CS5529
SCLK
Continuous Running SCLK Timing (Not Scale)
Write Timing (Not Scale)
Read Timing (Not Scale)
DS246F5
CS5529
GENERAL DESCRIPTION
CS5529 16-bit Analog-to-Digital Converter (ADC) which includes coarse/fine charge buffers, fourth order modulator, calibration microcontroller, eight digital filters which provide selectable decimation rates, 6-bit output latch, three-wire serial interface. optimized digitize unipolar bipolar signals industrial applications. digital filters provide eight selectable output word rates (OWRs) 1.88 Sps, 3.76 Sps, 7.51 Sps, 15.0 Sps, 30.0 Sps, 61.6 Sps, 84.5 Sps, 101.1 when operated from 32.768 watch crystal equivalent clock (output word rates increased approximately using clock). filters designed settle full accuracy selected output word rate conversion. When operated word rates less (XIN 32.768 kHz), filter rejects both line interference simultaneously. Note that keep from saturating analog front end, input span must stay below times reference voltage. This corresponds gain register 0.666. when reference voltage used.
Note: When smaller reference voltage used, resulting code widths smaller. Since output codes exhibit more changing codes fixed amount noise, converter appears noisier.
Calibration also affect ADC's full scale span because system gain calibration used increase decrease full scale span ADC's transfer functions. limit, input full scale reduced point which gain register reaches upper limit 3.999. (this will occur when gain calibrated with input signal less than equal approximately nominal full scale, does have intrinsic gain error). Calibration effects analog input span detailed later section data sheet.
Analog Input
CS5529 provides nominal input span when gain register decimal differential reference voltage between VREF+ VREF- gain registers content used during calibration gain slope ADC's transfer function. differential reference voltage magnitude gain register factors that used scale nominal input span. After reset, gain register defaults decimal. this case, external voltage between VREF+ VREF- sets ADC's nominal full scale input span user want modify input span, either gain register reference voltage's magnitude needs changed. example, 1.25 reference used place nominal input, fullscale span half. achieve same 1.25V input span, user could simply reference modify gain register decimal.
Analog Input Model
Figure illustrates input models pins. model includes coarse/fine charge buffer which reduces dynamic current demands from signal source. buffer designed accommodate rail rail (common-mode plus signal) input voltages. Typical (sampling) current about 16nA (XIN 32.768 kHz, Figure Application Note "Switched-Capacitor Input Structures", details various input architectures.
Voltage Reference Input Model
Figure illustrates input models VREF pins. includes coarse/fine charge buffer which reduces dynamic current demand external reference. Typical (sampling) current about (XIN 32.768 kHz, Figure reference's buffer designed accommodate rail-to-rail (common-mode plus signal) input voltDS246F5
CS5529
1Fine 1Coarse 20pF 1Fine 2Coarse 10pF 32.768
Figure Input model VREF+ VREF- pins.
25mV fVos
VREF 25mV fVos
32.768
Figure Input models AIN+ AIN- pins.
ages. differential voltage between VREF+ VREF- sets nominal full scale input span converter. single-ended reference voltage, such LT1019-2.5, reference output connected VREF+ CS5529 ground reference LT1019-2.5 connected VREF- pin.
illustrates block diagram internal register. After system initialization reset, serial port command mode. converter stays this mode until valid 8-bit command received (the first 8-bits into serial port). Once valid 8bit command received interpreted ADC's command register, serial port enters data mode. data mode next serial clock pulses shift data either into serial port serial clock pulses needed setup register command issued). Command Register Descriptions section illustrates valid commands.
Serial Port
CS5529 includes microcontroller with command register, configuration register, conversion data register (read only), gain offset register calibration. registers, except 8-bit command register, 24-bits length. Fig-
Offset Register
Gain Register
Read Only
Conversion Data Register (1x24)
Serial Interface Write Only
SCLK
Configuration Register
Latch Outputs Power Mode Output Word Rates Unipolar/Bipolar Reset System etc.
Command Register
Figure CS5529 Register Diagram.
DS246F5
CS5529
Command Register Descriptions
D7(MSB) NAME Command Bit, RSB2 VALUE D3-D1 Single Conversion, Continuous Conversions, Read/Write, Register Select Bit, RSB2RSB0 RSB1 RSB0 PS/R FUNCTION Null command operation). command bits, including must Logic executable commands. Single Conversion active. Perform conversion. Continuous Conversions active. Perform conversions continuously. Write selected register. Read from selected register. Offset Register Gain Register Configuration Register Conversion Data Register (read only) Set-up Registers (Offset, Gain, Configuration) Reserved Reserved Reserved Power Save
Power Save/Run, PS/R
Table Command Perform Single Conversion
This command instructs perform single conversion. Perform Continuous Conversions
This command instructs perform continuous conversions. Power Save/Run
PS/R
PS/R normal mode entered. PS/R power save mode entered. Null
This command used clear port flag continuous conversion mode when port flag configuration register logic
DS246F5
CS5529
SYNC1
Part serial port re-initialization sequence (see text command). SYNC0
serial port re-initialization sequence. Read/Write Registers
RSB2 RSB1 RSB0
These commands used perform write read from specific register. register accessed selected with RSB2-RSB0 bits command word. RSB[4:0] Write Register Read Register
Register address binary encoded follows. registers bits long. Address Description Read Write Offset Register Read Write Gain Register Read Write Configuration Register Read Conversion Data Register Read Write Offset Gain Configuration Registers this sequence (i.e. 8-bit command followed 72-bits data access Offset, then Gain, then Configuration register)
Serial Port Interface
CS5529's serial interface consists four control lines: SDI, SDO, SCLK. Chip Select, control line which enables access serial port. tied logic port function three wire interface. SDI, Serial Data data signal used transfer data converters. SDO, Serial Data Out, data signal used transfer output data from converters. output will held high impedance time logic SCLK, Serial Clock, serial bit-clock which controls shifting data from ADC's serial port. must held logic before SCLK transitions recognized
port logic. accommodate opto-isolators SCLK designed with Schmitt-trigger input allow opto-isolator with slower rise fall times directly drive pin. Additionally, capable sinking sourcing directly drive opto-isolator LED. will have less than loss drive voltage when sinking sourcing Figure illustrates serial sequence necessary write read from serial port's registers. transfer data always initiated sending appropriate 8-bit command (MSB first) serial port (SDI pin). important note that some commands information from configuration registers perform function. those commands important that correct information written configuration register first.
DS246F5
CS5529
SCLK
giste rite ycle
SCLK
et-u giste
Read ycle
SCLK
SCLKs clock cycle rsio exce first rsio take clock cycle ontinuous onvers
Figure Command Data Word Timing.
DS246F5
CS5529
Serial Port Initialization
serial port initialized command mode whenever power-on reset performed when port initialization sequence completed. port initialization sequence involves clocking fifteen more) SYNC1 command bytes (0xFF) followed SYNC0 command byte (0xFE). This sequence places chip command mode where waits until valid command received. This function does reset internal registers their default settings. only resets serial port command mode.
Latch Output Pins
D3-D0 pins converter mimic D21D18 bits configuration register. D3-D0 used control multiplexers other digital logic functions outside converter. D0-D3 outputs powered from DGND. Their output voltage will logic DGND logic A1-A0 pins converter mimic D23-D22 bits configuration register used control analog switches. These outputs powered from VA-, hence, their output voltage will either logic logic outputs sink source least recommended limit drive currents less than reduce self-heating chip.
System Initialization
When power CS5529 applied, chip held reset condition until 32.768 oscillator started counter-timer elapses. high 32.768 crystal, oscillator takes 400-600 start. counter-timer counts 1002 oscillator clock cycles make sure oscillator fully stable. During this time-out period serial port logic reset (Reset Valid) configuration register indicate that valid reset occurred. After reset, on-chip registers initialized following states converter placed command mode where waits valid command.
Configuration Register: Offset Register: Gain Register: Note: 000040(H) 000000(H) 400000(H)
Power Consumption
CS5529 accommodates four power consumption modes: normal, power, standby, sleep. normal mode, default mode, entered after power-on-reset typically consumes power mode alternate mode that reduces consumed power entered setting (the power mode bit) configuration register logic Since converter's noise linearity performance improves with increased power consumption, slightly degraded noise linearity performance should expected power mode. final modes power save modes. These modes power down most analog portion chip stop filter convolutions. power save modes entered whenever Power Save (0x81 hexadecimal) command issued serial port. particular power save mode entered depends state (the power save select bit) configuration register. logic converter enters standby mode reducing power consumption standby mode leaves oscillator on-chip bias generator
system reset initiated time writing logic (Reset System) configuration register. After reset, (Reset Valid) until configuration register read. user must then write logic take part reset mode.
Configuration Register
configuration register register used modify functions ADC. following sections detail functions bits configuration register.
DS246F5
CS5529
running. This allows converter quickly return normal power mode once PS/R back logic configuration register logic Power Save command issued, sleep mode entered reducing consumed power less than Since sleep mode disables oscillator, approximately crystal oscillator start-up delay period required before returning normal power mode. external clock used, chip should start within microseconds. better than rejection both with output word rates below 15.0 (XIN 32.768 kHz). converter's digital filters scale with XIN. example with output word rate Sps, filter's corner frequency typically 12.7 increased 64.536 doubles filter's corner frequency moves 25.4
Clock Generator
CS5529 includes gate which connected with external crystal provide master clock chip. chip designed operate using low-cost 32.768 "tuning fork" type crystal. lead crystal should connected other XOUT. Lead lengths should minimized reduce stray capacitance. Note that converter will operate with external (CMOS compatible) clock with frequencies kHz.
Output Word Rate
WR2-WR0 bits configuration register output conversion word rate converter shown Configuration Register Descriptions table. word rates indicated table assume master clock 32.768 kHz. Upon reset converter operate with output word rate 15.0 Sps.
Digital Filter
CS5529 eight different linear phase digital filters which output word rates (OWRs) stated Configuration Register Descriptions. These rates assume that 32.768 kHz. Each filters magnitude response similar that shown Figure filters optimized settle full accuracy every conversion yield
Reset System
reset system permits user perform hardware reset. hardware reset initiated time writing logic (Reset System) configuration register. After hardware reset cycle complete, serial port logic reset (Reset Valid) configuration register indicate that valid reset occurred. After reset, on-chip registers initialized following states converter placed command mode where waits valid command.
Configuration Register: Offset Register: Gain Register: Note: 000040(H) 000000(H) 400000(H)
Figure Filter Response (Normalized Output Word Rate
system reset initiated time writing logic (Reset System) configuration register. After reset, (Reset Valid) until configuration register read. user must then write logic take part reset mode.
DS246F5
CS5529
Port Flag
port flag configuration register allows user select mode which conversions will presented serial port. With port flag cleared, user must read conversion data register. With port flag logic user read conversion data from serial port first issuing NULL command clear flag then issuing SCLKs read conversion word. version cycles complete will after gain calibration completed.
Note: will cleared time data register, offset register, gain register, setup register read. Reading configuration register alone will clear bit. After CS5529 reset, converter functional perform measurements without being calibrated. this case, converter will utilize initialized values on-chip registers (Gain 1.0, Offset 0.0) calculate output words. initial offset gain errors internal circuitry chip will remain.
Calibration
Calibration used zero gain slope ADC's transfer function. calibration control bits configuration register allow user perform either self calibration system calibration. offset gain calibration steps each take conversion cycle complete. calibration step, calibration control bits will back logic (Done Flag) will logic combination self-calibration (CC2-CC0= 011; offset calibration followed gain calibration), calibration will take conOffset Register
23(MSB) Sign 2-13 2-14 2-15 2-16 2-17 2-18 2-19
Calibration Registers
offset calibration result stored offset register. result used during conversion process nullify offset errors. offset register 2-24 proportion input span (bipolar span times unipolar span). offset register determines offset trimmed positive negative positive, negative). converter typically trim percent input span. Refer following Offset Register Gain Register descriptions details.
2-20
2-21
2-10 2-22
2-11 2-23
2-12 2-24
represents 2-24 proportion input span (bipolar span times unipolar span). Offset data word bits align (bit MSB-4 offset register changes MSB-4 data). After reset, bits `0'.
DS246F5
CS5529
Gain Register
23(MSB) 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-10 2-22
gain register span from (4-2-22). After Reset (MSB-1) `1', other bits `0'.
gain calibration results stored gain register. result sets slope ADC's transfer function. gain register spans from 2-22). decimal equivalent meaning gain register
OPEN AIN+
AINVREF+ Reference VREF-
OPEN
CLOSED CLOSED
where binary numbers have value either zero corresponds MSB-1, 22).
Figure Self Calibration Gain.
Self Calibration
CS5529 offers both self offset self gain calibrations. self-calibration offset, converter internally ties inputs modulator together routes them VREF- shown Figure Also self offset calibration requires that VREF- tied fixed voltage between VA-. self-calibration gain, differential inputs modulator connected VREF+ VREF- shown Figure7.
System Calibration
system calibration functions, user must input signals which represent system ground system full scale converter. When system offset calibration performed ground reference signal must applied converter (see Figure When system gain calibration performed, user must input signal representing positive full scale point shown Figure either case, calibration signals must within specified calibration limits each specific calibration step (refer System Calibration Specifica-
OPEN CLOSED AIN+
External Connections AIN+
AINVREF-
OPEN CLOSED
AIN-
Figure Self Calibration Offset.
Figure System Calibration Offset.
DS246F5
CS5529
Calibration Tips
External Connections AIN+ Full Scale AIN-
Figure System Calibration Gain.
Calibration steps performed output word rate selected WR2-WR0 bits configuration register. Since higher word rates result conversion words with more peak-to-peak noise, calibration should performed lower output word rates. Also, minimize digital noise near device, user should wait each calibration step completed before reading writing serial port. Factory calibration performed user's system using system calibration capabilities CS5529. After calibrated user's system, offset gain register contents read system microcontroller recorded EEPROM. These same calibration words then uploaded into offset gain registers converter when power first applied system. user scale input range modifying gain register. example, self system calibration performed with full scale full scale 1.25 desired, user modify gain register double slope. This done reading gain register, shifting binary word position left (this multiplies gain word writing this word back into gain register. gain register scaled amount long does exceed decimal range 0.25 4.0. methods used determine when calibration complete: (Port Flag) configuration register logic falls logic completion calibration; regardless bit, (Done Flag) configuration register completion calibration. user either monitor determine when calibration complete. Whichever method used, calibration control bits (CC2-CC0) automatically return logic upon completion calibration.
tions). system gain calibration performed, calibrated input must cause resulting gain register's content, decoded decimal, exceed 3.9999998. above condition requires that full scale input voltage greater than percent differential reference voltage (i.e. 625mV input signal must applied differential reference voltage 2.5V).
Limitations Calibration Range
System calibration limited signal headroom analog signal path inside chip discussed under Analog Input section this data sheet. gain calibration full scale input signal reduced point which gain register reaches upper limit (4-2-22 decimal) FFFFFF (hexadecimal). Under nominal conditions, this occurs with full scale input signal equal about reference voltage. With converter's intrinsic gain error, this full scale input signal higher lower. defining minimum Full Scale Calibration Range (FSCR) under "Analog Characteristics", margin retained accommodate intrinsic gain error. Alternatively input full scale signal increased point which exceeds operating range analog circuitry. This occurs when input voltage approximately 1.5X differential reference voltage (Gain Register 1.0).
DS246F5
CS5529
Configuration Register Descriptions
D23(MSB)
NAME
VALUE 0000
FUNCTION Latch Output Pins A1-A0 mimic D23-D22 Register bits. Latch Output Pins D3-D0 mimic D21-D18 Register bits. Must always logic zero. Normal Mode Reduced Power Mode 15.0 (2180 cycles) 30.0 (1092 cycles) 61.6 (532 cycles) 84.5 (388 cycles) 101.1 (324 cycles) 1.88 (17444 cycles) 3.76 (8724 cycles) 7.51 (4364 cycles) Bipolar Measurement mode Unipolar Measurement mode Must always logic Normal Operation Activate Reset cycle. return normal operation this must written back logic zero. reset occurred been cleared (read only). Valid Reset occurred. (Cleared when read.) Port Flag mode inactive Port Flag mode active Standby Mode (Oscillator active, allows quick power-up) Sleep Mode (Oscillator inactive) Done Flag cleared (read only). Calibration Conversion cycle completed (read only). Normal operation calibration) Offset Self-Calibration Gain Self-Calibration Offset self-cal followed Gain self-calibration Used. Offset System Calibration Gain System Calibration Used.
D23-D22 Latch Outputs, A1-A0 D21-D18 Latch Outputs, D3-D0 Used, Power Mode,
D15-D13 Word Rate, WR2-0 (Note: Rates valid 32.768 kHz)
D11-D8
Unipolar/Bipolar, Used, Reset System,
D2-D0
Reset Valid Port Flag, Power Save Select, Done Flag, Calibration Control Bits, CC2-CC0
indicates value after part reset
DS246F5
CS5529
Performing Conversions
CS5529 offers modes performing conversions: single conversion continuous conversions. sections that follow detail differences provides examples illustrating modes. Note that assumed that configuration register been initialized before conversions performed.
Single Conversion
single conversion performed after user transmits single conversion command (0xC0 Hexadecimal). completion conversion, will fall logic indicate that conversion complete. acquire conversion, user must issue SCLKs with logic (i.e. NULL command) clear flag. Upon falling edge SCLK, will present first (MSB) conversion word. SCLKs (high, then low) then required read conversion word from port.
Note: user must give explicit command (other than NULL command) read conversion data register when logic data conversion word must read before command entered converter will remain data mode until conversion word read. Once conversion read converter returns command mode.
Performing Conversions with
single conversion performed after user transmits single conversion command (0xC0 Hexadecimal). completion conversion, (Done Flag) configuration register will logic While conversion being performed, user read configuration register determine set. Once been set, read conversion data register command (0x96 Hexadecimal) issued read conversion data register obtain conversion data word.
Note: 1)The configuration register will cleared logic when conversion data register, gain register, offset register read. Reading only configuration register will clear flag bit. another single conversion command issued converter while performing conversion, filter will abandon current conversion restart convolution cycle.
Continuous Conversions
Continuous conversions performed after user transmits continuous conversions command (0xA0 Hexadecimal). completion conversion, will fall logic indicate that conversion complete. read conversion word, user must issue SCLKs with logic (i.e. NULL command) clear flag. Upon falling edge SCLK, will present first (MSB) conversion word. SCLKs (high, then low) then required read conversion word from port. When operating continuous conversion mode, user need read every conversion. user chooses read conversion after falls, will rise clock cycle before next conversion word available then fall again signal that another conversion word available. exit continuous conversion mode, user must issue valid command, other than NULL command, input when
Performing Conversions with
(Port Flag) configuration register eliminates need user monitor (Done Flag) configuration register determine conversion available. When logic SDO's output behaves flag signal indicating when conversions completed. will fall logic once conversion complete.
DS246F5
CS5529
flag falls. instance, user just read conversion data register again exit continuous conversion mode.
Note: user begins clear flag read conversion data, this action must finished before conversion cycle which occurring background complete user wants able read conversion data. command issued converter while performing conversion, filter will stop current conversion start convolution cycle perform conversion. Continuous conversions aren't allowed unless port flag configuration register. converter will remain data mode continually perform conversions until exit command issued (i.e. exit user must read register).
conversion word represent conversion data. third byte contains error flag bits. third byte, D7-D4 always logic D3-D2 always logic bits D1-D0 flag bits. (Overrange Flag) logic time input signal more positive than positive full scale, more negative than zero (unipolar mode), more negative than negative full scale (bipolar mode). cleared back logic whenever conversion word occurs which overranged.The (Oscillation Detect) logic time that oscillatory condition detected modulator. This does occur under normal operating conditions, occur whenever input converter extremely overranged. set, conversion data bits completely erroneous. flag will cleared logic when modulator becomes stable. Table Table illustrate output coding CS5529. Unipolar conversions output binary format bipolar conversions output two's complement.
Output Coding
shown Output Conversion Data Register Descriptions, CS5529 presents output conversions 24-bit conversion word. first bits
Table Output Conversion Data Register Description bits flags).
Unipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Offset Binary FFFF FFFF -FFFE 8000 -7FFF 0001 -0000 0000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Two's Complement 7FFF 7FFF -7FFE 0000 -FFFF 8001 -8000 8000
VFS/2-0.5
-0.5
+0.5 <(+0.5 LSB)
-VFS+0.5 <(-VFS+0.5 LSB)
Note: table equals voltage between ground full scale unipolar gain ranges, voltage between full scale bipolar gain ranges. text about error flags under overrange conditions. Table CS5529 16-bit Output Coding. DS246F5
CS5529
Power Supply Arrangements
CS5529 designed operate from single dual analog supplies single digital supply. following power supply connections possible:
+5.0 Analog Supply
+2.5 -2.5 +3.0 -3.0 Figure illustrates CS5529 connected with single supply measure differential inputs relative common mode Figure illustrates CS5529 connected with ±2.5 bipolar
XOUT
VREF+
VREF-
32.768 Optional Clock Source
Differential Inputs (Gain Register 1.0) ±2.5 Differential Inputs (Gain Register 2.0) ±1.25 Differential Inputs (Gain Register 4.0)
AIN+
CS5529
AIND3
Common Mode
SCLK
Serial Data Interface
DGND
Logic Outputs: Switch from VAD0-D3 Switch from DGND
Figure CS5529 Configured with +5.0 Analog Supply.
+2.5 Analog Supply Digital Supply
XOUT
VREF+ VREFAIN+ CS5529
32.768 Optional Clock Source
±2.5 Differential Inputs (Gain Register 1.0) ±1.25 Differential Inputs (Gain Register 2.0) ±625 Differential Inputs (Gain Register 4.0) -2.5 Analog Supply Logic Outputs: Switch from VAD0-D3 Switch from DGND
SCLK AIND3
Serial Data Interface
DGND
Figure CS5529 Configured with ±2.5 Analog Supplies.
DS246F5
CS5529
analog supplies digital supply measure ground referenced bipolar signals. Figure illustrates CS5529 connected with ±3.0 bipolar analog supplies digital supply measure ground referenced bipolar signals.
+3.0 Analog Supply
XOUT
Digital Supply
VREF+ VREFCS5529 AIN+
32.768 Optional Clock Source
±3.0 Differential Inputs (Gain Register 1.0) ±1.50 Differential Inputs (Gain Register 2.0) ±750 Differential Inputs (Gain Register 4.0) -3.0 Analog Supply Logic Outputs: Switch from VAD0-D3 Switch from DGND
AIND3
SCLK
Serial Data Interface
DGND
Figure CS5529 Configured with ±3.0 Supplies.
DS246F5
CS5529
Getting Started
CS5529 many features. From software programmer's perspective, what should done first? begin, 32.768 crystal takes approximately start-up. accommodate this, recommended that software delay approximately second precede processor's initialization code before registers accessed ADC. This delay time dependent start-up delay clock source. CMOS clock source with start-up delay being used drive ADC, then this delay necessary. converters include on-chip power reset circuit automatically reset ADCs shortly after power When power CS5529 applied, chip held reset condition until 32.768 oscillator started countertimer elapses. counter-timer counts 1002 oscillator clock cycles make sure oscillator fully stable. During this time-out period serial port logic reset (Reset Valid) configuration register indicate that valid reset occurred. normal start-up conditions, this power-on-reset circuit should reset chip when power applied. your application experience abnormal power start-up conditions, following sequence instructions should performed guarantee converter begins proper operation: After power applied, initialize serial port using serial port synchronization sequence. Write reset (RS) configuration register reset converter. Read configuration register determine reset valid (RV) `1'. set, configuration register should read again. When been `1', reset back writing 0x000000 configuration register. Note that while other register bits will reset their default state, must normal operation converters. Once been `0', placed command state were waits valid command execute. next step load configuration register. need factory calibration, perform offset gain calibration steps. Then off-load offset gain register contents into EEPROM. These registers then initialized these conditions when instrument used normal operation. Once calibration ready, input command start conversions either single continuous conversion mode. Monitor flag that data ready read conversion data.
Layout
CS5529 should placed entirely over analog ground plane with DGND device connected analog ground plane. design splits ground plane, place analog-digital plane split immediately adjacent digital portion chip.
DS246F5
CS5529
DESCRIPTIONS
NEGATIVE ANALOG POWER POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT LOGIC OUTPUT (ANALOG) LOGIC OUTPUT (ANALOG)
LOGIC OUTPUT (DIGITAL)
VAVA+ AIN+
VREF+ VOLTAGE REFERENCE INPUT
VREFD3
VOLTAGE REFERENCE INPUT LOGIC OUTPUT (DIGITAL) LOGIC OUTPUT (DIGITAL) LOGIC OUTPUT (DIGITAL) SERIAL DATA INPUT
SERIAL DATA OUTPUT
AINA0 SCLK XOUT
DGND
CHIP SELECT SERIAL CLOCK INPUT CRYSTAL
POSITIVE DIGITAL POWER DIGITAL GROUND CRYSTAL
Clock Generator XIN; XOUT Crystal Crystal Out, Pins gate inside chip connected these pins used with crystal provide master clock device. Alternatively, external (CMOS compatible) clock (powered relative VD+) supplied into provide master clock device. Control Pins Serial Data Chip Select, When active low, port will recognize SCLK. When high will output high impedance state. should changed when SCLK Serial Data Input, input serial input port. Data will input rate determined SCLK. Serial Data Output, serial data output. will output high impedance state SCLK Serial Clock Input, clock signal this determines input/output rate data SDI/SDO pins respectively. This input Schmitt trigger allow slow rise time signals. SCLK will recognize clocks only when low.
DS246F5
CS5529
Logic Outputs (Analog), logic states A0-A1 mimic states D22-D23 bits configuration register. Logic Output VA-, Logic Output VA+. Logic Outputs (Digital), logic states D0-D3 mimic states D18-D21 bits configuration register. Logic Output DGND, Logic Output VD+. Measurement Reference Inputs AIN+, AIN- Differential Analog Input, Pins Differential input pins into device. VREF+, VREF- Voltage Reference Input, Pins Fully differential inputs which establish voltage reference on-chip modulator. Power Supply Connections Positive Analog Power, Positive analog supply voltage. Negative Analog Power, Negative analog supply voltage. Positive Digital Power, Positive digital supply voltage (+3.0 DGND Digital Ground, Digital Ground.
DS246F5
CS5529
SPECIFICATION DEFINITIONS
Linearity Error deviation code from straight line which connects points Converter transfer function. point located below first code transition other point located beyond code transition ones. Units percent full-scale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs. Unipolar Offset deviation first code transition from ideal (1/2 above voltage AIN- pin). When unipolar mode (U/B Units LSBs. Bipolar Offset deviation mid-scale transition (111.111 000.000) from ideal (1/2 below voltage AIN- pin). When bipolar mode (U/B Units LSBs.
DS246F5
CS5529
ORDERING INFORMATION
Model Number CS5529-AP CS5529-AS CS5529-ASZ Linearity Error (Max) ±0.003% ±0.003% ±0.003% Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C Package 20-pin 0.3" Plastic 20-pin 0.2" Plastic SSOP 20-pin 0.2" Plastic SSOP Lead Free
ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Peak Relfow Temp Rating* Maximum Floor Life
CS5529-AP CS5529-AS CS5529-ASZ (Lead Free)
Limit Days Days
(Moisture Sensitivity Level) specified IPC/JEDEC J-STD-020.
DS246F5
CS5529
PACKAGE DIMENSIONS
PLASTIC (PDIP) PACKAGE DRAWING
SEATING PLANE
VIEW
BOTTOM VIEW
SIDE VIEW
INCHES 0.000 0.015 0.115 0.014 0.045 0.008 0.980 0.300 0.240 0.090 0.280 0.300 0.000 0.115 0.210 0.025 0.195 0.022 0.070 0.014 1.060 0.325 0.280 0.110 0.320 0.430 0.060 0.150
MILLIMETERS 0.00 5.33 0.38 0.64 2.92 4.95 0.36 0.56 1.14 1.78 0.20 0.36 24.89 26.92 7.62 8.26 6.10 7.11 2.29 2.79 7.11 8.13 7.62 10.92 0.00 1.52 2.92 3.81
DS246F5
CS5529
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
INCHES
MILLIMETERS
NOTE
-0.084 -2.13 0.002 0.010 0.05 0.25 0.064 0.074 1.62 1.88 0.009 0.015 0.22 0.38 0.272 0.295 6.90 7.50 0.291 0.323 7.40 8.20 0.197 0.220 5.00 5.60 0.022 0.030 0.55 0.75 0.025 0.041 0.63 1.03 Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
DS246F5

Delta-sigma Analog-to-digital Converter Linearity Error: 0.0015%F

Top Searches for this datasheet

Other recent searches