High Capacity 2,000 52,000 available logic gates Kbits configurab
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Integrator Series FPGAs 40MX 42MX Families
High Capacity
2,000 52,000 available logic gates Kbits configurable dual-port SRAM Fast wide-decode circuitry user-programmable Pins performance Dual-Port SRAM Access FIFOs 35-bit Address Decode
Supported Actel Designer Series development system with interfaces popular design environments such Cadence, Exemplar, IST, Mentor Graphics, Synopsys, Synplicity, Viewlogic power consumption (less than 100µA stand-by mode) JTAG 1149.1 boundary scan testing 5.0V 3.3V Programmable PCI-compliant
General Description
High Performance
Actel's family programmable logic devices provides system logic designers with high-performance, cost-effective ASIC alternative single Actel FPGA. family architecture based Actel's patented antifuse technology, implemented 0.45µ triple-metal CMOS process. With capacities ranging from 2,000 52,000 gates, synthesis-friendly family devices provides data paths MHz, live power-up, deliver five times lower stand-by power consumption than other FPGA device. With FPGAs available wide variety packages.
Ease Integration
Mixed voltage operation (3.3 I/O) Synthesis-friendly architecture support ASIC design methodologies 95-100% resource utilization, using automatic place-and-route tools with 100% fixing Deterministic, user-controllable timing DirectTime software tools
Integrator Series Product Profile
Device Capacity A40MX02 A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
A42MX52
Gates ASIC Equivalent Gates SRAM Bits
Logic Modules
2,000 1,200 PL44 PL68 PQ100 VQ80
4,000 2,000 PL44 PL68 PL68 PQ100 VQ80
9,000 4,000 PL84 PQ100 PQ160 TQ176
16,000 8,000 PL84 PQ160 PQ208 TQ176
24,000 14,000 PL84 PQ160 PQ208 TQ176
36,000 20,000 2,560 1230 1184 1,276 PQ208 RQ208 RQ240
52,000 30,000 3,072 1888 1833 1,944 RQ208 RQ240
Sequential Combinatorial Decode
SRAM Modules (64x4 32x8) Dedicated Flip-Flops Clocks User (maximum) JTAG Packages
1997
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1997 Actel Corporation
Integrator family comprised 40MX 42MX FPGAs. 42MX devices also feature Actel's which supports mixed voltage systems. I/Os operate with either 5.0V swing, 5.0V input tolerance, 3.3V mixed 5.0V/3.3V system operation. logic core operated 5.0V maximum performance; 3.3V minimum power consumption. 42MX FPGA devices include system-level features such JTAG, dual-port SRAM, fast wide-decode modules, programmable interface. 42MX FPGAs were designed integrate system logic that typically implemented multiple CPLDs, PALs FPGAs.
Ordering Information
A42MX16
42MX family offers industry's fastest dual-port SRAM implementing fast FIFOs, LIFOs, temporary data storage. large number storage elements efficiently address applications requiring wide data-path manipulation transformation functions such telecommunications, networking, DSP. Power consumption reduced 100µA, providing excellent solution low-power systems. MultiPlex includes selectable output drives certain 42MX devices, enabling 100% compliance both 5.0V 3.3V systems.
Application (Temperature Range) Blank Commercial +70°C) Industrial (-40 +85°C) Package Lead Count Package Type Plastic Leaded Chip Carrier Plastic Quad Flatpack Plastic Power Quad Flatpack Thin (1.4 Quad Flatpack Very Thin (1.0 Quad Flatpack Speed Grade Blank Standard Speed Approximately faster than Standard Approximately faster than Standard Approximately faster than Standard Approximately slower than Standard Part Number A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 A42MX52 2,000 Gates 4,000 Gates 9,000 Gates 16,000 Gates 24,000 Gates 36,000 Gates 52,000 Gates
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Product Plan
Speed Grade A40MX02 Device 44-pin Plastic Leaded Chip Carrier (PLCC) 68-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Plastic Quad Flatpack (PQFP) 80-pin Very Thin Plastic Quad Flatpack (VQFP) A40MX04 Device 44-pin Plastic Leaded Chip Carrier (PLCC) 68-pin Plastic Leaded Chip Carrier (PLCC) 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Plastic Quad Flatpack (PQFP) 80-pin Very Thin Plastic Quad Flatpack (VQFP) A42MX09 Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Plastic Quad Flatpack (PQFP) 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Plastic Quad Flatpack (TQFP) A42MX16 Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Plastic Quad Flatpack (PQFP) 160-pin Plastic Quad Flatpack (PQFP) 208-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Plastic Quad Flatpack (TQFP) A42MX24 Device 84-pin Plastic Leaded Chip Carrier (PLCC) 160-pin Plastic Quad Flatpack (PQFP) 208-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Plastic Quad Flatpack (TQFP) A42MX36 Device 208-pin Plastic Quad Flatpack (PQFP) 208-pin Plastic Power Quad Flatpack (RQFP) 240-pin Plastic Power Quad Flatpack (RQFP) A42MX52 Device 208-pin Plastic Power Quad Flatpack (RQFP) 240-pin Plastic Power Quad Flatpack (RQFP) Applications: Commercial Industrial Military MIL-STD-883 Availability: Application
Available Planned Planned
Speed Grade:
Approx. faster than Standard Approx. faster than Standard Approx. faster than Standard Approx. slower than Standard
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Integrator Series devices supported Actel's Designer Series development software, which provides seamless integration into ASIC design flow. Designer Series development tools offer automatic placement routing (even with preassigned pins), static timing analysis, user programming, debug diagnostic probe capabilities. addition, DirectTime tool provides deterministic well controllable timing. DirectTime allows designer specify performance requirements individual paths system clocks. Using these specifications, software will automatically optimize placement routing logic meet constraints. Included with Designer Series tools Actel's ACTgenMacro Builder. ACTgen allows designer quickly build fast, efficient logic functions such counters, adders, FIFOs, RAM. Designer Series tools provide designers with capability move high-level description languages,
Plastic Device Resources
such VHDL Verilog, schematic design entry with interfaces most tools. Designer Series supported Pentium Sun® workstations. software provides interfaces Cadence, Mentor Graphics®, Escalade, OrCADand Viewlogic® design environments. Additional development tools supported through Actel's Industry Alliance Program, including DATA (ABEL FPGA) MINC. Actel's FPGAs ideal solution shortening system design development cycle, they offer cost-effective alternative low-volume production runs. 40MX 42MX devices excellent choices integrating logic that currently implemented multiple PALs, CPLDs, FPGAs. Some example applications include high-speed controllers address decoding, peripheral interfaces, DSP, coprocessor functions.
User I/Os Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 A42MX52 PLCC 44-pin PLCC 68-pin PLCC 84-pin VQFP 80-pin PQFP 100-pin PQFP 160-pin PQFP 208-pin RQFP 208-pin RQFP 240-pin TQFP 176-pin
Package Definitions (Consult your local Actel sales representative product availability.) PLCC Plastic Leaded Chip Carrier, PQFP Plastic Quad Flat Pack, TQFP Thin Quad Flat Pack, VQFP Very Thin Quad Flat Pack, RQFP Plastic Power Quad Flat Pack
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Description
CLK, CLKA, CLKB Clock Clock Clock (input)
QCLKA/B,C,D Quadrant Clock (Input/Output)
Quadrant clock inputs. When used register control signal, these pins function general-purpose I/O.
Serial Data Input (Input)
clock inputs clock distribution networks. clock input buffered prior clocking logic modules. This also used I/O.
DCLK Diagnostic Clock (Input)
Serial data input diagnostic probe device programming. active when MODE HIGH. This functions when MODE LOW.
Test Clock
clock input diagnostic probe device programming. DCLK active when MODE HIGH. This functions when MODE LOW.
Ground (Input)
Clock signal shift JTAG data into device. This functions when JTAG fuse programmed.
Test Data
Input supply voltage.
Input/Output (Input, Output)
Input, output, three-state, bidirectional buffer. Input output levels compatible with standard CMOS specifications. Unused pins automatically driven Designer Series software.
MODE Mode (Input)
Serial data input JTAG instructions data. Data shifted rising edge TCLK. This functions when JTAG fuse programmed.
Test Data
Serial data output JTAG instructions test data. This functions when JTAG fuse programmed.
Test Mode Select
Controls multifunction pins (DCLK, PRA, PRB, SDI, TDO). When MODE HIGH, special functions active. provide Actionprobe capability, MODE should terminated through resistor that MODE pulled high when required. turn input/output devices low-power mode, MODE must HIGH.
Connection
Serial data input JTAG test mode. Data shifted rising edge TCLK. This functions when JTAG fuse programmed.
Supply Voltage (Input)
Input HIGH supply voltage.
Supply Voltage (Input)
connected circuitry within device.
PRA/I/O Probe (Output)
Input HIGH supply voltage, supplies array core only.
Supply Voltage (Input)
Used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when debugging been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. active when MODE HIGH. This functions when MODE LOW.
PRB/I/O Probe (Output)
Input HIGH supply voltage, supplies cells only. Note: TCK, TDI, TDO, available only devices containing JTAG circuitry.
Used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when debugging been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. active when MODE HIGH. This functions when MODE LOW.
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Connecting Devices
40MX
40MX FPGAs will operate 5.0V only systems, 3.3V only systems. 3.3V 5.0V
42MX
Input 3.3V 5.0V
Output 3.3V 5.0V
42MX FPGAs will operate 5.0V only systems, 3.3V only systems, mixed 5.0V/3.3V systems. VCCA 3.3V 5.0V 5.0V VCCI 3.3V 3.3V 5.0V Input 3.3V 3.3V, 5.0V 5.0V Output 3.3V 3.3V 5.0V
Integrator Series Architectural Overview
Figure 40MX Logic Module
40MX 42MX devices composed fine-grained building blocks that produce fast, efficient logic designs. devices within Integrator Series composed logic modules, routing resources, clock networks, modules, which building blocks designing fast logic designs. addition, subset devices contain embedded dual-port SRAM wide decode modules. dual-port SRAM modules optimized high-speed data-path functions such FIFOs, LIFOs, scratchpad memory. "Integrator Series Product Profile" page 1-91, lists specific logic resources contained within each device.
Logic Modules
40MX logic module eight-input, one-output logic circuit chosen wide range functions implements efficient interconnect routing resources (Figure logic module implement four basic logic functions (NAND, AND, NOR) gates two, three, four inputs. Each function have many versions, with different combinations active-low inputs. logic module also implement variety D-latches, exclusivity functions, AND-ORs, OR-ANDs. dedicated hard-wired latches flip-flops required array, since latches flip-flops constructed from logic modules wherever needed application.
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42MX devices contain three types logic modules: combinatorial (C-modules), sequential (S-modules), decode (D-modules). C-module shown Figure implements following function: where S0=A0*B0 S1=A1+B1 S-module shown Figure designed implement high-speed sequential functions within single logic module. S-module implements same combinatorial logic function C-module while adding sequential element. sequential element configured either flip-flop transparent latch. increase flexibility, S-module register passed that implements purely combinatorial logic.
Figure C-module Implementation
GATE
7-input function plus D-type flip-flop with clear
7-input function plus latch
GATE
4-input function plus latch with clear
8-input function (same C-module)
Figure S-module Implementation
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Some 42MX devices contain third type logic module, D-modules, which arranged around peripheries devices. D-modules contain wide-decode circuitry, which provides fast, wide-input function similar that found product term architectures (Figure D-module allows 42MX devices perform wide-decode functions speeds comparable CPLDs devices. output D-module programmable inverter active HIGH assertion. D-module output hard-wired output pin, back into array incorporated into other logic.
Dual-Port SRAM Modules
inputs
Hardwire Programmable inverter
Feedback array
Several 42MX devices contain dual-port SRAM modules that have been optimized synchronous asynchronous applications. SRAM modules arranged 256-bit blocks that configured (Refer "Integrator Series Product Profile" table, page 1-91, number SRAM blocks within particular device.) SRAM
Figure D-Module Implementation modules cascaded together form memory spaces user-definable width depth. block diagram 42MX dual-port SRAM block shown Figure
WD[7:0]
Latches [7:0]
[5:0] Write Port Logic SRAM Module (256 bits) Read Port Logic Latches
RDAD[5:0]
WRAD[5:0] Latches
[5:0]
Read Logic
RCLK
MODE BLKEN WCLK Write Logic RD[7:0]
Routing Tracks
Figure 42MX Dual-Port SRAM Block 42MX SRAM modules true dual-port structures containing independent Read Write ports. Each SRAM module contains bits read write addressing (RDAD[5:0] WRAD[5:0], respectively) blocks. When configured byte mode, highest order address bits (RDAD5 WRAD5) used. read write ports SRAM block contain independent clocks (RCLK WCLK) with programmable polarities offering active HIGH implementation. SRAM block contains eight data inputs (WD[7:0]), eight outputs (RD[7:0]) which connected segmented vertical routing tracks. 42MX dual-port SRAM blocks ideal high-speed buffered applications requiring fast FIFO LIFO queues. Actel's ACTgen Macro Builder provides capability design quickly memory functions, such FIFOs, LIFOs,
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arrays. addition, unused SRAM blocks need wasted, since they used implement registers other logic within design.
MultiPlex Modules
C-module, register input output signals. achieve 5.0V 3.3V PCI-compliant output drives A42MX24, A42MX36, A42MX52, chip-wide fuse programmed. When fuse programmed, output drive standard. (See bottom portion Figure Actel's Designer Series development tools provide design library macros. macro library provides macrofunctions that implement configurations supported FPGAs.
Routing Structure
modules provide interface between device pins logic array. Figure block diagram 42MX module. variety user functions, determined library macro selection, implemented module. (Refer Macro Library Guide more information.) 42MX modules contain tristate buffer, with input output latches that configured input, output, bidirectional operation.
From Array
G/CLK*
architecture uses vertical horizontal routing tracks interconnect various logic modules. These routing tracks metal interconnects that either continuous length broken into pieces called segments. Varying segment lengths allows interconnect over design tracks occur with only antifuse connections. Segments joined together ends, using antifuses, increase their lengths full length track. interconnects accomplished with maximum four antifuses.
Horizontal Routing
Array
G/CLK*
configured Latch Flip-Flop (using C-module)
Schematic
Horizontal channels located between rows modules composed several routing tracks. horizontal routing tracks within channel divided into more segments. minimum horizontal segment length width module pair, maximum horizontal segment length full length channel. segment that spans more than one-third length considered long horizontal segment. typical channel shown Figure Nondedicated horizontal routing tracks used route signal nets. Dedicated routing tracks used global clock networks power ground tie-off tracks.
Vertical Routing
Signal Output Drive Enable Fuse
Figure Module Integrator Series devices contain flexible structures, that each output dedicated output-enable control. module used latch input output data, both, providing fast setup time. addition, Actel Designer software tools build flip-flop, using
Another routing tracks vertically through module. Vertical tracks three types: input, output, long. Vertical tracks also divided into more segments. Each segment input track dedicated input particular module. Each segment output track dedicated output particular module. Long segments uncommitted assigned during routing. Each output segment spans four channels (two above below), except near bottom array, where edge effects occur. LVTs contain either segments. example vertical routing tracks segments shown Figure
Antifuse Structures
antifuse "normally open" structure opposed normally closed fuse structure used PROMs PALs. antifuses implement programmable logic device results highly testable structures well efficient
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Segmented horizontal routing tracks
Logic Modules
CLKB CLKA FROM PADS CLKMOD
CLKINB CLKINA INTERNAL SIGNAL CLKO(17)
Antifuses CLOCK DRIVERS
CLKO(16) CLKO(15)
Vertical routing tracks CLKO(2) CLKO(1)
Figure Routing Structure programming algorithms. structure highly testable because there preexisting connections; therefore, temporary connections made using pass transistors. These temporary connections isolate individual antifuses programmed individual circuit structures tested. This done both before after programming. example, metal tracks tested continuity shorts between adjacent tracks, functionality logic modules verified.
Clock Networks
CLOCK TRACKS
Figure Clock Networks networks (Figure Each quadrant clock provides local, high-fanout resource contiguous logic modules within quadrant device. Quadrant clock signals originate from specific pins from internal array used secondary register clock, register clear, output enable.
Test Circuitry
40MX devices have global distribution network. low-skew, high fanout clock distribution networks provided each 42MX device. These networks referred CLK0 CLK1. Each network clock module (CLKMOD) that selects source clock signal driven follows: Externally from CLKA Externally from CLKB Internally from CLKINA input Internally from CLKINB input clock modules located modules. Clock drivers dedicated horizontal clock track located each horizontal routing channel. user controls clock module selecting clock macros from macro library. macro CLKBUF used connect external clock pins clock network, macro CLKINT used connect internally generated clock signal clock network. Since both clock networks identical, user does care whether CLK0 CLK1 being used. clock input pads also used normal I/Os, bypassing clock networks. (See Figure 42MX devices that contain SRAM modules have four additional register control resources, called quadrant clock
Both 40MX 42MX devices provide means test debug design once programmed into device. 40MX 42MX devices contain Actel's Actionprobe® test facility. Once device been programmed, Actionprobe test facility allows designer probe internal node during device operation debugging design. addition, 42MX devices contain JTAG 1149.1 Boundary Scan Test.
JTAG Boundary Scan Testing (BST)
Device spacing decreasing with advent fine-pitch packages such TQFP BGA, manufacturers routinely implementing surface-mount technology with multilayer boards. Boundary scan becoming attractive tool help system manufacturers test their boards. Joint Test Action Group (JTAG) developed IEEE Boundary Scan standard 1149.1 facilitate board-level testing during manufacturing. IEEE Standard 1149.1 defines four-pin Test Access Port (TAP) interface testing integrated circuits system. 42MX family provides four JTAG pins: Test Data (TDI), Test Data (TDO), Test Clock (TCLK), Test Mode Select (TMS). Devices configured JTAG "chain"
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where data transmitted serially between devices TDO-to-TDI interconnections. TCLK signals shared among devices JTAG chain that components operate same state. 42MX family implements subset IEEE 1149.1 instruction, addition private instruction, allow Actel's Actionprobe facility with JTAG BST. Refer
IEEE 1149.1 specification detailed information regarding JTAG testing.
JTAG Architecture
42MX JTAG circuitry consist Test Access Port (TAP) controller, JTAG instruction register, JPROBE register, bypass register, boundary scan register. Figure block diagram 42MX JTAG circuitry.
QCLKA Quad Clock Module Quad Clock Module
QCLKC
QCLKB *QCLK1IN
QCLK1
QCLK3
QCLKD *QCLK3IN
Quad Clock Module *QCLK2IN
QCLK2
QCLK4
Quad Clock Module *QCLK4IN
*QCLK1IN, QCLK2IN, QCLK3IN, QCKL4IN internally generated signals.
Figure Quadrant Clock Network
JPROBE Register Boundary Scan Register Bypass Register Control Logic Output
Controller TCLK Instruction Register
Instruction Decode
Figure JTAG Circuitry
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When device operating JTAG mode, four pins used TDI, TDO, TMS, TCLK signals. active reset (nTRST) supported. However 42MX contains power-on reset circuitry that resets JTAG circuitry upon power-up. During normal device operation, JTAG pins should held disable JTAG circuitry. following table summarizes functions JTAG signals.
JTAG Signal Name Test Data Function Serial data input JTAG instructions data. Data shifted rising edge TCLK. Serial data output JTAG instructions test data. Serial data input JTAG test mode. Data shifted rising edge TCLK. Clock signal shift JTAG data into device.
Test Mode EXTEST
Code
Description Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins. Allows snapshot signals device pins captured examined during device operation. Refer IEEE 1149.1 specification. private instruction allowing user connect Actel's Micro Probe registers JTAG chain. Allows user build application-specific instructions such READ WRITE. Refer IEEE 1149.1 specification. Refer IEEE 1149.1 specification. Enables bypass register between pins. test data passes through selected device adjacent devices JTAG chain.
SAMPLE/ PRELOAD
INTEST JPROBE
Test Data Test Mode Select Test Clock
USER INSTRUCTION
TCLK
HIGH CLAMP BYPASS
JTAG Instructions
JTAG testing within 42MX devices controlled Test Access Port (TAP) state machine. controller drives three-bit instruction register, bypass register, boundary scan data registers within device. controller uses signal control JTAG testing device. JTAG test mode determined stream entered pin. table next column describes JTAG instructions supported 42MX.
Actionprobe
device been successfully programmed security fuse been programmed, internal logic module output observed using Actionprobe circuitry and/or pins. Actionprobe diagnostic system provides software hardware required perform real-time debugging. Refer "Using Actionprobe System-Level Debug" application note further information.
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5.0V Operating Conditions Absolute Maximum Ratings
Free temperature range
Recommended Operating Conditions
Parameter Temperature Range1 Commercial Industrial Units
Symbol Parameter TSTG Supply Voltage Input Voltage Output Voltage Source/Sink Current2 Storage Temperature
Limits -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +150
Units
Power Supply Tolerance
%VCC
Note: Ambient temperature (TA) used commercial industrial.
Notes: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Device should operated outside Recommended Operating Conditions. Device inputs normally high impedance draw extremely current. However, when input voltage greater than less than internal protection diode will forward biased draw excessive current.
Electrical Specifications
Commercial Symbol VOH1 Parameter Min. (IOH (IOH (IOH VOL1 Input Transition Time Capacitance2, Standby Current, ICC4 (typical ICC(D) Dynamic Supply Current Power Mode Standby Current, Power Current During Power-Up Notes: Only output tested time. min. tested, information only. Includes worst-case 84-pin CPGA package capacitance. VOUT MHz. outputs unloaded. inputs GND; typical 0.25 limit includes during normal operation. (IOL (IOL -0.3 0.33 -0.3 0.33 -0.3 0.40 3.84 Max. Min. 3.84 Max. Min. Max. Commercial Industrial Units
"Power Dissipation" page 1-21.
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3.3V Operating Conditions Absolute Maximum Ratings
Free temperature range
Recommended Operating Conditions
Parameter Temperature Range1 Commercial Industrial Units
Symbol TSTG
Parameter Supply Voltage Input Voltage Output Voltage Source Sink Current2 Storage Temperature
Limits -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +150
Units
Power Supply Tolerance
Note: Ambient temperature (TA) used commercial.
Notes: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Device should operated outside Recommended Operating Conditions. Device inputs normally high impedance draw extremely current. However, when input voltage greater than less than internal protection diodes will forward bias draw excessive current.
Electrical Specifications
Commercial Parameter Min. VOH1 VOL1 Input Transition Time Capacitance2, Standby Current, ICC4 (typical (IOH (IOH -3.2 (IOL -0.3 2.15 0.75 -0.3 0.48 0.75 Max. Min. Max. Industrial Units
ICC(D) Dynamic Supply Current Power Mode Standby Current, Power Current During Power-Up
"Power Dissipation" page 1-21.
Notes: Only output tested time. min. tested, information only. Includes worst-case 84-pin PLCC package capacitance. VOUT MHz. Typical standby current outputs unloaded. inputs GND.
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Package Thermal Characteristics
device junction-to-case thermal characteristic junction-to-ambient characteristic thermal characteristics shown with different flow rates.
Maximum junction temperature 150°C. sample calculation absolute maximum power dissipation allowed PQFP 160-pin package commercial temperature follows:
150°C 70°C Max. junction temp. (°C) Max. commercial temp. 2.6W (°C/W) 30°C/W Package Type Count Plastic Quad Flatpack Plastic Quad Flatpack Plastic Quad Flatpack Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Thin Quad Flatpack Power Quad Flatpack Power Quad Flatpack Still °C/W °C/W °C/W °C/W °C/W °C/W °C/W 16.8 °C/W 16.1 °C/W ft/min °C/W °C/W 16.2 °C/W °C/W °C/W °C/W °C/W 11.4 °C/W 10.6 °C/W Still ft/min Maximum Power Dissipation
Power Dissipation
General Power Equation
power standby current typically small component overall power. Standby power calculated commercial, worst-case conditions: 5.25 Power 10.5
[ICCstandby ICCactive] IOL* VOL* (VCC VOH) where: ICCstandby current flowing when inputs outputs changing. ICCactive current flowing CMOS switching. IOL, sink/source currents. VOL, level output voltages. equals number outputs driving loads VOL. equals number outputs driving loads VOH. accurate determination problematic because their values depend family type, design details, system I/O. power divided into components: static active.
Static Power Component
static power dissipation loads depends number outputs driving high load current. Again, this number typically small. instance, 32-bit sinking 0.33 will generate with outputs driving with outputs driving high. actual dissipation will average somewhere between, I/Os switch states with time.
Active Power Component
Actel FPGAs have small static power components that result power dissipation lower than PALs PLDs. integrating multiple PALs/PLDs into FPGA, even greater reduction board-level power dissipation achieved.
Power dissipation CMOS devices usually dominated active (dynamic) power dissipation. This component frequency dependent, function logic external I/O. Active power dissipation results from charging internal chip capacitances interconnect, unprogrammed antifuses, module inputs, module outputs, plus external capacitance board traces load device inputs. additional component active power dissipation totem-pole current CMOS transistor pairs. effect associated with equivalent capacitance that combined with frequency voltage represent active power dissipation.
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Equivalent Capacitance
Average logic module switching rate Average input buffer switching rate Average output buffer switching rate Average first routed array clock rate Average second routed array clock rate
power dissipated CMOS circuit expressed Equation Power (µW) VCC2 where:
equivalent capacitance expressed picofarads (pF). power supply volts (V). switching frequency megahertz (MHz).
Fixed Capacitance Values Actel FPGAs (pF)
Equivalent capacitance calculated measuring ICCactive specified frequency voltage each circuit component interest. Measurements have been made over range frequencies fixed value VCC. Equivalent capacitance frequency independent that results used over wide range operating conditions. Equivalent capacitance values shown below.
Values Actel FPGAs
Device Type A40MX02 A40MX04 A40MX09 A42MX16 A42MX24 A42MX36 A42MX52
routed_Clk1 41.4 68.6
routed_Clk2
Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR)
11.6 23.8
Determining Average Switching Frequency
calculate active power dissipated from complete design, switching frequency each part logic must known. Equation shows piece-wise linear summation over components. Power VCC2 CEQM fm)Modules CEQI fn)Inputs (CEQO fp)outputs CEQCR fq1)routed_Clk1 fq1)routed_Clk1 CEQCR fq2)routed_Clk2 fq2)routed_Clk2 where: CEQI Number logic modules switching frequency Number input buffers switching frequency Number output buffers switching frequency Number clock loads first routed array clock Number clock loads second routed array clock Fixed capacitance first routed array clock Fixed capacitance second routed array clock Equivalent capacitance input buffers
determine switching frequency design, must have detailed understanding data input values circuit. following guidelines meant represent worst-case scenarios that they generally used predict upper limits power dissipation. These guidelines follows: Logic Modules combinatorial modules inputs/4 outputs/4 sequential modules sequential modules
Inputs switching Outputs switching First routed array clock loads (q1) Second routed array clock loads (q2) Load capacitance (CL)
Average logic module switching rate F/10 (fm) Average input switching rate (fn) Average output switching rate (fp) F/10
CEQM Equivalent capacitance logic modules CEQO Equivalent capacitance output buffers CEQCR Equivalent capacitance routed array clock Output load capacitance
Average first routed array clock rate (fq1) Average second routed array clock rate (fq2)
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40MX Timing Model*
Input Delay Module tINYL tIRD2
Internal Delays
Predicted Routing Delays
Output Delay Module
Logic Module
tDLH tIRD1 tIRD4 tIRD8 tRD1 tRD2 tRD4 tRD8 tENHZ 11.6
ARRAY CLOCK
tCKH FMAX
Values shown 40MX speed' devices worst-case commercial conditions.
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42MX Timing Model*
Input Delays
Internal Delays
Combinatorial Module Logic Module tINYL IRD2
Predicted Routing Delays
Output Delays Module
tDLH tRD1 tRD2 tRD4 tRD8
tINH tINSU tINGL Sequential Logic Module
Combinatorial Logic included tSUD
Module tDLH
tRD1
tENHZ
tOUTH tOUTSU tGLH
ARRAY CLOCKS
tCKH FMAX
tSUD
tLCO 10.7 loads, pad-pad)
*Values shown A42MX09-2 worst-case commercial conditions
Input module predicted routing delay
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42MX Timing Model (Logic Functions using Quadrant Clocks)*
Input Delays Module tINPY IRD1
Internal Delays
Predicted Routing Delays
Output Delays Module
Combinatorial Module tRD1 tRD2 tRD4
tDLH
tINH tINSU tINGO Decode Module tPDD Module tDLH
tRDD
Sequential Logic Module
Combinatorial Logic included tSUD
tRD1
tENHZ
tLSU tGHL=
tSUD QUADRANT CLOCKS tCKH ns**
FMAX
Preliminary values shown A42MX36-2 worst-case commercial conditions Load dependent
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42MX Timing Model (SRAM Functions)*
Input Delays Module tINPY IRD1
tINSU tINH tINGO
Predicted Routing Delays [7:0] WRAD [5:0] BLKEN WCLK tADSU tADH tWENSU tBENS [7:0] RDAD [5:0] tRD1
Module tDLH
RCLK tADSU tADH tRENSU tRCO
tGHL= tLSU
ARRAY CLOCKS FMAX
*Values shown A42MX36-2 worst-case commercial conditions.
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Parameter Measurement
Output Buffer Delays
TRIBUFF test loads (shown below)
tENLZ
tENHZ
tDLH
tDHL
tENZL
tENZH
Test Loads
Load (Used measure propagation delay)
Load (Used measure rising/falling edges)
output under test
output under test
tPLZ/tPZL tPHZ/tPZH
Input Buffer Delays
Module Delays
INBUF
tINYH tINYL
tPLH tPHL tPLH
tPHL
1-111
Sequential Module Timing Characteristics
Flip-Flops Latches
(Positive edge triggered)
tSUD tSUENA tHENA PRE, tWASYN tWCLKI tWCLKA
Note:
represents data functions involving multiplexed flip-flops.
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Sequential Timing Characteristics (continued)
Input Buffer Latches
DATA
IBDL
CLKBUF
DATA tINH tINSU tHEXT tSUEXT
Output Buffer Latches
OBDLHS
tOUTSU tOUTH
1-113
Decode Module Timing
A-G, tPHL tPLH
SRAM Timing Characteristics
Write Port WRAD [5:0] BLKEN WCLK [7:0] Array 32x8 64x4 (256 bits)
Read Port RDAD [5:0] RCLK [7:0]
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Dual-Port SRAM Timing Waveforms
42MX SRAM Write Operation
tRCKHL WCLK tADSU WD[7:0] WRAD[5:0] Valid tWENSU tBENSU BLKEN Valid tBENH tWENH tADH
tRCKHL
Note:
Identical timing falling-edge clock.
42MX SRAM Synchronous Read Operation
tCKHL RCLK
tRCKHL
tRENSU tADSU RDAD[5:0] Valid
tRENH
tADH
tRCO tDOH RD[7:0] Data Data
Note:
Identical timing falling-edge clock.
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42MX SRAM Asynchronous Read Operation-Type
(Read Address Controlled)
tRDADV RDAD[5:0] ADDR1 tDOH RD[7:0] Data ADDR2 tRPD Data
42MX SRAM Asynchronous Read Operation-Type
(Write Address Controlled)
tWENSU
tWENH
WD[7:0] WRAD[5:0] BLKEN
Valid tADSU tADH tRPD tDOH
WCLK
RD[7:0]
Data
Data
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Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends resistive capacitive loading routing tracks, interconnect elements, module inputs being driven. Propagation delay increases length routing tracks, number interconnect elements, number inputs increases. From design perspective, propagation delay statistically correlated modeled fanout (number loads) driven module. Higher fanout usually requires some paths have longer routing tracks. FPGAs deliver tight fanout delay distribution. This tight distribution achieved ways: decreasing delay interconnect elements decreasing number interconnect elements path. Actel's patented PLICE antifuse offers extremely very resistive/capacitive interconnect. antifuses, fabricated 0.45 micron lithography, offer nominal levels ohms resistance femtofarad (fF) capacitance antifuse. Integrator Series fanout distribution also tight number antifuses required each interconnect path. proprietary architecture limits number antifuses path maximum four, with interconnects using antifuses.
Timing Characteristics
determined until after placement routing user's design complete. Delay values then determined using Designer Series utility performing simulation with post-layout delays.
Critical Nets Typical Nets
Propagation delays expressed only typical nets, which used initial design performance evaluation. Since architecture provides deterministic timing abundant routing resources, Actel's Designer Series development tools offers DirectTime, timing-driven place-and-route tool. Using DirectTime, designer specify timing-critical nets system clock frequency. Using these timing specifications, place-and-route software optimizes layout design meet user's specifications.
Long Tracks
Some nets design long tracks, which special routing resources that span multiple rows, columns, modules. Long tracks employ three sometimes four antifuse connections, which increase capacitance resistance, resulting longer delays macros connected long tracks. Typically, nets fully utilized device require long tracks. Long tracks approximately delay. This additional delay represented statistically higher fanout (FO=8) routing delays data sheet specifications section.
Timing Derating
Timing characteristics devices fall into three categories: family dependent, device dependent, design dependent. input output buffer characteristics common Integrator Series members. Internal routing delays device dependent. Design dependency means actual delays
best-case timing derating factor 0.45 used reflect best case processing. Note that this factor relative standard-speed timing parameters must multiplied appropriate voltage temperature derating factors given application.
Timing Derating Factor (Tem perature Voltage)
Industrial Min. (Commercial Specification) 0.69 Max. 1.11
Timing Derating Factor Designs Typical Temperature 25°C) Voltage (5.0
(Maximum Specification, Worst-Case Condition) 0.85
Note:
This derating factor applies routing propagation delays.
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Temperature Voltage Deratin Factors (Normalized Worst-Case Commercial, 4.75 70°C)
4.50 4.75 5.00 5.25 5.50 0.75 0.71 0.69 0.68 0.67 0.79 0.75 0.72 0.69 0.69 0.86 0.82 0.80 0.77 0.76 0.92 0.87 0.85 0.82 0.81 1.06 1.00 0.97 0.95 0.93 1.11 1.05 1.02 0.98 0.97 1.23 1.16 1.13 1.09 1.08
Junction Temperature Voltage Derating Curves (normalized Worst-Case Commercial, 4.75 70°C)
4.50 4.75 5.00 Voltage 5.25 5.50 25°C -40°C -55°C
Derating Factor
125°C 85°C 70°C
Note:
This derating factor applies routing propagation delays.
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A40MX02 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, 4.75 70°C)
Logic Module Propagation Delays Parameter Description tPD1 tPD2 Single Module Dual Module Macros Sequential Latch Flip-Flop (Latch) Reset
`-2' Speed Min. Max. 1.54 3.06 1.54 1.54 1.54
`-1' Speed Min. Max. 1.74 3.47 1.74 1.74 1.74
`Std' Speed Min. Max. 2.05 4.08 2.05 2.05 2.05
`-F' Speed Min. Max. 2.87 5.71 2.87 2.87 2.87 Units
Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Characteristics3 3.38 0.00 3.38 0.00 4.13 4.13 5.59 167.50 3.83 0.00 3.83 0.00 4.68 4.68 6.33 154.10 4.50 0.00 4.50 0.00 5.50 5.50 7.45 134.00 6.30 0.00 6.30 0.00 7.70 7.70 10.43 80.40 1.48 2.08 2.69 3.29 5.69 1.67 2.35 3.04 3.72 6.45 1.97 2.77 3.58 4.38 7.59 2.76 3.88 5.01 6.13 10.63
Sequential Timing tSUD tHD4 tSUENA tHENA tWCLKA tWASYN fMAX
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment. Setup times assume fanout Further testing information obtained from DirectTime Analyzer utility. Hold Time DFME1A macro greater than Designer later Timer check Hold Time this macro.
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A40MX02 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter Description tINYH tINYL High
`-2' Speed Min. Max. 1.36 1.36
`-1' Speed Min. Max. 1.54 1.54
`Std' Speed Min. Max. 1.81 1.81
`-F' Speed Min. Max. 2.53 2.53 Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.84 3.44 4.04 4.64 7.05 3.21 3.89 4.58 5.26 7.99 3.78 4.58 5.39 6.19 9.40 5.29 6.41 7.55 8.67 13.16
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 5.39 5.59 174.79 167.50 2.58 2.71 2.58 2.71 0.45 0.62 6.10 6.33 159.85 154.10 3.92 3.92 4.22 4.22 2.92 3.07 2.92 3.07 0.51 0.70 7.18 7.45 139.00 134.00 4.44 4.44 4.79 4.79 3.44 3.61 3.44 3.61 0.60 0.82 10.05 10.43 83.40 80.40 5.22 5.22 5.63 5.63 4.82 5.05 4.82 5.05 0.84 1.15 7.31 7.31 7.88 7.88
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment.
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A40MX02 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data High Data Enable High Enable Enable High Enable Delta High Delta High Module Timing1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
3.68 4.61 4.38 5.44 7.40 5.14 0.02 0.03
4.17 5.22 4.96 6.16 8.39 5.82 0.03 0.03
4.91 6.14 5.84 7.25 9.87 6.85 0.03 0.04
6.87 8.60 8.18 10.15 13.82 9.59 0.04 0.06
ns/pF ns/pF
CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data High Data Enable High Enable Enable High Enable Delta High Delta High
4.36 3.92 4.03 5.66 7.40 5.14 0.04 0.02
4.94 4.45 4.56 6.41 8.39 5.82 0.04 0.03
5.81 5.23 5.37 7.54 9.87 6.85 0.05 0.03
8.13 7.32 7.52 10.56 13.82 9.59 0.07 0.04
ns/pF ns/pF
Notes: Delays based loading. information found "Simultaneous Switching Output Limits Actel FPGAs" application note page 4-125.
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A40MX02 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, 4.75 70°C)
Logic Module Propagation Delays Parameter Description tPD1 tPD2 Single Module Dual Module Macros Sequential Latch Flip-Flop (Latch) Reset
`-2' Speed Min. Max. 2.15 4.28 2.15 2.15 2.15
`-1' Speed Min. Max. 2.44 4.86 2.44 2.44 2.44
`Std' Speed Min. Max. 2.87 5.71 2.87 2.87 2.87
`-F' Speed Min. Max. 4.02 8.00 4.02 4.02 4.02 Units
Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Characteristics3 4.73 0.00 4.73 0.00 5.78 5.78 7.82 100.50 5.36 0.00 5.36 0.00 6.55 6.55 8.87 92.46 6.30 0.00 6.30 0.00 7.70 7.70 10.43 80.40 8.82 0.00 8.82 0.00 10.78 10.78 14.60 48.24 2.07 2.91 3.76 4.60 7.97 2.34 3.30 4.26 5.21 9.03 2.76 3.88 5.01 6.13 10.63 3.86 5.43 7.02 8.58 14.88
Sequential Timing tSUD tHD4 tSUENA tHENA tWCLKA tWASYN fMAX
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
Notes: 3.3V specifications. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment. Setup times assume fanout Further testing information obtained from DirectTime Analyzer utility. Hold Time DFME1A macro greater than Designer later Timer check Hold Time this macro.
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A40MX02 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter Description tINYH tINYL High
`-2' Speed Min. Max. 1.90 1.90
`-1' Speed Min. Max. 2.15 2.15
`Std' Speed Min. Max. 2.53 2.53
`-F' Speed Min. Max. 3.55 3.55 Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3.97 4.81 5.66 6.50 9.87 4.50 5.45 6.41 7.37 11.19 5.29 6.41 7.55 8.67 13.16 7.41 8.89 10.56 12.13 18.42
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input High Input High 3.61 3.79 3.61 3.79 0.63 0.86 7.54 7.82 104.88 100.50 8.54 8.87 95.91 92.46 5.48 5.48 5.91 5.91 4.09 4.30 4.09 4.30 0.71 0.98 10.05 10.43 83.40 80.40 6.21 6.21 6.70 6.70 4.82 5.05 4.82 5.05 0.84 1.15 14.07 14.60 50.04 48.24 7.31 7.31 7.88 7.88 6.74 7.08 6.74 7.08 1.18 1.61 10.23 10.23 11.03 11.03
Minimum Pulse Width High Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment.
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A40MX02 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data High Data Enable High Enable Enable High Enable Delta High Delta High Module Timing1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
5.16 6.45 6.13 7.61 10.36 7.19 0.03 0.04
5.84 7.31 6.95 8.63 11.75 8.15 0.04 0.05
6.87 8.60 8.18 10.15 13.82 9.59 0.04 0.06
9.62 12.03 11.45 14.21 19.35 13.43 0.06 0.08
ns/pF ns/pF
CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data High Data Enable High Enable Enable High Enable Delta High Delta High
6.10 5.49 5.64 7.92 10.36 7.19 0.05 0.03
6.91 6.22 6.39 8.97 11.75 8.15 0.06 0.04
8.13 7.32 7.52 10.56 13.82 9.59 0.07 0.04
11.39 10.25 10.53 14.78 19.35 13.43 0.10 0.06
ns/pF ns/pF
Notes: Delays based loading. information found "Simultaneous Switching Output Limits Actel FPGAs" application note page 4-125.
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A40MX04 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, 4.75 70°C)
Logic Module Propagation Delays Parameter Description tPD1 tPD2 Single Module Dual Module Macros Sequential Latch Flip-Flop (Latch) Reset
`-2' Speed Min. Max. 1.54 3.06 1.54 1.54 1.54
`-1' Speed Min. Max. 1.74 3.47 1.74 1.74 1.74
`Std' Speed Min. Max. 2.05 4.08 2.05 2.05 2.05
`-F' Speed Min. Max. 2.87 5.71 2.87 2.87 2.87 Units
Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Characteristics3 3.38 0.00 3.38 0.00 4.13 4.13 5.59 167.50 3.83 0.00 3.83 0.00 4.68 4.68 6.33 154.10 4.50 0.00 4.50 0.00 5.50 5.50 7.45 134.00 6.30 0.00 6.30 0.00 7.70 7.70 10.43 80.40 1.48 2.08 2.69 3.29 5.69 1.67 2.35 3.04 3.72 6.45 1.97 2.77 3.58 4.38 7.59 2.76 3.88 5.01 6.13 10.63
Sequential Timing tSUD tHD4 tSUENA tHENA tWCLKA tWASYN fMAX
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment. Setup times assume fanout Further testing information obtained from DirectTime Analyzer utility. Hold Time DFME1A macro greater than Designer later Timer check Hold Time this macro.
1-125
A40MX04 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter Description tINYH tINYL High
`-2' Speed Min. Max. 1.36 1.36
`-1' Speed Min. Max. 1.54 1.54
`Std' Speed Min. Max. 1.81 1.81
`-F' Speed Min. Max. 2.53 2.53 Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.84 3.44 4.04 4.64 7.05 3.21 3.89 4.58 5.26 7.99 3.78 4.58 5.39 6.19 9.40 5.29 6.41 7.55 8.67 13.16
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 5.39 5.59 174.79 167.50 2.58 2.71 2.58 2.71 0.45 0.62 6.10 6.33 159.85 154.10 3.92 3.92 4.22 4.22 2.92 3.07 2.92 3.07 0.51 0.70 7.18 7.45 139.00 134.00 4.44 4.44 4.79 4.79 3.44 3.61 3.44 3.61 0.60 0.82 10.05 10.43 83.40 80.40 5.22 5.22 5.63 5.63 4.82 5.05 4.82 5.05 0.84 1.15 7.31 7.31 7.88 7.88
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment.
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A40MX04 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data High Data Enable High Enable Enable High Enable Delta High Delta High Module Timing1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
3.68 4.61 4.38 5.44 7.40 5.14 0.02 0.03
4.17 5.22 4.96 6.16 8.39 5.82 0.03 0.03
4.91 6.14 5.84 7.25 9.87 6.85 0.03 0.04
6.87 8.60 8.18 10.15 13.82 9.59 0.04 0.06
ns/pF ns/pF
CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data High Data Enable High Enable Enable High Enable Delta High Delta High
4.36 3.92 4.03 5.66 7.40 5.14 0.04 0.02
4.94 4.45 4.56 6.41 8.39 5.82 0.04 0.03
5.81 5.23 5.37 7.54 9.87 6.85 0.05 0.03
8.13 7.32 7.52 10.56 13.82 9.59 0.07 0.04
ns/pF ns/pF
Notes: Delays based loading. information found "Simultaneous Switching Output Limits Actel FPGAs" application note page 4-125.
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A40MX04 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, 4.75 70°C)
Logic Module Propagation Delays Parameter Description tPD1 tPD2 Single Module Dual Module Macros Sequential Latch Flip-Flop (Latch) Reset
`-2' Speed Min. Max. 2.15 4.28 2.15 2.15 2.15
`-1' Speed Min. Max. 2.44 4.86 2.44 2.44 2.44
`Std' Speed Min. Max. 2.87 5.71 2.87 2.87 2.87
`-F' Speed Min. Max. 4.02 8.00 4.02 4.02 4.02 Units
Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Characteristics3 4.73 0.00 4.73 0.00 5.78 5.78 7.82 100.50 5.36 0.00 5.36 0.00 6.55 6.55 8.87 92.46 6.30 0.00 6.30 0.00 7.70 7.70 10.43 80.40 8.82 0.00 8.82 0.00 10.78 10.78 14.60 48.24 2.07 2.91 3.76 4.60 7.97 2.34 3.30 4.26 5.21 9.03 2.76 3.88 5.01 6.13 10.63 3.86 5.43 7.02 8.58 14.88
Sequential Timing tSUD tHD4 tSUENA tHENA tWCLKA tWASYN fMAX
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
Notes: 3.3V specifications. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment. Setup times assume fanout Further testing information obtained from DirectTime Analyzer utility. Hold Time DFME1A macro greater than Designer later Timer check Hold Time this macro.
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A40MX04 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter Description tINYH tINYL High
`-2' Speed Min. Max. 1.90 1.90
`-1' Speed Min. Max. 2.15 2.15
`Std' Speed Min. Max. 2.53 2.53
`-F' Speed Min. Max. 3.55 3.55 Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3.97 4.81 5.66 6.50 9.87 4.50 5.45 6.41 7.37 11.19 5.29 6.41 7.55 8.67 13.16 7.41 8.89 10.56 12.13 18.42
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input High Input High 3.61 3.79 3.61 3.79 0.63 0.86 7.54 7.82 104.88 100.50 8.54 8.87 95.91 92.46 5.48 5.48 5.91 5.91 4.09 4.30 4.09 4.30 0.71 0.98 10.05 10.43 83.40 80.40 6.21 6.21 6.70 6.70 4.82 5.05 4.82 5.05 0.84 1.15 14.07 14.60 50.04 48.24 7.31 7.31 7.88 7.88 6.74 7.08 6.74 7.08 1.18 1.61 10.23 10.23 11.03 11.03
Minimum Pulse Width High Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment.
1-129
A40MX04 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data High Data Enable High Enable Enable High Enable Delta High Delta High Module Timing1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
5.16 6.45 6.13 7.61 10.36 7.19 0.03 0.04
5.84 7.31 6.95 8.63 11.75 8.15 0.04 0.05
6.87 8.60 8.18 10.15 13.82 9.59 0.04 0.06
9.62 12.03 11.45 14.21 19.35 13.43 0.06 0.08
ns/pF ns/pF
CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data High Data Enable High Enable Enable High Enable Delta High Delta High
6.10 5.49 5.64 7.92 10.36 7.19 0.05 0.03
6.91 6.22 6.39 8.97 11.75 8.15 0.06 0.04
8.13 7.32 7.52 10.56 13.82 9.59 0.07 0.04
11.39 10.25 10.53 14.78 19.35 13.43 0.10 0.06
ns/pF ns/pF
Notes: Delays based loading. information found "Simultaneous Switching Output Limits Actel FPGAs" application note page 4-125.
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A42MX09 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, 4.75 70°C)
Logic Module Propagation Delays1 Parameter Description tPD1 tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Single Module Sequential Latch Flip-Flop (Latch) Reset
`-2' Speed Min. Max. 1.55 1.37 1.33 1.37
`-1' Speed Min. Max. 1.76 1.56 1.50 1.56
`Std' Speed Min. Max. 2.07 1.83 1.77 1.83
`-F' Speed Min. Max. 2.90 2.56 2.48 2.56 Units
Predicted Routing Delays
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
0.70 0.97 1.24 1.51 2.59
0.79 1.10 1.40 1.71 2.93
0.93 1.29 1.65 2.01 3.45
1.30 1.81 2.31 2.81 4.83
Sequential Timing Characteristics
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency
0.36 0.00 0.45 0.00 3.77 4.94 4.50 0.00 0.30 0.00 0.30
0.41 0.00 0.51 0.00 4.27 5.59 5.10
0.48 0.00 0.60 0.00 5.02 6.58 6.00
0.67 0.00 0.84 0.00 7.03 9.21 8.40
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Setup hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
1-131
A42MX09 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter Description tINYH tINYL tINGH tINGL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 High High
`-2' Speed Min. Max. 1.16 1.43 0.54 5.30
`-1' Speed Min. Max. 1.32 1.62 0.61 6.00
`Std' Speed Min. Max. 1.55 1.91 0.72 7.06
`-F' Speed Min. Max. 2.17 2.67 1.01 9.88 Units
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
2.05 2.34 2.64 2.94 4.13
2.32 2.65 2.99 3.33 4.68
2.73 3.12 3.52 3.92 5.50
3.82 4.37 4.93 5.49 7.70
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input High Input High Minimum Pulse Width High 1.35 1.46 1.35 1.46 0.34 0.34 0.54 0.54 0.00 0.00 4.20 4.50 0.61 0.61 0.00 0.00 4.76 5.10 2.75 3.15 2.54 2.93 1.53 1.66 1.53 1.66 0.38 0.38 0.72 0.72 0.00 0.00 5.60 6.00 3.11 3.57 2.88 3.32 1.80 1.95 1.80 1.95 0.45 0.45 1.01 1.01 0.00 0.00 7.84 8.40 3.66 4.20 3.39 3.90 2.52 2.73 2.52 2.73 0.63 0.63 5.12 5.88 4.75 5.46
Minimum Pulse Width Maximum Skew
Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst case performance
1-132
Fami
A42MX09 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Description Module Timing1 Data High Data Enable High Enable Enable High Enable High Latch Setup Latch Hold Latch Clock-Out (pad-to-pad), clock loading Array Clock-Out (pad-to-pad), clock loading Capacity Loading, High Capacity Loading, High
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
2.71 3.19 2.93 3.24 5.44 5.93 4.61 4.61 0.54 0.00 6.90 9.68 0.03 0.04 0.61 0.00
3.07 3.61 3.32 3.67 6.16 6.72 5.22 5.22 0.72 0.00 7.82 10.97 0.03 0.04
3.61 4.25 3.90 4.32 7.25 7.90 6.14 6.14 1.01 0.00 9.20 12.90 0.04 0.07
5.05 5.95 5.46 6.05 10.15 11.06 8.60 8.60
12.88 18.06 0.06 0.07
ns/pF ns/pF
CMOS Output Module Timing
Data High Data Enable High Enable Enable High Enable High Latch Setup Latch Hold Latch Clock-Out (pad-to-pad), clock loading Array Clock-Out (pad-to-pad), clock loading Capacity Loading, High Capacity Loading, High 0.54 0.00
3.44 2.66 2.93 3.24 5.44 5.93 4.61 4.61 0.61 0.00 6.90 9.68 0.03 0.04
3.89 3.02 3.32 3.67 6.16 6.72 5.22 5.22 0.72 0.00 7.82 10.97 0.03 0.04
4.58 3.55 3.90 4.32 7.25 7.90 6.14 6.14 1.01 0.00 9.20 12.90 0.04 0.05
6.41 4.97 5.46 6.05 10.15 11.06 8.60 8.60
12.88 18.06 0.06 0.07
ns/pF ns/pF
Notes: Delays based loading. information found "Simultaneously Switching Output Limits Actel FPGAs" application note.
1-133
A42MX09 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, 4.75 70°C)
Logic Module Propagation Delays1 Parameter Description tPD1 tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Single Module Sequential Latch Flip-Flop (Latch) Reset
`-2' Speed Min. Max. 2.17 1.92 1.86 1.92
`-1' Speed Min. Max. 2.46 2.18 2.11 2.18
`Std' Speed Min. Max. 2.90 2.56 2.48 2.56
`-F' Speed Min. Max. 4.06 3.59 3.47 3.59 Units
Predicted Routing Delays
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
0.98 1.35 1.73 2.11 3.62
1.11 1.54 1.96 2.39 4.11
1.30 1.81 2.31 2.81 4.83
1.82 2.53 3.23 3.94 6.76
Sequential Timing Characteristics
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency
0.50 0.00 0.63 0.00 5.27 6.91 6.30 0.00 0.30 0.00 0.30
0.57 0.00 0.71 0.00 5.97 7.83 7.14
0.67 0.00 0.84 0.00 7.03 9.21 8.40
0.94 0.00 1.18 0.00 9.84 12.90 11.76
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Setup hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. 3.3V specifications.
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Fami
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter Description tINYH tINYL tINGH tINGL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 High High
`-2' Speed Min. Max. 1.63 2.01 0.76 7.41
`-1' Speed Min. Max. 1.84 2.27 0.86 8.40
`Std' Speed Min. Max. 2.17 2.67 1.01 9.88
`-F' Speed Min. Max. 3.04 3.74 1.41 13.84 Units
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
2.87 3.28 3.70 4.12 5.78
3.25 3.71 4.19 4.66 6.55
3.82 4.37 4.93 5.49 7.70
5.35 6.12 6.90 7.68 10.78
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input High Input High Minimum Pulse Width High 1.89 2.05 1.89 2.05 0.47 0.47 0.76 0.76 0.00 0.00 5.88 6.30 0.86 0.86 0.00 0.00 6.66 7.14 3.84 4.41 3.56 4.10 2.14 2.32 2.14 2.32 0.54 0.54 1.01 1.01 0.00 0.00 7.84 8.40 4.36 5.00 4.03 4.64 2.52 2.73 2.52 2.73 0.63 0.63 1.41 1.41 0.00 0.00 10.98 11.76 5.12 5.88 4.75 5.46 3.53 3.82 3.53 3.82 0.88 0.88 7.17 8.23 6.64 7.64
Minimum Pulse Width Maximum Skew
Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst case performance
1-135
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Description Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Module Timing1 Data High Data Enable High Enable Enable High Enable High Latch Setup Latch Hold Latch Clock-Out (pad-to-pad), clock loading Array Clock-Out (pad-to-pad), clock loading Capacity Loading, High Capacity Loading, High
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
3.79 4.46 4.10 4.54 7.61 8.30 6.45 6.45 0.76 0.00 9.66 13.55 0.04 0.05 0.86 0.00
4.30 5.06 4.64 5.14 8.63 9.40 7.31 7.31 1.01 0.00 10.95 15.35 0.05 0.06
5.05 5.95 5.46 6.05 10.15 11.06 8.60 8.60 1.41 0.00 12.88 18.06 0.06 0.07
7.08 8.33 7.64 8.47 14.21 15.48 12.03 12.03
18.03 25.28 0.08 0.10
ns/pF ns/pF
CMOS Output Module Timing Data High Data
4.81 3.73 4.10 4.54 7.61 8.30 6.45 6.45 0.76 0.00 9.66 13.55 0.04 0.05 0.86 0.00
5.45 4.22 4.64 5.14 8.63 9.40 7.31 7.31 1.01 0.00 10.95 15.35 0.05 0.06
6.41 4.97 5.46 6.05 10.15 11.06 8.60 8.60 1.41 0.00 12.88 18.06 0.06 0.07
8.98 6.96 7.64 8.47 14.21 15.48 12.03 12.03
Enable High Enable Enable High Enable High Latch Setup Latch Hold Latch Clock-Out (pad-to-pad), clock loading Array Clock-Out (pad-to-pad), clock loading Capacity Loading, High Capacity Loading, High
18.03 25.28 0.08 0.10
ns/pF ns/pF
Notes: Delays based loading. information found "Simultaneously Switching Output Limits Actel FPGAs" application note.
1-136
Fami
A42MX16 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, 4.75 70°C)
Logic Module Propagation Delays1 Parameter tPD1 tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Description Single Module Sequential Latch Flip-Flop (Latch) Reset
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Predicted Routing Delays
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Sequential Timing Characteristics
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency
10.0
14.0
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Setup hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
1-137
A42MX16 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter tINYH tINYL tINGH tINGL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Description High High
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
12.3
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input High Input High 13.7 12.5 13.9
Minimum Pulse Width High Minimum Pulse Width Maximum Skew
Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment.
1-138
Fami
A42MX16 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Description Module Timing1 Data High Data Enable High Enable Enable High Enable High Latch Clock-Out (pad-to-pad), clock loading Array Clock-Out (pad-to-pad), clock loading Capacitive Loading, High Capacitive Loading, High
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
0.03 0.04
12.9 0.04 0.05
11.7 10.8 10.9 12.0 12.9 18.1 0.06 0.07
ns/pF ns/pF
11.0 0.03 0.04
CMOS Output Module Timing
Data High Data Enable High Enable Enable High Enable High Latch Clock-Out (pad-to-pad), clock loading Array Clock-Out (pad-to-pad), clock loading Capacitive Loading, High Capacitive Loading, High
0.03 0.04
11.0 0.03 0.04
10.0 12.9 0.04 0.05
13.0 12.9 13.0 14.0 12.9 18.1 0.06 0.07
ns/pF ns/pF
Notes: Delays based loading. information found "Simultaneously Switching Output Limits Actel FPGAs" application note.
1-139
A42MX16 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, 4.75 70°C)
Logic Module Propagation Delays1 Parameter tPD1 tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Description Single Module Sequential Latch Flip-Flop (Latch) Reset
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Predicted Routing Delays
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Sequential Timing Characteristics
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency
10.5
11.9
14.0
12.9 19.6
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Setup hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. 3.3V specifications.
1-140
Fami
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays Parameter tINYH tINYL tINGH tINGL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Description High High
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
10.5
12.3
10.4 12.0 17.2
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input High Input High 10.3 10.4 11.7 10.6 11.8 13.7 12.5 13.9 12.7 19.2 17.4 19.4 10.6 10.6
Minimum Pulse Width High Minimum Pulse Width Maximum Skew
Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency
Note: These parameters should used estimating device performance. Optimization techniques further reduce delays Routing delays typical designs across worst-case operating conditions. Post-route timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment.
1-141
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Output Module Timing Parameter Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Description Module Timing1 Data High Data Enable High Enable Enable High Enable High Latch Clock-Out (pad-to-pad), clock loading Array Clock-Out (pad-to-pad), clock loading Capacitive Loading, High Capacitive Loading, High
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
10.0 10.2 10.9 15.4 0.05 0.06
11.7 10.8 10.9 12.0 12.9 18.1 0.06 0.07
16.4 15.1 15.3 16.8 18.0 25.3 0.08 0.10
ns/pF ns/pF
13.5 0.04 0.05
CMOS Output Module Timing
Data High Data Enable High Enable Enable High Enable High Latch Clock-Out (pad-to-pad), clock loading Array Clock-Out (pad-to-pad), clock loading Capacitive Loading, High Capacitive Loading, High
10.5 13.5 0.04 0.05
11.1 11.0 11.0 11.9 10.9 15.4 0.05 0.06
13.0 12.9 13.0 14.0 12.9 18.1 0.06 0.07
10.5 11.3 18.2 18.1 18.1 19.6 18.0 25.3 0.08 0.10
ns/pF ns/pF
Notes: Delays based loading. information found "Simultaneously Switching Output Limits Actel FPGAs" application note.
1-142
Fami
A42MX24 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions)
Preliminary Information Logic Module Propagation Delays1 Parameter Description Combinatorial Functions tPDD tRD1 tRD2 tRD3 tRD4 tRD5 tSUENA tHENA tWCLKA tWASYN Internal Array Module Delay Internal Decode Module Delay
Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
1.55 1.64
1.75 1.86
2.06 2.19
2.88 3.07
Predicted Routing Delays
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.25 1.52 1.79 2.06 3.14
1.41 1.72 2.02 2.33 3.55
1.66 2.02 2.38 2.74 4.18
2.32 2.83 3.33 3.84 5.85
Sequential Timing Characteristics
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Setup Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset Output Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.45 0.00 3.70 3.85 0.35 0.00
1.36 1.32 0.40 0.00 1.36 0.51 0.00 4.19 5.49
1.54 1.50 0.47 0.00 1.54 0.60 0.00 4.93 6.46
1.81 1.76 0.66 0.00 1.81 0.84 0.00 6.90 9.04
2.53 2.46
2.53
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Setup hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
1-143
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Input Module Propagation Delays Parameter Description tINPY tINGO tINH tINSU tILA Input Data Input Latch Gate-to-Output Input Latch Hold Input Latch Setup Latch Active Pulse Width 0.00 0.53 5.20 `-2' Speed Min. Max. 1.16 1.43 0.00 0.60 5.89 `-1' Speed Min. Max. 1.31 1.62 0.00 0.70 6.93 `Std' Speed Min. Max. 1.54 1.91 0.00 0.98 9.70 `-F' Speed Min. Max. 2.16 2.67 Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.64 2.94 3.23 3.53 4.72 2.99 3.33 3.66 4.00 5.35 3.52 3.92 4.31 4.71 6.29 4.93 5.49 6.03 6.59 8.81
Global Clock Network Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period (1/fmax) Maximum Data-Path Frequency FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 0.53 0.53 0.00 0.00 4.88 5.40 191.25 175.00 2.40 2.63 2.40 2.63 0.60 0.60 0.60 0.60 0.00 0.00 5.53 6.12 175.95 161.00 2.87 3.64 2.36 3.08 2.72 2.98 2.72 2.98 0.68 0.68 0.70 0.70 0.00 0.00 6.50 7.20 153.00 140.00 3.25 4.12 2.67 3.50 3.20 3.50 3.20 3.50 0.80 0.80 0.98 0.98 0.00 0.00 9.10 10.08 91.80 84.00 3.82 4.85 3.14 4.12 4.48 4.90 4.48 4.90 1.12 1.12 5.35 6.79 4.40 5.77
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance.
1-144
Fami
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Output Module Timing Parameter Description Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Module Timing1 Data High Data Enable High Enable Enable High Enable High Latch Output Setup Latch Output Hold Latch Clock-Out (Pad-to-Pad) Array Latch Clock-Out (Pad-to-Pad) Capacitive Loading, High Capacitive Loading, High
Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
2.97 3.35 2.25 2.68 5.83 5.39 4.58 4.58 0.53 0.00 8.33 11.78 0.04 0.03 0.60 0.00
3.37 3.80 2.55 3.03 6.60 6.10 5.19 5.19 0.70 0.00 9.44 13.35 0.04 0.03
3.96 4.47 3.00 3.57 7.77 7.18 6.10 6.10 0.98 0.00 11.10 15.70 0.05 0.04
5.54 6.26 4.20 5.00 10.88 10.05 8.54 8.54
15.54 21.98 0.07 0.06
ns/pF ns/pF
CMOS Output Module Timing Data High Data
3.80 2.78 2.25 2.68 5.83 5.39 4.58 4.58 0.53 0.00 8.33 11.78 0.04 0.03 0.60 0.00
4.31 3.15 2.55 3.03 6.60 6.10 5.19 5.19 0.70 0.00 9.44 13.35 0.04 0.03
5.07 3.71 3.00 3.57 7.77 7.18 6.10 6.10 0.98 0.00 11.10 15.70 0.05 0.04
7.10 5.19 4.20 5.00 10.88 10.05 8.54 8.54
Enable High Enable Enable High Enable High Latch Setup Latch Hold Latch Clock-Out (Pad-to-Pad) Array Latch Clock-Out (Pad-to-Pad) Capacitive Loading, High Capacitive Loading, High
15.54 21.98 0.07 0.06
ns/pF ns/pF
Notes: Delays based loading. information found "Simultaneously Switching Output Limits Actel FPGAs" application note.
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A42MX24 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions)
Preliminary Information Logic Module Propagation Delays1 Parameter Description Combinatorial Functions tPDD tRD1 tRD2 tRD3 tRD4 tRD5 tSUENA tHENA tWCLKA tWASYN Internal Array Module Delay Internal Decode Module Delay
Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
2.16 2.30
2.45 2.61
2.88 3.07
4.04 4.29
Predicted Routing Delays
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.74 2.12 2.50 2.88 4.39
1.98 2.40 2.83 3.26 4.97
2.32 2.83 3.33 3.84 5.85
3.25 3.96 4.66 5.37 8.19
Sequential Timing Characteristics
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Setup Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset Output Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.63 0.00 5.18 6.78 0.49 0.00
1.90 1.85 0.56 0.00 1.90 0.71 0.00 5.87 7.69
2.15 2.09 0.66 0.00 2.15 0.84 0.00 6.90 9.04
2.53 2.46 0.92 0.00 2.53 1.18 0.00 9.66 12.66
3.55 3.45
3.55
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance. Postroute timing based actual routing delay measurements performed device prior shipment. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from DirectTime Analyzer utility. Setup hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
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A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Input Module Propagation Delays Parameter Description tINPY tINGO tINH tINSU tILA tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input Data Input Latch Gate-to-Output Input Latch Hold Input Latch Setup Latch Active Pulse Width
`-2' Speed Min. Max. 1.62 2.01 0.00 0.74 7.28
`-1' Speed Min. Max. 1.83 2.27 0.00 0.83 8.25
`Std' Speed Min. Max. 2.16 2.67 0.00 0.98 9.70
`-F' Speed Min. Max. 3.02 3.74 0.00 1.37 13.58 Units
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
3.70 4.12 4.53 4.95 6.60
4.19 4.66 5.13 5.60 7.49
4.93 5.49 6.03 6.59 8.81
6.90 7.68 8.45 9.23 12.33
Global Clock Network Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period (1/fmax) Maximum Data-Path Frequency FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 FO=32 FO=486 0.74 0.74 0.00 0.00 6.83 7.56 114.75 105.00 3.36 3.68 3.36 3.68 0.84 0.84 0.83 0.83 0.00 0.00 7.74 8.57 105.57 96.60 4.01 5.09 3.30 4.33 3.81 4.17 3.81 4.17 0.95 0.95 0.98 0.98 0.00 0.00 9.10 10.08 91.80 84.00 4.55 5.77 3.74 4.90 4.48 4.90 4.48 4.90 1.12 1.12 1.37 1.37 0.00 0.00 12.74 14.11 55.08 50.40 5.35 6.79 4.40 5.77 6.27 6.86 6.27 6.86 1.57 1.57 7.49 9.51 6.15 8.08
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance.
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A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Output Module Timing Parameter Description Output tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Module Timing1 Data High Data Enable High Enable Enable High Enable High Latch Output Setup Latch Output Hold Latch Clock-Out (Pad-to-Pad) Array Latch Clock-Out (Pad-to-Pad) Capacitive Loading, High Capacitive Loading, High
Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
4.16 4.69 3.15 3.75 8.16 7.54 6.41 6.41 0.74 0.00 11.66 16.49 0.05 0.04 0.83 0.00
4.71 5.32 3.57 4.25 9.25 8.54 7.26 7.26 0.98 0.00 13.21 18.68 0.06 0.05
5.54 6.26 4.20 5.00 10.88 10.05 8.54 8.54 1.37 0.00 15.54 21.98 0.07 0.06
7.76 8.76 5.88 7.00 15.23 14.07 11.96 11.96
21.76 30.77 0.10 0.08
ns/pF ns/pF
CMOS Output Module Timing Data High Data
5.32 3.90 3.15 3.75 8.16 7.54 6.41 6.41 0.74 0.00 11.66 16.49 0.05 0.04 0.83 0.00
6.03 4.41 3.57 4.25 9.25 8.54 7.26 7.26 0.98 0.00 13.21 18.68 0.06 0.05
7.10 5.19 4.20 5.00 10.88 10.05 8.54 8.54 1.37 0.00 15.54 21.98 0.07 0.06
9.94 7.27 5.88 7.00 15.23 14.07 11.96 11.96
Enable High Enable Enable High Enable High Latch Setup Latch Hold Latch Clock-Out (Pad-to-Pad) Array Latch Clock-Out (Pad-to-Pad) Capacitive Loading, High Capacitive Loading, High
21.76 30.77 0.10 0.08
ns/pF ns/pF
Notes: Delays based loading. information found "Simultaneously Switching Output Limits Actel FPGAs" application note.
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A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions)
Preliminary Information Logic Module Propagation Delays Parameter Description Combinatorial Functions tPDD tRD1 tRD2 tRD3 tRD4 tRD5 tRDD tSUENA tHENA tWCLKA tWASYN Internal Array Module Delay Internal Decode Module Delay Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Predicted Module Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay
Sequential Timing Characteristics Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Setup Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset Output Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
1-149
A42MX36 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Logic Module Timing Parameter Description Synchronous SRAM Operations tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Read Cycle Time Write Cycle Time Clock High/Low Time Data Valid After Clock High/Low Address/Data Setup Time Address/Data Hold Time Read Enable Setup Read Enable Hold Write Enable Setup Write Enable Hold Block Enable Setup Block Enable Hold 10.0 10.0 14.0 14.0 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Asynchronous SRAM Operations Asynchronous Access Time Read Address Valid Address/Data Setup Time Address/Data Hold Time Read Enable Setup Address Valid Read Enable Hold Write Enable Setup Write Enable Hold Data Hold Time 11.1 10.2 13.0 12.0 18.2 16.8
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A42MX36 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Advanced Information Input Module Propagation Delays Parameter Description tINPY tINGO tINH tINSU tILA tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fHMAX Input Data Input Latch Input Latch Input Latch Gate-to-Output1 Hold1 Setup1 Pulse Width1 `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Latch Active
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 12.3
Global Clock Network Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period (1/fmax) Maximum Data-Path Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 12.2 13.4 11.5 10.7 12.5 16.1 11.5 15.0
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance.
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A42MX36 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions)
Advanced Information Output Module Timing Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data High Data Enable High Enable Enable High Enable High Latch Output Setup Latch Output Hold Latch Clock-Out (Pad-to-Pad) Array Latch Clock-Out (Pad-to-Pad) Capacitive Loading, High Capacitive Loading, High
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
13.9 10.5 11.6 16.4
11.1 15.7 11.1 11.1 11.1 11.9 13.2 18.5
13.1 18.5 13.0 13.0 13.0 14.0 15.5 21.8
12.2 11.3
18.3 25.9 10.5 11.3 18.2 18.2 18.2 19.6
ns/pF ns/pF
CMOS Output Module Timing Data High Data
Enable High Enable Enable High Enable High Latch Setup Latch Hold Latch Clock-Out (Pad-to-Pad) Array Latch Clock-Out (Pad-to-Pad) Capacitive Loading, High Capacitive Loading, High
21.7 30.5
ns/pF ns/pF
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance. information found "Simultaneously Switching Output Limits Actel FPGAs" application note.
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A42MX36 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions)
Preliminary Information Logic Module Propagation Delays Parameter Description Combinatorial Functions tPDD tRD1 tRD2 tRD3 tRD4 tRD5 tRDD tSUENA tHENA tWCLKA tWASYN Internal Array Module Delay Internal Decode Module Delay Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Predicted Module Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay
Sequential Timing Characteristics Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Setup Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset Output Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 12.7
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A42MX36 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Logic Module Timing Parameter Description Synchronous SRAM Operations tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Read Cycle Time Write Cycle Time Clock High/Low Time Data Valid After Clock High/Low Address/Data Setup Time Address/Data Hold Time Read Enable Setup Read Enable Hold Write Enable Setup Write Enable Hold Block Enable Setup Block Enable Hold 12.0 10.5 10.5 11.9 11.9 14.0 14.0 19.6 19.6 Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Asynchronous SRAM Operations Asynchronous Access Time Read Address Valid Address/Data Setup Time Address/Data Hold Time Read Enable Setup Address Valid Read Enable Hold Write Enable Setup Write Enable Hold Data Hold Time 13.7 12.6 15.5 14.3 18.2 16.8 25.5 23.5
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A42MX36 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Input Module Propagation Delays Parameter Description tINPY tINGO tINH tINSU tILA tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fHMAX Input Data Input Latch Input Latch Input Latch Gate-to-Output1 Hold1 Setup1 Pulse Width1 `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. 13.6 `-F' Speed Min. Max. Units
Latch Active
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 10.5 12.3 10.4 12.0 17.2
Global Clock Network Input High Input High Minimum Pulse Width High Minimum Pulse Width Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period (1/fmax) Maximum Data-Path Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 10.1 10.4 11.4 12.1 11.2 12.2 13.4 10.6 13.7 12.7 17.1 18.8 12.5 16.1 11.5 15.0 17.4 22.5 16.1 21.0
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance.
1-155
A42MX36 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions)
Preliminary Information Output Module Timing Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data High Data Enable High Enable Enable High Enable High Latch Output Setup Latch Output Hold Latch Clock-Out (Pad-to-Pad) Array Latch Clock-Out (Pad-to-Pad) Capacitive Loading, High Capacitive Loading, High
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
13.8 19.4 13.7 13.7 13.7 14.7 16.3 22.9
10.4 15.6 22.0 15.5 15.5 15.5 16.7 18.4 25.9
12.2 11.3 18.3 25.9 10.5 11.3 18.2 18.2 18.2 19.6 21.7 30.5
17.1 15.8 13.4 13.4
25.7 36.3 11.4 13.9 14.7 15.9 25.5 25.5 25.5 27.4
ns/pF ns/pF
CMOS Output Module Timing Data High Data
Enable High Enable Enable High Enable High Latch Setup Latch Hold Latch Clock-Out (Pad-to-Pad) Array Latch Clock-Out (Pad-to-Pad) Capacitive Loading, High Capacitive Loading, High
30.4 42.7
ns/pF ns/pF
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Postroute timing analysis simulation required determine actual worst-case performance. information found "Simultaneously Switching Output Limits Actel FPGAs" application note.
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Package Assignments
44-Pin PLCC 68-Pin PLCC
44-Pin PLCC
68-Pin PLCC
Signal
A40MX02 Function CLK, MODE SDI, DCLK, PRA, PRB,
A40MX04 Function CLK, MODE SDI, DCLK, PRA, PRB,
Signal
A40MX02 Function CLK, MODE SDI, DCLK, PRA, PRB,
A40MX04 Functions CLK, MODE SDI, DCLK, PRA, PRB,
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Package Assignments (continued)
84-Pin PLCC
A40MX04 84-Pin PLCC
Signal
A40MX04 Function CLK, MODE SDI, DCLK, PRA, PRB,
Notes: Denotes Connection. unlisted numbers user I/Os. MODE should terminated through resistor enable Actionprobe usage; otherwise terminated directly GND.
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Package Assignments (continued)
100-Pin PQFP
100-Pin PQFP
A40MX02 Function PRB,
A40MX04 Function PRB,
A40MX02 Function CLK, MODE SDI, DCLK, PRA,
A40MX04 Function CLK, MODE SDI, DCLK, PRA,
Notes: Denotes Connection. unlisted numbers user I/Os. MODE should terminated through resistor enable Actionprobe usage; otherwise terminated directly GND.
1-159
Package Assignments (continued)
80-Pin VQFP
80-Pin VQFP
A40MX02 Function
A40MX04 Function
A40MX02 Function CLK, MODE SDI, DCLK, PRA, PRB,
A40MX04 Function CLK, MODE SDI, DCLK, PRA, PRB,
Notes: Denotes Connection. unlisted numbers user I/Os. MODE should terminated through resistor enable Actionprobe usage; otherwise terminated directly GND.
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Package Assignments (continued)
84-Pin PLCC Package (Top View)
84-Pin PLCC
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84-Pin PLCC Package
Number
A42MX09 Function CLKB,I/O PRB,I/O DCLK,I/O MODE VCCI VCCA VCCA VCCA VCCI SDI,I/O PRA,I/O CLKA,I/O VCCA
A42MX16 Function CLKB,I/O PRB,I/O DCLK,I/O MODE VCCI VCCA VCCA VCCA VCCI SDI,I/O PRA,I/O CLKA,I/O VCCA
A42MX24 Function CLKB,I/O PRB,I/O (WD) (WD) (WD) DCLK,I/O MODE VCCI VCCA TMS, TDI, (WD) (WD) (WD) VCCA (WD) (WD) (WD) (WD) (WD) (WD) (WD) TCK, VCCA VCCI SDI,I/O (WD) (WD) (WD) PRA,I/O CLKA,I/O VCCA
Notes: (WD): Denotes with associated wide-decode module. Wide-decode (WD) also general-purpose user I/O. Denotes Connection. unlisted numbers user I/Os. MODE should terminated through resistor enable Actionprobe usage; otherwise terminated directly GND.
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1-163
Package Assignments (continued)
100-pin PQFP Package (Top View)
100-Pin PQFP
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100-pin PQFP Package
Number
A42MX09 PQ100 Function DCLK, MODE VCCA VCCA
A42MX16 PQ100 Function DCLK, MODE VCCA VCCA
Number
A42MX09 PQ100 Function VCCA VCCI VCCA SDI, PRA, CLKA, VCCA CLKB, PRB,
A42MX16 PQ100 Function VCCA VCCI VCCA SDI, PRA, CLKA, VCCA CLKB, PRB,
Notes: Denotes Connection. unlisted numbers user I/Os. MODE should terminated through resistor enable Actionprobe usage; otherwise terminated directly GND.
1-165
Package Assignments (continued)
160-pin PQFP Package (Top View)
160-Pin PQFP
Notes: (WD): Denotes with associated wide-decode module. Wide-decode (WD) also general-purpose user I/O. Denotes Connection. unlisted numbers user I/Os. MODE should terminated through resistor enable Actionprobe usage; otherwise terminated directly GND.
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160-Pin PQFP Package
Number
A42MX16 Function DCLK,I/O VCCI PRB,I/O CLKB,I/O VCCA CLKA,I/O PRA,I/O VCCI SDI,I/O VCCA VCCA VCCI VCCA
A42MX24 Function DCLK,I/O (WD) (WD) VCCI (WD) (WD) PRB,I/O CLKB,I/O VCCA CLKA,I/O PRA,I/O (WD) (WD) (WD) (WD) VCCI (WD) (WD) SDI,I/O VCCA VCCA VCCI VCCA TCK,
Number
A42MX16 Function VCCI VCCA VCCI VCCA VCCA VCCI VCCA MODE
A42MX24 Function TDO, (WD) (WD) VCCI (WD) (WD) VCCA (WD) (WD) (WD) (WD) VCCI (WD) (WD) TDI, TMS, VCCA VCCA VCCI VCCA MODE
1-167
Package Assignments (continued)
208-Pin PQFP Package, 208-pin RQFP Package (Top View)
208-Pin PQFP 208-Pin RQFP
Notes: (WD): Denotes with associated wide-decode module. Wide-decode (WD) also general-purpose user I/O. Denotes Connection. unlisted numbers user I/Os. MODE should terminated through resistor enable Actionprobe usage; otherwise terminated directly GND. RQFP exposed circular metal heat sink surface.
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208-Pin PQFP Package, 208-pin RQFP Package
A42MX16 Number Function MODE VCCA VCCI VCCA VCCA VCCI VCCA VCCI A42MX24 Function VCCA MODE VCCA VCCI VCCA VCCA TMS, TDI, (WD) (WD) VCCI (WD) (WD) (WD) (WD) VCCA VCCI (WD) (WD) (WD) (WD) VCCI (WD) (WD) TDO, A42MX36 PQ208 Function VCCA MODE VCCA VCCI VCCA VCCA TMS, TDI, (WD) (WD) VCCI QCLKA, (WD) (WD) (WD) (WD) VCCA VCCI (WD) (WD) QCLKB, (WD) (WD) VCCI (WD) (WD) TDO, 42MX36 RQ208 Function DCLK, (WD) (WD) QCLKC, (WD) (WD) (WD) (WD) PRB, CLKB, VCCA CLKA, PRA, (WD) (WD) QCLKD, (WD) (WD) VCCI (WD) (WD) SDI, VCCA VCCA VCCI VCCA TCK, VCCA A42MX16 Number Function VCCA VCCI VCCA VCCA SDI,I/O VCCI PRA,I/O CLKA,I/O VCCA CLKB,I/O PRB,I/O VCCI DCLK,I/O A42MX24 Function TCK, VCCA VCCI VCCA VCCA SDI,I/O (WD) (WD) VCCI (WD) (WD) (WD) (WD) PRA,I/O CLKA,I/O VCCI VCCA CLKB,I/O PRB,I/O (WD) (WD) (WD) (WD) VCCI (WD) (WD) DCLK,I/O A42MX36 PQ208 Function TCK, VCCA VCCI VCCA VCCA SDI,I/O (WD) (WD) VCCI (WD) (WD) QCLKD, (WD) (WD) PRA,I/O CLKA,I/O VCCI VCCA CLKB,I/O PRB,I/O (WD) (WD) (WD) (WD) QCLKC, VCCI (WD) (WD) DCLK,I/O 42MX36 RQ208 Function TDO, (WD) (WD) (WD) (WD) QCLKB, (WD) (WD) VCCA (WD) (WD) (WD) (WD) QCLKA, VCCI (WD) (WD) TDI, TMS, VCCA VCCA VCCA VCCI MODE VCCA
1-169
Package Assignments (continued)
240-Pin RQFP Package (Top View)
Exposed Heat Sink
240-Pin RQFP
Notes: (WD): Denotes with associated wide-decode module. Wide-decode (WD) also general-purpose user I/O. Denotes Connection. unlisted numbers user I/Os. MODE should terminated through resistor enable Actionprobe usage; otherwise terminated directly GND. RQFP exposed circular metal heat sink surface.
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240-Pin RQFP Package
Number
A42MX36 Function DCLK, (WD) (WD) VCCI QCLKC, (WD) (WD) (WD) (WD) PRB, CLKB, VCCA VCCI CLKA, PRA, (WD) (WD) QCLKD, (WD) (WD) VCCI (WD) (WD) SDI, VCCA VCCI VCCA VCCA VCCI VCCA TCK, VCCI VCCA
Number
A42MX36 Function TDO, (WD) (WD) VCCI (WD) (WD) QCLKB, (WD) (WD) VCCI VCCA (WD) (WD) (WD) (WD) QCLKA, VCCI (WD) (WD) TDI, TMS, VCCI VCCA VCCA VCCI VCCA VCCI MODE VCCA
1-171
Package Assignments (continued)
176-Pin TQFP Package (Top View)
176-Pin TQFP
Notes: (WD): Denotes with associated wide-decode module. Wide-decode (WD) also general-purpose user I/O. Denotes Connection. unlisted numbers user I/Os. MODE should terminated through resistor enable Actionprobe usage; otherwise terminated directly GND.
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Fami
176-pin TQFP Package
Number A42MX09 Function MODE VCCA VCCA VCCA A42MX16 Function MODE VCCA VCCI VCCA VCCA VCCI VCCA VCCI A42MX24 Function MODE VCCA VCCI VCCA VCCA TMS, TDI, (WD) (WD) VCCI (WD) (WD) (WD) (WD) VCCA (WD) (WD) (WD) (WD) VCCI (WD) (WD) TDO, Number A42MX09 Function VCCI VCCA SDI,I/O PRA,I/O CLKA,I/O VCCA CLKB,I/O PRB,I/O DCLK,I/O A42MX16 Function VCCI VCCA SDI,I/O VCCI PRA,I/O CLKA,I/O VCCA CLKB,I/O PRB,I/O VCCI DCLK,I/O A42MX24 Function TCK, VCCI VCCA SDI,I/O (WD) (WD) VCCI (WD) (WD) (WD) (WD) PRA,I/O CLKA,I/O VCCA CLKB,I/O PRB,I/O (WD) (WD) (WD) (WD) VCCI (WD) (WD) DCLK,I/O
1-173
1-174
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