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APEX
Programmable Logic Device Family
2001, ver.
Features.
Preliminary Information
Programmable logic device (PLD) manufactured using 0.15-µm alllayer copper-metal fabrication process eight layers metal) 1-gigabit second (Gbps) True-LVDSTM, LVPECL, pseudo current mode logic (PCML), HyperTransport interface Clock-data synchronization (CDS) True-LVDS interface correct fixed clock-to-data skew Enables common networking communications standards such RapidIO, CSIX, Utopia POS-PHY Level Support high-speed external memory interfaces, including zero turnaround (ZBT), quad data rate (QDR), double data rate (DDR) static (SRAM), single data rate (SDR) synchronous dynamic (SDRAM) faster design performance than APEX20KE devices average Enhanced 4,096-bit embedded system blocks (ESBs) implementing first-in first-out (FIFO) buffers, Dual-Port+ (bidirectional dual-port RAM), content-addressable memory (CAM) High-performance, low-power copper interconnect Fast parallel byte-wide synchronous device configuration Look-up table (LUT) logic available register-intensive functions High-density architecture 1,900,000 7,000,000 maximum system gates (see Table 89,280 logic elements (LEs) 1,523,712 bits that used without reducing available logic Low-power operation design 1.5-V supply voltage Copper interconnect reduces power consumption MultiVoltI/O support 1.5-V, 1.8-V, 2.5-V, 3.3-V interfaces ESBs offer programmable power-saving mode
Altera Corporation
A-DS-APEXII-1.1
APEX Programmable Logic Device Family
Preliminary Information
Table APEX Device Features Feature
Maximum gates Typical gates ESBs Maximum bits True-LVDS channels Flexible-LVDS
EP2A15
1,900,000 600,000 16,640 425,984
EP2A25
2,750,000 900,000 24,320 622,592
EP2A40
3,000,000 1,500,000 38,400 655,360
EP2A70
5,250,000 3,000,000 67,200 1,146,880 1,060
EP2A90
7,000,000 4,000,000 89,280 1,523,712 1,140
channels
True-LVDS PLLs General-purpose outputs Maximum user pins Notes:
Each device input channels output channels. EP2A15 EP2A25 devices have input output channels; EP2A40, EP2A70, EP2A90 devices have input output channels. PLL: phase-locked loop. True-LVDS PLLs dedicated implement True-LVDS functionality. internal outputs available. Additionally, device external output pair (two external outputs device).
.and More Features
features Gbps capability 1-Gbps True-LVDS, LVPECL, PCML, HyperTransport support input output channels that feature clock synchronization circuitry independent clock multiplication serialization/deserialization factors Common networking communications standards such RapidIO, CSIX, Utopia POS-PHY Level enabled 624-megabits second (Mbps) Flexible-LVDS HyperTransport support input output channels (input channels also support LVPECL) Support high-speed external memories, including ZBT, QDR, SRAM, SDRAM Compliant with peripheral component interconnect Special Interest Group (PCI SIG) Local Specification, Revision 3.3-V operation bits Compliant with 133-MHz PCI-X specifications Support other advanced standards, including AGP, CTT, SSTL-3 SSTL-2 Class GTL+, HSTL Class dedicated registers each element (IOE): input registers, output registers, output-enable registers Programmable hold feature
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Programmable pull-up resistor pins available during user mode Programmable output drive 3.3-V LVTTL standard levels Programmable output slew-rate control reduces switching noise Hot-socketing operation supported Pull-up resistor pins before during configuration Enhanced internal memory structure High-density 4,096-bit ESBs Dual-Port+ with bidirectional read write ports Support many other memory functions, including CAM, FIFO, packing mode partitions into 2,048-bit blocks Device configuration Fast byte-wide synchronous configuration minimizes in-circuit reconfiguration time Device configuration supports multiple voltages (either Flexible clock management circuitry with eight general-purpose outputs Four general-purpose PLLs with outputs Built-in low-skew clock tree Eight global clock signals ClockLockfeature reducing clock delay skew ClockBoostfeature providing clock multiplication 160) division 256) ClockShiftfeature providing programmable clock phase delay shifting with coarse (90°, 180°, 270°) fine (0.5 resolution Advanced interconnect structure All-layer copper interconnect high performance Four-level hierarchical FastTrack® interconnect structure fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such fast adders, counters, comparators (automatically used software tools megafunctions) Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used software tools megafunctions) Interleaved local interconnect allowing drive other through fast local interconnect
Altera Corporation
APEX Programmable Logic Device Family Data Sheet
Preliminary Information
Advanced software support Software design support automatic place-and-route provided Altera® QuartusII development system Windows-based PCs, SPARCstations, 9000 Series 700/800 workstations Altera MegaCore® functions Altera Megafunction Partners Program (AMPPSM) megafunctions optimized APEX architecture LogicLockincremental design intellectual property (IP) integration team-based design NativeLinkintegration with popular synthesis, simulation, timing analysis tools SignalTap® embedded logic analyzer simplifies in-system design evaluation giving access internal nodes during device operation Support popular revision-control software packages, including PVCS, RCS, SCCS
Tables show APEX ball-grid array (BGA) FineLine BGAdevice package sizes, options, counts. Table APEX Package Sizes Feature
Pitch (mm) Area (mm2) Length Width
672-Pin FineLine
1.00
724-Pin
1.27 1,225
1,020-Pin FineLine
1.00 1,089
1,508-Pin FineLine
1.00 1,600
Table APEX Package Options Count Feature
EP2A15 EP2A25 EP2A40 EP2A70 EP2A90 Notes:
Notes (1), 724-Pin
1,060 1,140
672-Pin FineLine
1,020-Pin FineLine
1,508-Pin FineLine
APEX devices support vertical migration within same package (e.g., designer migrate between EP2A15, EP2A25, EP2A40 devices 672-pin FineLine package). counts include dedicated clock fast pins.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
General Description
APEX devices integrate high-speed differential support using True-LVDS interface. dedicated serializer, deserializer, circuitry True-LVDS interface support LVDS, LVPECL, HyperTransport, PCML standards. Flexible-LVDS pins located regular user banks offer additional differential support, increasing total device bandwidth. This circuitry, together with enhanced IOEs support numerous standards, allows APEX devices meet high-speed interface requirements. APEX devices also include other high-performance features such bidirectional dual-port RAM, CAM, general-purpose PLLs, numerous global clocks.
Configuration
logic, circuitry, interconnects APEX architecture configured with CMOS SRAM elements. APEX devices reconfigurable 100% tested prior shipment. result, test vectors have generated fault coverage. Instead, designer focus simulation design verification. addition, designer does need manage inventories different ASIC designs; APEX devices configured board specific functionality required. APEX devices configured system power-up with data either stored Altera configuration device provided system controller. Altera offers in-system programmability (ISP)-capable configuration devices, which configure APEX devices serial data stream. enhanced configuration devices configure APEX device under Moreover, APEX devices contain optimized interface that permits microprocessors configure APEX devices serially parallel, synchronously asynchronously. This interface also enables microprocessors treat APEX devices memory configure device writing virtual memory location, simplifying reconfiguration. APEX devices also support byte-wide, synchronous configuration scheme speeds using EPC16 configuration devices microprocessor. This parallel configuration reduces configuration time using eight data lines send configuration data versus data line serial configuration. APEX devices support multi-voltage configuration; device configuration performed
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
After APEX device been configured, reconfigured incircuit resetting device loading data. Real-time changes made during system operation, enabling innovative reconfigurable computing applications.
Software
APEX devices supported Altera Quartus development system: single, integrated package that offers hardware description language (HDL) schematic design entry, compilation logic synthesis, full simulation worst-case timing analysis, SignalTap logic analysis, device configuration. Quartus software runs Windows-based PCs, SPARCstations, 9000 Series 700/800 workstations. Quartus software includes LogicLock incremental design feature. LogicLock feature allows designer make timing assignments, verify functionality performance, then constraints lock down placement performance specific block logic using LogicLock constraints. Constraints LogicLock function guarantee repeatable placement when implementing block logic current project exporting block another project. constraints LogicLock feature lock down logic fixed location device. LogicLock feature also lock logic down floating location, Quartus software determines best relative placement block meet design requirements. Adding additional logic project will affect performance blocks locked down with LogicLock constraints. Quartus software provides NativeLink interfaces other industrystandard UNIX workstation-based tools. example, designers open Quartus software from within third-party design tools. Quartus software also contains built-in optimized synthesis libraries; synthesis tools these libraries optimize designs APEX devices. example, Synopsys Design Compiler library, supplied with Quartus development system, includes DesignWare functions optimized APEX architecture.
Functional Description
APEX devices incorporate LUT-based logic, product-term-based logic, memory, high-speed standards into device. Signal interconnections within APEX devices well from device pins) provided FastTrack interconnect-a series fast, continuous column channels that entire length width device.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Each located each column FastTrack interconnect. Each contains bidirectional buffer registers that used registering input, output, output-enable signals. When used with dedicated clock pin, these registers provide exceptional performance interface support with external memory devices such SDRAM SRAM devices. IOEs provide variety features such 3.3-V, 64-bit, 66-MHz compliance, 3.3-V, 64-bit, 133-MHz PCI-X compliance, Joint Test Action Group (JTAG) boundary-scan test (BST) support, output drive strength control, slew-rate control, tri-state buffers, bus-hold circuitry, programmable pull-up resistors, programmable input output delays, open-drain outputs. APEX devices offer enhanced support, including support LVCMOS, LVTTL, HSTL, LVDS, LVPECL, HyperTransport, PCML, 3.3-V PCI, PCI-X, GTL+, SSTL-2, SSTL-3, CTT, 3.3-V standards. High-speed Gbps) differential transfers supported with True-LVDS circuitry LVDS, LVPECL, HyperTransport, PCML standards. optional feature corrects clock-to-data skew True-LVDS receiver channels, allowing flexible board topologies. Flexible-LVDS channels support differential transfer Mbps (DDR) LVDS HyperTransport standards. implement many types memory, including Dual-Port+ RAM, CAM, ROM, FIFO functions. Embedding memory directly into improves performance reduces area compared distributed-RAM implementations. abundance cascadable ESBs ensures that APEX device implement multiple wide memory blocks high-density designs. ESB's high speed ensures implement small memory blocks without speed penalty. abundance ESBs, conjunction with ability implement separate memory blocks, ensures that designers create many different-sized memory blocks system requires. Figure shows overview APEX device.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Device Block Diagram
Clock Management Circuitry
ClockLock
FastTrack Interconnect
Four-input data path functions. Product-term integration high-speed control logic state machines.
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
IOEs support PCI, GTL+, SSTL-3, LVDS, other standards.
Flexible integration embedded memory, including CAM, RAM, ROM, FIFO, other memory functions.
Table lists resources available APEX devices. Table APEX Device Resources Device
EP2A15 EP2A25 EP2A40 EP2A70 EP2A90
MegaLAB Rows
MegaLAB Columns
ESBs
APEX devices provide eight dedicated clock input pins four dedicated fast pins that globally drive register control inputs, including clocks. These signals ensure efficient distribution high-speed, low-skew control signals. control signals dedicated routing channels provide short delays skew. dedicated fast signals also driven internal logic, providing ideal solution clock divider internally-generated asynchronous control signal with high fan-out. dedicated clock fast pins APEX devices also feed logic. Dedicated clocks also used with APEX generalpurpose PLLs clock management.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
MegaLAB Structure
APEX devices constructed from series MegaLABstructures. Each MegaLAB structure contains logic array blocks (LABs), ESB, MegaLAB interconnect, which routes signals within MegaLAB structure. Signals routed between MegaLAB structures pins FastTrack interconnect. addition, edge LABs driven pins through local interconnect. Figure shows MegaLAB structure. Figure MegaLAB Structure
MegaLAB Interconnect
Adjacent IOEs
LE10
LE10
LE10
Local Interconnect
LABs
Logic Array Block
Each consists LEs, LEs' associated carry cascade chains, control signals, local interconnect. local interconnect transfers signals between same adjacent LABs, IOEs, ESBs. Quartus Compiler places associated logic within adjacent LABs, allowing fast local interconnect high performance. APEX devices interleaved structure, that each drive local interconnect areas. Every other drives either left right local interconnect area, alternating local interconnect drive within same adjacent LABs. This feature minimizes column interconnects, providing higher performance flexibility. Each structure drive through fast local interconnects. Figure shows APEX LAB.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Structure
Interconnect
MegaLAB Interconnect
drive local, MegaLAB, row, column interconnects.
To/From Adjacent LAB, ESB, IOEs To/From Adjacent LAB, ESB, IOEs
Local Interconnect
Column Interconnect driven local interconnect areas. These drive local interconnect areas.
Each contains dedicated logic driving control signals ESBs. control signals include clock, clock enable, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load signals. maximum control signals used time. Although synchronous load clear signals generally used when implementing counters, they also used with other functions. Each clocks clock enable signals. LAB's clock clock enable signals linked (e.g., particular using CLK1 will also CLKENA1). with same clock different clock enable signals either both clock signals placed into separate LABs. both rising falling edges clock used LAB, both LAB-wide clock signals used.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
LAB-wide control signals generated from local interconnect, global signals, dedicated clock pins. inherent skew FastTrack interconnect enables used clock distribution. Figure shows control signal generation circuit. Figure Control Signal Generation
Dedicated Clocks Fast Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect SYNCLOAD LABCLKENA2 SYNCCLR LABCLK2 LABCLKENA1 LABCLR1
LABCLK1
LABCLR2
Notes:
LABCLR1 LABCLR2 signals also control asynchronous load asynchronous preset within LAB. SYNCCLR signal generated local interconnect global signals.
Logic Element
smallest unit logic APEX architecture. Each contains four-input LUT, which function generator that quickly implement function four variables. addition, each contains programmable register carry cascade chains. Each drives local interconnect, MegaLAB interconnect, FastTrack interconnect routing structures. Figure
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Logic Element
Register Bypass
LAB-wide LAB-wide Synchronous Synchronous Load Clear Cascade-In
Carry-In
Packed Register Select Programmable Register
FastTrack Interconnect, MegaLAB Interconnect, Local Interconnect
data1 data2 data3 data4
Look-Up Table (LUT)
Carry Chain
Cascade Chain
Synchronous Load Clear Logic
CLRN FastTrack Interconnect, MegaLAB Interconnect, Local Interconnect
labclr1 labclr2 Chip-Wide Reset
Asynchronous Clear/Preset/ Load Logic
Clock Clock Enable Select labclk1 labclk2
labclkena1 labclkena2 Carry-Out Cascade-Out
Each LE's programmable register configured operation. register's clock clear control signals driven global signals, general-purpose pins, internal logic. combinatorial functions, register bypassed output drives outputs
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Each outputs that drive local, MegaLAB, FastTrack interconnect routing structure. Each output driven independently LUT's register's output. example, drive output while register drives other output. This feature, called register packing, improves device utilization because register used unrelated functions. also drive registered unregistered versions output. APEX architecture provides types dedicated high-speed data paths that connect adjacent without using local interconnect paths: carry chains cascade chains. carry chain supports high-speed arithmetic functions such counters adders, while cascade chain implements wide-input functions such equality comparators with minimum delay. Carry cascade chains connect through LABs same MegaLAB structure.
Carry Chain
carry chain provides fast carry-forward function between LEs. carry-in signal from lower-order drives forward into higherorder carry chain, feeds into both next portion carry chain. This feature allows APEX architecture implement high-speed counters, adders, comparators arbitrary width. Quartus Compiler create carry chain logic automatically during design process, designer create manually during design entry. Parameterized functions such DesignWare functions from Synopsys library parameterized modules (LPM) functions automatically take advantage carry chains appropriate functions. Quartus Compiler creates carry chains longer than linking LABs together automatically. enhanced fitting, long carry chain skips alternate LABs MegaLAB structure. carry chain longer than skips either from even-numbered next evennumbered LAB, from odd-numbered next oddnumbered LAB. example, last first upper-left MegaLAB structure carries first third MegaLAB structure. Figure shows n-bit full adder implemented with carry chain. portion generates bits using input signals carry-in signal; routed output register bypassed simple adders used accumulator functions. Another portion carry chain logic generates carry-out signal, which routed directly carry-in signal next-higher-order bit. final carry-out signal routed where driven onto local, MegaLAB, FastTrack interconnect routing structures.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Carry Chain
Carry-In
Register
Carry Chain
Register
Carry Chain
Register
Carry Chain
Register
Carry-Out
Carry Chain
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Cascade Chain
With cascade chain, APEX architecture implement functions with very wide fan-in. Adjacent LUTs compute portions function parallel; cascade chain serially connects intermediate values. cascade chain logical logical (via DeMorgan's inversion) connect outputs adjacent LEs. Each additional provides four more inputs effective width function, with short cascade delay. Quartus Compiler create cascade chain logic automatically during design process, designer create manually during design entry. Cascade chains longer than implemented automatically linking LABs together. enhanced fitting, long cascade chain skips alternate LABs MegaLAB structure. cascade chain longer than skips either from even-numbered next even-numbered LAB, from odd-numbered next odd-numbered LAB. example, last first upper-left MegaLAB structure carries first third MegaLAB structure. Figure shows cascade function connect adjacent form functions with wide fan-in. Figure APEX Cascade Chain
Cascade Chain Cascade Chain
d[3.0]
d[3.0]
d[7.4]
d[7.4]
d[(4n 1).(4n
d[(4n 1).(4n
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Operating Modes
APEX operate following three modes:
Normal mode Arithmetic mode Counter mode
Each mode uses resources differently. each mode, seven available inputs LE-the four data inputs from local interconnect, feedback from programmable register, carry-in cascade-in from previous LE-are directed different destinations implement desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load, clock enable control register. These LAB-wide signals available modes. Quartus software, conjunction with parameterized functions such DesignWare functions, automatically chooses appropriate mode common functions such counters, adders, multipliers. required, designer also create special-purpose functions that specify which operating mode optimal performance. Figure shows operating modes.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Figure APEX Operating Modes
Normal Mode
Carry-In data1 data2 data3 data4 4-Input
LAB-Wide Clock Enable Cascade-In LE-Out
LE-Out
CLRN
Cascade-Out
Arithmetic Mode
Carry-In Cascade-In
LAB-Wide Clock Enable LE-Out
data1 data2
3-Input 3-Input Carry-Out
LE-Out
CLRN
Cascade-Out
Counter Mode
Carry-In
Cascade-In
LAB-Wide Synchronous Load
LAB-Wide Synchronous Clear LAB-Wide Clock Enable LE-Out
data1 data2 data3 3-Input Carry-Out Cascade-Out
3-Input
LE-Out
CLRN
Notes:
normal mode support register packing. There LAB-wide clock enables LAB. When using carry-in normal mode, packed register feature unavailable. register feedback multiplexer available each LAB. DATA1 DATA2 input signals supply counter enable, down control, register feedback signals other than second LAB. LAB-wide synchronous clear LAB-wide synchronous load affect registers LAB.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Normal Mode normal mode suitable general logic applications, combinatorial functions, wide decoding functions that take advantage cascade chain. normal mode, four data inputs from local interconnect carry-in inputs four-input LUT. Quartus Compiler automatically selects carry-in DATA3 signal inputs LUT. output combined with cascade-in signal form cascade chain through cascade-out signal. normal mode support packed registers. Arithmetic Mode arithmetic mode ideal implementing adders, accumulators, comparators. arithmetic mode uses 3-input LUTs. computes three-input function; other generates carry output. shown Figure first uses carry-in signal data inputs from local interconnect generate combinatorial registered output. example, when implementing adder, this output three signals: DATA1, DATA2, carry-in. second uses same three signals generate carry-out signal, thereby creating carry chain. arithmetic mode also supports simultaneous cascade chain. arithmetic mode drive registered unregistered versions output. Quartus software implements parameterized functions that arithmetic mode automatically where appropriate; designer does need specify carry chain will used. Counter Mode counter mode offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load options. counter enable synchronous up/down control signals generated from data inputs local interconnect. synchronous clear synchronous load options LAB-wide signals that affect registers LAB. Consequently, counter mode, other that must used part same counter used combinatorial function. Quartus software automatically places registers that used counter into other LABs.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
counter mode uses three-input LUTs: generates counter data, other generates fast carry bit. 2-to-1 multiplexer provides synchronous loading, another gate provides synchronous clearing. cascade function used counter mode, synchronous clear load overrides signal carried cascade chain. synchronous clear overrides synchronous load. arithmetic mode drive registered unregistered versions output.
Clear Preset Logic Control
Logic register's clear preset signals controlled LAB-wide signals. directly supports asynchronous clear function. Quartus Compiler NOT-gate push-back technique emulate asynchronous preset. Moreover, Quartus Compiler programmable NOT-gate push-back technique emulate simultaneous preset clear asynchronous load. However, this technique uses three additional register. emulation performed automatically when design compiled. Registers that emulate simultaneous preset load will enter unknown state upon power-up when chipwide reset asserted. addition clear preset modes, APEX devices provide chip-wide reset (DEV_CLRn) that resets registers device. this controlled through option Quartus software that before compilation. chip-wide reset overrides other control signals. Registers using asynchronous preset preset when chipwide reset asserted; this effect results from inversion technique used implement asynchronous preset.
FastTrack Interconnect
APEX architecture, connections between LEs, ESBs, pins provided FastTrack interconnect. FastTrack interconnect series continuous horizontal vertical routing channels that traverse device. This global routing structure provides predictable performance, even complex designs. contrast, segmented routing FPGAs requires switch matrices connect variable number routing paths, increasing delays between logic resources reducing performance.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
FastTrack interconnect consists column interconnect channels that span entire device. interconnect routes signals throughout MegaLAB structures; column interconnect routes signals throughout column MegaLAB structures. When using column interconnect, IOE, drive other IOE, device. Figure Figure APEX Interconnect Structure
Interconnect
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
Column Interconnect
MegaLAB
MegaLAB
MegaLAB
MegaLAB
line driven directly LEs, IOEs, ESBs that row. Further, column line drive line, allowing IOE, drive elements different column interconnect. interconnect drives MegaLAB interconnect drive LEs, IOEs, ESBs particular MegaLAB structure.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
column line directly driven LEs, IOEs, ESBs that column. IOEs drive column line device's left right edge. column line used route signals from another. column line drive line; also drive MegaLAB interconnect directly, allowing faster connections between rows. Figure shows FastTrack interconnect uses local interconnect drive within MegaLAB structures. Figure FastTrack Connection Local Interconnect
MegaLAB MegaLAB Column
Column Interconnect Drives MegaLAB Interconnect
MegaLAB Interconnect
MegaLAB Interconnect Drives Local Interconnect
Column
Figure shows intersection column interconnect these forms interconnects drive each other.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure Driving FastTrack Interconnect
Interconnect MegaLAB Interconnect
Column Interconnect
Local Interconnect
APEX devices feature FastRowlines quickly routing input signals with high fan-out. Column pins drive FastRow interconnect, which routes signals directly into local interconnect without having drive through MegaLAB interconnect. FastRow lines traverse MegaLAB structures. FastRow interconnect drives four MegaLABs four MegaLABs bottom device. FastRow interconnect drives local interconnects appropriate MegaLABs. Column pins using FastRow interconnect achieve faster set-up time, because signal does need MegaLab interconnect line reach destination Figure shows FastRow interconnect.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Figure APEX FastRow Interconnect
FastRow Interconnect
FastRow Interconnect Drives Local Interconnect MegaLAB Structures
Select Vertical Pins Drive Local Interconnect FastRow Interconnect
Local Interconnect
MegaLAB
LABs
MegaLAB
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table summarizes elements APEX architecture drive each other. Table APEX Routing Scheme Source
Column Column Local interconnect MegaLAB interconnect FastTrack interconnect Column FastTrack interconnect FastRow interconnect
Destination
Local MegaLAB Interconnect Interconnect Column FastRow FastTrack FastTrack Interconnect Interconnect Interconnect
Product-Term Logic
product-term portion MultiCore architecture implemented with ESB. configured block macrocells ESB-by-ESB basis. inputs from adjacent local interconnect feed each ESB; therefore, either MegaLAB adjacent drive ESB. Also, nine macrocells feed back into through local interconnect higher performance. Dedicated clock pins, global signals, additional inputs from local interconnect drive control signals. product-term mode, each contains macrocells. Each macrocell consists product terms programmable register. Figure shows product-term mode.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Figure Product-Term Logic
Dedicated Clocks Global Signals
MegaLAB Interconnect
Macrocell Inputs CLK[1.0] ENA[1.0] CLRN[1.0] Column Interconnect
From Adjacent
Local Interconnect
Macrocells
APEX macrocells configured individually either sequential combinatorial logic operation. macrocell consists three functional blocks: logic array, product-term select matrix, programmable register. Combinatorial logic implemented product terms. productterm select matrix allocates these product terms either primary logic inputs gates) implement combinatorial functions, parallel expanders used increase logic available another macrocell. product term inverted; Quartus software uses this feature perform DeMorgan's inversion more efficient implementation wide functions. Quartus Compiler NOT-gate push-back technique emulate asynchronous preset. Figure shows APEX macrocell.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Macrocell
ESB-Wide ESB-Wide ESB-Wide Clears Clock Enables Clocks Parallel Logic Expanders (From Other Macrocells)
Programmable Register
ProductTerm Select Matrix
Clock/ Enable Select
Output
CLRN
Signals from Local Interconnect Clear Select
registered functions, each macrocell register programmed individually implement operation with programmable clock control. register bypassed combinatorial operation. During design entry, designer specifies desired register type; Quartus software then selects most efficient register operation each registered function optimize resource utilization. Quartus software other synthesis tools also select most efficient register operation automatically when synthesizing designs. Each programmable register clocked ESB-wide clocks. ESB-wide clocks generated from device dedicated clock pins, global signals, local interconnect. Each clock also associated clock enable, generated from local interconnect. clock clock enable signals related particular ESB; macrocell using clock also uses associated clock enable. both rising falling edges clock used ESB, both ESB-wide clock signals used.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
programmable register also supports asynchronous clear function. Within ESB, asynchronous clears generated from global signals local interconnect. Each macrocell either choose between asynchronous clear signals choose cleared. Either clear signals inverted within ESB. Figure shows control logic when implementing product-terms. Figure Product-Term Mode Control Logic
Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect
CLK2
CLKENA2
CLK1
CLKENA1 CLR2
CLR1
Parallel Expanders
Parallel expanders unused product terms that allocated neighboring macrocell implement fast, complex logic functions. Parallel expanders allow product terms feed macrocell logic directly, with product terms provided macrocell parallel expanders provided neighboring macrocells ESB. Quartus Compiler allocate sets parallel expanders macrocells automatically. Each parallel expanders incurs small, incremental timing delay. Figure shows APEX parallel expanders.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Parallel Expanders
From Previous Macrocell
ProductTerm Select Matrix
Macrocell ProductTerm Logic Parallel Expander Switch
ProductTerm Select Matrix
Macrocell ProductTerm Logic Parallel Expander Switch
Signals from Local Interconnect
Next Macrocell
Embedded System Block
implement various types memory blocks, including DualPort+ (bidirectional dual-port RAM), dual- single-port RAM, ROM, FIFO, blocks. includes input output registers; input registers synchronize writes, output registers pipeline designs improve system performance. offers bidirectional, dual-port mode, which supports combination port operations: reads, writes, read write different clock frequencies. Figure shows block diagram.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Figure Bidirectional Dual-Port Memory Configuration
dataA[ addressA[ wrenA clockA clockenA aclrA dataB[ addressB[ wrenB clockB clockenB aclrB
addition bidirectional dual-port memory, also supports dual-port, single-port RAM. Dual-port memory supports simultaneous read write. Single-port memory supports independent read write. Figure shows these different memory port configurations ESB. Figure Dual- Single-Port Memory Configurations
Dual-Port Memory
data[ wraddress[ wren inclock inclocken inaclr rdaddress[ rden outclock outclocken outaclr
Single-Port Memory
data[ address[ wren inclock inclocken inaclr
outclock outclocken outaclr
Note:
single-port memory blocks implemented single ESB.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
also enables variable width data ports reading writing ports dual-port configuration. example, written mode port while being read mode from port Table lists supported variable width configurations dual-port mode. Table Variable Width Configurations Dual-Port Read Port Width
bits, bits, bits, bits
Write Port Width
bits, bits, bits, bits
ESBs implement synchronous RAM, which easier than asynchronous RAM. circuit using asynchronous must generate write enable (WE) signal while ensuring that data address signals meet setup hold time specifications relative signal. contrast, ESB's synchronous generates signal self-timed with respect global clock. Circuits using ESB's selftimed only need meet setup hold time specifications global clock. inputs driven adjacent local interconnect, which turn driven MegaLAB FastTrack interconnects. Because driven local interconnect, adjacent drive directly fast memory access. outputs drive MegaLAB FastTrack interconnects local interconnect fast connection adjacent fast feedback product-term logic. When implementing memory, each configured following sizes: 1,024 2,048 4,096 dual-port single-port modes, configured addition list above. also split half used independent 2,048-bit single-port blocks. independent blocks must have identical configurations with maximum width example, half used single-port memory while other half also used single-port memory. This effectively doubles number blocks APEX device implement given number ESBs. Quartus software automatically merges logical memory functions design into ESB; designer does need merge functions manually.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
combining multiple ESBs, Quartus software implements larger memory blocks automatically. example, blocks combined form block, blocks combined form block. Memory performance does degrade memory blocks 4,096 words deep. Each implement 4,096-word-deep memory; ESBs used parallel, eliminating need external control logic that would increase delays. create high-speed memory block more than 4,096-words deep, Quartus software automatically combines ESBs with control logic.
Input/Output Clock Mode
implements input/output clock mode both dual-port bidirectional dual-port memory. using input/output clock mode clocks. each ports, clock controls registers inputs into ESB: data input, WREN, read address, write address. other clock controls data output registers. Each port, also supports independent read clock enable, write clock enable, asynchronous clear signals. Input/output clock mode commonly used applications where reads writes occur same system frequency, require different clock enable signals input output registers. Figure shows input/output clock mode.
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Data
Notes:
Data
Eight Dedicated Clocks
Four Dedicated Inputs Global Signals
Figure Input/Output Clock Mode
dataA[
RAM/ROM 1,024 2,048 4,096
dataB[
addressA[
Address
Address
APEX Programmable Logic Device Family
Note
wraddressB[
wrenA
wrenB
outclkenA Data Out[]
Write/Read Enable Data Out[]
Write/Read Enable
outclkenB
inclkenA Write Pulse Generator
inclkenB Write Pulse Generator inclock
inclock
outclock
qA[]
qB[]
outclock
Preliminary Information
registers cleared asynchronously local interconnect signals, global signals, chip-wide reset. This configuration supported bidirectional dual-port configuration.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
addition input/output mode clocking scheme, clock connections various input/output registers customizable MegaWizard® Plug-In Manager.
Single-Port Mode
APEX also supports single-port mode, which used when simultaneous reads writes required. Figure single support single-port mode RAMs. Figure Single-Port Mode
Dedicated Fast Global Signals Dedicated Clocks RAM/ROM 1,024 Data 2,048 4,096 Data Address address[
Note
data[
FastTrack Interconnect
wren
outclken
Write Enable
inclken inclock
Write Pulse Generator
outclock
Note:
registers asynchronously cleared local interconnect signals, global signals, chip-wide reset.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Content-Addressable Memory
APEX devices implement ESBs. thought inverse RAM. stores data specific location; when system submits address, block provides data. Conversely, when system submits data CAM, block provides address where data found. example, data FA12 stored address outputs when FA12 driven into used high-speed search operations. When searching data within block, search performed serially. Thus, finding particular data word take many cycles. searches addresses parallel outputs address storing particular word. When match found, match flag high. ideally suited applications such Ethernet address lookup, data compression, pattern recognition, cache tags, fast routing table lookup, high-bandwidth address filtering. Figure shows block diagram. Figure Block Diagram
data[ wraddress[ wren inclock inclocken inaclr data_address[ match outclock outclocken outaclr
APEX on-chip provides faster system performance than traditional discrete CAM. Integrating logic into APEX device eliminates off-chip on-chip delays, improving system performance. When mode, each port implements 32-word, 32-bit CAM. Wider deeper CAM, such 32-word, 64-bit 128-word, 32-bit block, implemented combining multiple blocks with some ancillary logic implemented LEs. Quartus software automatically combines ESBs create larger blocks. supports writing "don't care" bits into words memory. don't-care used mask comparisons; don't-care effect matches.
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Preliminary Information
APEX Programmable Logic Device Family
generate outputs three different modes: single-match mode, multiple-match mode, fast multiple-match mode. each mode, outputs matched data's location encoded unencoded address. When encoded, outputs encoded address data's location. instance, data located address output When unencoded, each port uses outputs show location data over clock cycles. this case, data located address 12th output line goes high. Figures show encoded outputs unencoded outputs, respectively. Figure Encoded Address Outputs
addr[15.0] data[31.0] Data Address match Encoded Output
Figure Unencoded Address Outputs
data[30.0] Data select Address
Unencoded outputs. goes high signify match.
Notes:
unencoded output, only supports input data bits. input used select line choose banks outputs. select input then outputs words between through select input outputs even words between through
single-match mode, takes clock cycles write into CAM, only clock cycle read from CAM. this mode, both encoded unencoded outputs available without external logic. Single-match mode better suited designs without duplicate data memory.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
same data written into multiple locations memory, block used multiple-match fast multiple-match modes. outputs matched data's locations encoded unencoded address. multiple-match mode, takes clock cycles write into block. reading, there outputs from each each clock cycle. Therefore, takes clock cycles represent words from single port. this mode, encoded unencoded outputs available. implement encoded version, Quartus software adds priority encoder with LEs. Fast multiple-match identical multiple match mode, however, only takes clock cycle read from block generate valid outputs. this, entire used represent outputs. fast multiple-match mode, implement maximum block size words. block pre-loaded with data during configuration, written during system operation. most cases, clock cycles required write each word into CAM. When don't-care bits used, third clock cycle required.
more information CAM, Application Note (Implementing High-Speed Search Applications with APEX CAM).
Driving Signals
ESBs provide flexible options driving control signals. Different clocks used inputs outputs. Registers inserted independently data input, data output, read address, write address, signals. global signals local interconnect drive signals. global signals, dedicated clock pins, local interconnects drive clock signals. Because drive local interconnect, control signals clock, clock enable, synchronous clear signals. Figure shows control signal generation logic.
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Preliminary Information
APEX Programmable Logic Device Family
Figure Control Signal Generation
Dedicated Clocks Fast Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect RDEN
INCLKENA
OUTCLKENA
WREN INCLOCK
OUTCLOCK
INCLR OUTCLR
local interconnect, which driven adjacent (for high-speed connection ESB) MegaLAB interconnect. drive local, MegaLAB, FastTrack interconnect routing structure drive IOEs same MegaLAB structure anywhere device.
Implementing Logic
addition implementing logic with product terms, implement logic functions when programmed with read-only pattern during configuration, creating large LUT. With LUTs, combinatorial functions implemented looking results, rather than computing them. This implementation combinatorial functions faster than using algorithms implemented general logic, performance advantage that further enhanced fast access times ESBs. large capacity ESBs enables designers implement complex functions logic level without routing delays associated with linked distributed blocks. Parameterized functions such functions take advantage automatically. Further, Quartus software implement portions design with ESBs where appropriate.
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APEX Programmable Logic Device Family
Preliminary Information
Programmable Speed/Power Control
APEX ESBs offer high-speed mode that supports fast operation ESB-by-ESB basis. When high speed required, this feature turned reduce ESB's power dissipation 50%. ESBs that power incur nominal timing delay adder. This Turbo Bitoption available ESBs that implement product-term logic memory functions. that used will powered down that does consume current. Designers program each APEX device either highspeed low-power operation. result, speed-critical paths design high speed, while remaining paths operate reduced power.
Structure
APEX devices contains bidirectional buffer, registers, latch complete embedded bidirectional single data rate IOE. Figure shows structure APEX IOE. contains input registers (plus latch), output registers, output enable registers. Both input registers latch used capturing input. Both output registers used drive outputs. output enable (OE) register used fast clock-tooutput enable timing. negative edge-clocked register used SDRAM interfacing. Quartus software automatically duplicates single register that controls multiple output bidirectional pins.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Figure APEX Structure
Logic Array Register
Register
Output Register Output
Output Register Output Input Register
Input Input
Input Register
Input Latch
IOEs located around periphery APEX device. Each drives row, column, MegaLAB, local interconnect when used input bidirectional pin. drive local, MegaLAB, row, column interconnect; column drive FastTrack column interconnect. Figure shows connects interconnect.
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APEX Programmable Logic Device Family
Preliminary Information
Figure Connection Interconnect
Interconnect MegaLAB Interconnect
drive through row, column, MegaLAB interconnect.
Each drive local, MegaLAB, row, column interconnect. Each data signal driven local interconnect.
drive through local interconnect faster clock-to-output times.
Figure shows column connects interconnect.
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Preliminary Information
APEX Programmable Logic Device Family
Figure Column Connection Interconnect
Each drive column FastRow interconnects. Each data signal driven local interconnect.
drive through local interconnect faster clock-to-output times.
drive column through row, column, MegaLAB interconnect.
Column Interconnect
Interconnect
MegaLAB Interconnect
FastRow interconnects connect column directly local interconnect within MegaLAB structures. This feature provides fast setup times pins that drive high fan-outs with complex logic, such designs. fast bidirectional timing, registers using local routing improve setup times timing. APEX devices have peripheral control made signals that drive control signals. peripheral composed output enables, OE[5:0] clock enables, CE[5:0]. These twelve signals driven from internal logic from Fast signals. Table lists peripheral control signal destinations.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table Peripheral Control Destinations Peripheral
Output Enable [OE0] Output Enable [OE1] Output Enable [OE2] Output Enable [OE3] Output Enable [OE4] Output Enable [OE5] Clock Enable [CE0] Clock Enable [CE1] Clock Enable [CE2] Clock Enable [CE3] Clock Enable [CE4] Clock Enable [CE5]
Control Signal
normal bidirectional operation, input register used input data requiring fast setup times. input register have clock input clock enable separate from output registers. output register used data requiring fast clock-to-output performance. register used fast clock-to-output enable timing. output register share same clock source same clock enable source from local interconnect associated LAB, fast global signals, global signals. Figure shows bidirectional configuration.
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Preliminary Information
APEX Programmable Logic Device Family
Figure APEX Bidirectional Configuration
Column, Local Interconnect Eight Dedicated Clocks
Peripheral Signals
Register Output Delay VCCIO
Output Clock Enable Delay
CLRN/PRN
Register Delay
Optional Clamp
VCCIO
Programmable Pull-Up
Chip-Wide Reset Output Register Drive Strength Control Open-Drain Output Slew Control Output Delay
Logic Array Output Register Delay
CLRN/PRN
Input Logic Array Delay Input Input Register Delay
Bus-Hold Circuit
Input Register
Input Clock Enable Delay
CLRN/PRN
APEX includes programmable delays that activated ensure zero hold times, minimum clock-to-output times, input register-to-logic array register transfers, logic array-to-output register transfers.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
path which directly drives register require delay ensure zero hold time, whereas path which drives register through combinatorial logic require delay. Programmable delays exist decreasing input logic array input register delays. Quartus Compiler program these delays automatically minimize setup time while providing zero hold time. Delays also programmable increasing register delays output and/or output enable registers. programmable delay exists increasing delay output pin, which required interfaces. Table shows programmable delays APEX devices. Table APEX Programmable Delay Chain Programmable Delays
Input logic array delay Input input register delay Output propagation delay Output enable register delay Output delay Output clock enable delay Input clock enable delay Logic array output register delay Note:
This delay four settings: three levels delay.
Quartus Logic Option
Decrease input delay internal cells Decrease input delay input register Increase delay output Increase delay output enable Increase delay output Increase output clock enable delay Increase input clock enable delay Decrease input delay output register
registers APEX devices share same source clear preset. designer program preset clear each individual IOE. registers programmed power high after configuration complete. programmed power low, asynchronous clear control registers. programmed power high, asynchronous preset control registers. This feature prevents inadvertent activation another device's active-low input upon power-up. register uses preset clear signal then registers must that preset clear signal.
Double Data Rate
APEX devices have six-register IOEs which support interfacing clocking data both positive negative clock edges. IOEs APEX devices support inputs, outputs, bidirectional modes.
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Preliminary Information
APEX Programmable Logic Device Family
When using inputs, input registers used clock double rate input data alternating edges. input latch also used within input acquisition. latch holds data that present during clock high times. This allows both bits data synchronous same clock edge (either rising falling). Figure shows configured input. Figure APEX Input Configuration
Column, Local Interconnect Eight Dedicated Clocks VCCIO
Optional Clamp
VCCIO
Peripheral Signals
Programmable Pull-Up
Input Input Register Delay
Input Register
CLRN/PRN Input Clock Enable Delay
Bus-Hold Circuit
Chip-Wide Reset
Input Register
Latch
CLRN/PRN
CLRN/PRN
When using outputs, output registers configured clock data paths from rising clock edges. These register outputs multiplexed clock drive output rate. output register clocks first clock high time, while other output register clocks second clock time. Figure shows configured output.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Output Configuration
Column, Local Interconnect Eight Dedicated Clocks
Peripheral Signals
Register Output Delay
VCCIO
Output Clock Enable Delay
CLRN/PRN Register Delay
Optional Clamp
VCCIO
Programmable Pull-Up
Chip-Wide Reset
Register
CLRN/PRN
Used SDRAM
Logic Array Output Register Delay
Output Register Output Propagation Delay
CLRN/PRN
Logic Array Output Register Delay
Output Register
Drive Strength Control Open-Drain Output Slew Control
CLRN/PRN
Bus-Hold Circuit
APEX operates bidirectional mode combining input output configurations. APEX pins transfer data bidirectional support SDRAM (334 Mbps). negative-edge-clocked register used hold signal inactive until falling edge clock. This done meet SDRAM timing requirements. SRAMs also supported with pins separate read write ports.
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Preliminary Information
APEX Programmable Logic Device Family
Zero Turnaround SRAM Interface Support
addition SDRAM support, APEX device pins also support interfacing with SRAM devices MHz. SRAM blocks designed eliminate dead cycles when turning bidirectional around between reads writes, writes reads. allows 100% utilization because SRAM read written every clock cycle. avoid contention, output clock-to-low-impedance time (tZX) delay ensures that greater than clock-to-high-impedance time (tXZ). Phase delay control clocks OE/output input registers using general-purpose PLLs enable APEX device meet times.
Programmable Drive Strength
output buffer each APEX device programmable drive strength control certain standards. LVTTL standard several levels drive strength that user control. SSTL-3 class SSTL-2 class HSTL class 3.3-V GTL+ support minimum setting. minimum setting lowest drive strength that guarantees IOH/IOL standard. Using minimum settings provides signal slew rate control reduce system noise signal overshoot. Table shows possible settings standards with drive strength control.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table Programmable Drive Strength Standard
LVTTL (3.3
IOH/IOL Current Strength Setting
PCI-X
LVTTL (2.5 LVTTL (1.8 LVTTL (1.5 SSTL-3 class SSTL-2 class HSTL class GTL+ (3.3
Minimum
Open-Drain Output
APEX devices provide optional open-drain (equivalent opencollector) output each pin. This open-drain output enables device provide system-level control signals (e.g., interrupt writeenable signals) that asserted several devices.
Slew-Rate Control
output buffer each APEX device programmable output slew rate control that configured low-noise highspeed performance. faster slew rate provides high-speed transitions high-performance systems. However, these fast transitions introduce noise transients into system. slow slew rate reduces system noise, adds nominal delay rising falling edges. Each individual slew rate control, allowing designer specify slew rate pin-by-pin basis. slew rate control affects both rising falling edges.
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APEX Programmable Logic Device Family
Hold
Each APEX device provides optional bus-hold feature. When this feature enabled pin, bus-hold circuitry weakly holds signal last driven state. holding last driven state until next input signal present, bus-hold feature eliminates need external pull-up pull-down resistors hold signal level when tri-stated. bus-hold circuitry also pulls undriven pins away from input threshold voltage where noise cause unintended high-frequency switching. This feature selected individually each pin. bus-hold output will drive higher than VCCIO prevent overdriving signals. bus-hold feature enabled, programmable pull-up option cannot used. bus-hold feature should also disabled open-drain outputs used with GTL+ standard. bus-hold circuitry weakly pulls signal level last driven state through resistor with nominal resistance (RBH) approximately Table page gives specific sustaining current that will driven through this resistor overdrive current that will identify next driven input level. This information provided each VCCIO voltage level. bus-hold circuitry active only after configuration. When going into user mode, bus-hold circuit captures value present configuration.
Programmable Pull-Up Resistor
Each APEX device provides optional programmable pull-up resistor during user mode. When this feature enabled pin, pull-up resistor (typically weakly holds output VCCIO level bank that output resides
Dedicated Fast Pins
APEX devices incorporate dedicated bidirectional pins signals with high internal fanout, such control signals. These pins called dedicated fast pins (FAST1, FAST2, FAST3, FAST4) drive four global fast lines throughout device, ideal fast clock, clock enable, preset, clear, high fanout logic signal distribution. dedicated fast pins have output register register, they have input registers. dedicated fast lines also driven local interconnect generate internal global signals.
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APEX Programmable Logic Device Family
Preliminary Information
Advanced Standard Support
APEX device IOEs support following standards:
LVTTL LVCMOS 1.5-V 1.8-V 2.5-V 3.3-V 3.3-V PCI-X 3.3-V LVDS LVPECL PCML HyperTransport GTL+ HSTL class SSTL-3 class SSTL-2 class Differential HSTL
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Preliminary Information
APEX Programmable Logic Device Family
Table describes standards supported APEX devices. Table APEX Supported Standards Standard Type Input Reference Voltage (VREF)
0.75 1.25 1.32
Output Supply Voltage (VCCIO)
Board Termination Voltage (VTT)
0.75 1.25
LVTTL LVCMOS 3.3-V 3.3-V PCI-X LVDS LVPECL PCML HyperTransport Differential HSTL GTL+ HSTL class SSTL-2 class SSTL-3 class Note:
Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Differential Differential Differential Differential Differential Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced
Differential HSTL only supported eight dedicated global clock pins four dedicated high-speed clock pins.
more information standards supported APEX devices, Application Note (Using Selectable Standards Altera Devices). APEX devices contain eight banks, shown Figure blocks within right banks contain circuitry support high-speed True-LVDS, LVPECL, PCML, HyperTransport inputs, another blocks within left banks support high-speed True-LVDS, LVPECL, PCML, HyperTransport outputs. other standards supported banks, including True-LVDS blocks.
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APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Banks
banks support Flexible-LVDS, HyperTransport, LVPECL inputs, regular standards.
Bank
Bank
True-LVDS, LVPECL, PCML, HyperTransport Output Block Bank Regular Pins Support 3.3-V, 2.5-V, 1.8-V, 1.5-V LVTTL 3.3-V PCI-X GTL+ SSTL-2 Class SSTL-3 Class HSTL Class
True-LVDS, LVPECL, PCML, HyperTransport Input Block Bank
Bank
Bank
True-LVDS, LVPECL, PCML, HyperTransport Output Block
Individual Power
True-LVDS, LVPECL, PCML, HyperTransport Input Block
Bank
Bank
banks support Flexible-LVDS HyperTransport outputs regular standards.
Notes:
within pads LVDS pins input only maintain acceptable noise level VCCIO plane. output placed within pads LVDS pins unless separated power ground pin. Show Pads view Quartus software's Floor Plan Editor locate these pads. Quartus software will give error message illegal output bidirectional placement next LVDS pin. True-LVDS pins Flexible-LVDS pins used high-speed differential signalling, they support standards used input, output, bidirectional pins with VCCIO
Each bank VCCIO pins. single device support 1.5-V, 1.8-V, 2.5-V, 3.3-V interfaces; each bank support different standard independently. Each bank also separate VREF level support terminated standards (such SSTL-3) independently.
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Preliminary Information
APEX Programmable Logic Device Family
Each bank support multiple standards with same VCCIO input output pins. Each bank support voltage-referenced standard, support multiple standards with same VCCIO voltage level. example, when VCCIO bank support LVTTL, LVCMOS, 3.3-V PCI, SSTL-3 inputs outputs. When True-LVDS banks used LVDS pins, they support other standards.
True-LVDS Interface
APEX devices contain dedicated circuitry supporting differential standards speeds Gbps. APEX devices have dedicated differential buffers circuitry support LVDS, LVPECL, HyperTransport, PCML standards. Four dedicated high-speed PLLs (separate from general-purpose PLLs) multiply reference clocks drive high-speed differential serializer/deserializer channels. addition, circuitry each receiver channel corrects fixed clockto-data skew. APEX devices support input channels, output channels, dedicated receiver PLLs, dedicated transmitter PLLs. True-LVDS circuitry supports following standards applications:
RapidIO POS-PHY Level Utopia HyperTransport
APEX devices support source-synchronous interfacing with LVDS, LVPECL,PCML, HyperTransport signaling Gbps. Serial channels transmitted received along with low-speed clock. receiving device then multiplies clock factor serialization/deserialization rate number from does have equal clock multiplication value. example, 840-Mbps LVDS channel received along with 84-MHz clock. 84-MHz clock multiplied drive serial shift register, register clocked parallel 10-bits wide MHz. Figures
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APEX Programmable Logic Device Family
Preliminary Information
Figure True-LVDS Receiver Diagram
Notes (1).
Bits Wide
Deserializer Data
Receiver Channel
RX_CLK1
Receiver PLL1
Receiver Channel Receiver Channel Receiver Channel
Receiver Channel
Receiver Channel Global Clock
Notes:
sets receiver channels located each APEX device. Each channels receiver PLL. does have equal When deserializer bypassed. When registers used. These clock pins drive receiver PLLs only. They drive directly logic array. However, receiver drive logic array global clock line.
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Preliminary Information
APEX Programmable Logic Device Family
Figure True-LVDS Transmitter Diagram
Notes (1),
Bits Wide
Serializer Data from
Transmitter Channel Transmitter PLL1 Transmitter Channel TXOUTCLOCK1
Global Clock from Receiver System Clock
Transmitter Channel Transmitter Channel
Transmitter Channel Transmitter Channel
Notes:
sets transmitter channels located each APEX device. Each channels transmitter PLL. does have equal When deserializer bypassed. When registers used. These clock pins drive transmitter PLLs only. They drive directly logic array. However, transmitter drive logic array global clock line.
Clock-Data Synchronization
addition dedicated serial-to-parallel converters, APEX True-LVDS circuitry contains circuitry every receiver channel. feature turned independently each receiver channel. There modes circuitry: single-bit mode, which corrects fixed clock-to-data skew ±50% data period, multi-bit mode, which corrects fixed clock-to-data skew.
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APEX Programmable Logic Device Family
Preliminary Information
Single-Bit Mode Single-bit corrects fixed clock-to-data skew ±50% data period, which allows receiver input skew margin (RSKM) increase data period. single-bit CDS, deserialization factor, must equal multiplication factor, combination allowable factors associated training patterns automatically determine byte alignment (see Table 11). Table Single-Bit Training Patterns Factor
Single-Bit Pattern
0000011111 000001111 00001111 0000111 000111 00011 0011
Multi-Bit Mode Multi-bit corrects fixed clock-to-data skew. This feature enables flexible board topologies, such topology (see Figure 34), switch topology, matrix topology. Multi-bit corrects skews inherent with these topologies, making them possible use.
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Preliminary Information
APEX Programmable Logic Device Family
Figure Multi-Bit Supports Topology
Clock
APEX Device
Data APEX Device APEX Device
Data APEX Device
Clock Clock
Clock
When using multi-bit CDS, factors need same value. byte boundary cannot distinguished with multi-bit patterns (see Table 12). Therefore, byte must aligned using internal logic. Table shows possible training patterns multi-bit CDS. Either pattern used. Table Multi-Bit Patterns Factor
Factor
Multi-Bit Pattern
J-bits 010101 pattern J-bits 101010 pattern
Pre-Programmed
When fixed clock-to-data skew known, preprogrammed into device during configuration. preprogrammed into device, training patterns need transmitted receiver channels. resolution each preprogrammed setting data period, compensate skew ±50% data period.
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APEX Programmable Logic Device Family
Preliminary Information
Flexible-LVDS Pins
subset pins banks supports interfacing with Flexible-LVDS, LVPECL, HyperTransport inputs. These Flexible-LVDS input pins include dedicated LVDS, LVPECL, HyperTransport input buffers. subset pins bottom banks supports interfacing with Flexible-LVDS HyperTransport outputs. These Flexible-LVDS output pins include dedicated LVDS HyperTransport output buffers. Flexible-LVDS pins require external components except 100- termination resistors receiver channels. These pins contain dedicated serialization/deserialization circuitry; therefore, internal logic used perform serialization/deserialization functions. EP2A15 EP2A25 devices support input output Flexible-LVDS channels. EP2A40 larger devices support input output Flexible-LVDS channels. APEX devices support Flexible-LVDS interface Mbps (DDR) channel. FlexibleLVDS pins along with True-LVDS pins provide 182-Gbps total device bandwidth.
MultiVolt Interface
APEX architecture supports MultiVolt interface feature, which allows APEX devices packages interface with systems different supply voltages. devices have pins internal operation input buffers (VCCINT), another output drivers (VCCIO). APEX VCCINT pins must always connected 1.5-V power supply. With 1.5-V VCCINT level, input pins 1.5-V, 1.8-V, 2.5-V 3.3-V tolerant. VCCIO pins connected either 1.5-V, 1.8-V, 2.5-V 3.3-V power supply, depending output requirements. output levels compatible with systems same voltage power supply (i.e., when VCCIO pins connected 1.5-V power supply, output levels compatible with 1.5-V systems). When VCCIO pins connected 3.3-V power supply, output high compatible with 3.3-V 5.0-V systems.
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Preliminary Information
APEX Programmable Logic Device Family
Table summarizes APEX MultiVolt support. Table APEX MultiVolt Support VCCIO
Notes:
clamping diode must disabled drive input with voltages higher than VCCIO. APEX devices 5.0-V tolerant with external resistor. When VCCIO APEX device drive 1.5-V, 1.8-V, 2.5-V device with 3.3-V tolerant inputs. When VCCIO APEX device drive 1.5-V 1.8-V device with 2.5-V tolerant inputs. When VCCIO APEX device drive 1.5-V device with 1.8-V tolerant inputs.
Note Output Signal
Input Signal
Open-drain output pins with pull-up resistor 5.0-V supply series register drive 5.0-V CMOS input pins that require When inactive, trace will pulled resistor. open-drain will only drive tri-state; will never drive high. rise time dependent value pull-up resistor load impedance. current specification should considered when selecting pull-up resistor.
Power Sequencing Socketing
Because APEX devices used mixed-voltage environment, they have been designed specifically possible power-up sequence. Therefore, VCCIO VCCINT power supplies powered order. Signals driven into APEX devices before during power-up without damaging device. addition, APEX devices drive during power-up. Once operating conditions reached device configured, APEX devices operate specified user.
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APEX Programmable Logic Device Family
Preliminary Information
GeneralPurpose PLLs
APEX devices have ClockLock, ClockBoost, ClockShift features, which four general-purpose PLLs (separate from four dedicated True-LVDS PLLs) provide clock management clock-frequency synthesis. These PLLs allow designers increase performance provide clock-frequency synthesis. reduces clock delay within device. This reduction minimizes clock-to-output setup times while maintaining zero hold times. PLLs, which provide programmable multiplication, allow designer distribute lowspeed clock multiply that clock on-device. APEX devices include high-speed clock tree: unlike ASICs, user does have design optimize clock tree. PLLs work conjunction with APEX device's high-speed clock provide significant improvements system performance bandwidth. PLLs APEX devices enabled through Quartus software. External devices required these features. Table shows general-purpose features APEX devices. Figure shows APEX general-purpose PLL. Table APEX General-Purpose Features Number PLLs
ClockBoost Feature
m/(n
Number External Clock Outputs
Number Feedback Inputs
Figure APEX General-Purpose
Phase Comparator
Notes
Voltage-Controlled Oscillator
inclock
Phase Shift Circuitry
clock0
clock1
extclk fbin
Note:
represents prescale divider input. represents multiplier. represent different post scale dividers possible outputs. integers that range from 160. integers that range from
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Preliminary Information
APEX Programmable Logic Device Family
Advanced ClockBoost Multiplication Division
APEX PLLs include circuitry that provides clock synthesis eight internal outputs external outputs using m/(n output divider) scaling. When locked, locked output clock aligns rising edge input clock. closed loop equation Figure gives output frequency fclock0 (m/(n k))fIN fclock1 (m/(n v))fIN. These equations allow multiplication division clocks programmable number. Quartus software automatically chooses appropriate scaling factors according frequency, multiplication, division values entered. single APEX device allows multiple user-defined multiplication division ratios that possible even with multiple delay-locked loops (DLLs). example, frequency scaling factor 3.75 needed given input clock, multiplication factor division factor entered. This advanced multiplication scaling performed with single PLL, making unnecessary cascade outputs.
External Clock Outputs
APEX devices have low-jitter external clocks available external clock sources. Other devices board these outputs clock sources. There three modes external clock outputs.
Zero Delay Buffer: external clock output phase aligned with clock input zero delay. Multiplication, programmable phase shift, time delay shift allowed this configuration. MegaWizard interface altclklock should used verify possible clock settings. External Feedback: external feedback input phase aligned with clock input pin. aligning these clocks, actively remove clock delay skew between devices. This mode same restrictions zero delay buffer mode. Normal Mode: external clock output will have phase delay relative clock input pin. internal clock used this mode, register clock will phase aligned input clock pin. Multiplication allowed with normal mode.
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APEX Programmable Logic Device Family
Preliminary Information
ClockShift Circuitry
General-purpose PLLs APEX devices have ClockShift circuitry that provides programmable phase shift. Users enter phase shift degrees time units) that affects outputs. Phase shifts 90°, 180°, 270° implemented exactly. Other values phase shifting, delay shifting time units, allowed with resolution range This resolution varies with frequency input user-entered multiplication division factors. phase shift ability only possible multiplied divided clock input output frequency have integer multiple relationship (i.e., fIN/fOUT fOUT/fIN must integer).
Clock Enable Signal
APEX PLLs have CLKLK_ENA enabling/disabling device PLLs. When CLKLK_ENA high, drives clock output ports. When CLKLK_ENA low, clock0, clock1, extclock ports driven PLLs lock. When CLKLK_ENA goes high again, relocks. individual enable port each programmable. more than instantiated, each does have clock enable. enable/disable device PLLs with CLKLK_ENA pin, inclocken port altclklock instance must connected CLKLK_ENA input pin.
Lock Signals
APEX device circuits support individual LOCK signals. LOCK signal drives high when locked onto input clock. LOCK remains high long input remains within specification. will input specification. LOCK optional each used APEX devices; when used, they pins. This signal available internally; used logic array, must back with input pin.
SignalTap Embedded Logic Analyzer
APEX devices include device enhancements support SignalTap embedded logic analyzer. including this circuitry, APEX device provides ability monitor design operation over period time through IEEE Std. 1149.1 (JTAG) circuitry; designer analyze internal logic speed without bringing internal signals pins. This feature particularly important advanced packages such FineLine packages because adding connection during debugging process difficult after board designed manufactured.
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APEX Programmable Logic Device Family
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
APEX devices provide JTAG circuitry that complies with IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing performed before after configuration, during configuration. APEX devices also JTAG port configuration with Quartus software with hardware using either JamStandard Test Programming Language (STAPL) Files (.jam) Byte-Code Files (.jbc). Finally, APEX devices JTAG port monitor logic operation device with SignalTap embedded logic analyzer. APEX devices support JTAG instructions shown Table
Table APEX JTAG Instructions JTAG Instruction Description
SAMPLE/PRELOAD Allows snapshot signals device pins captured examined during normal device operation, permits initial data pattern output device pins. Also used SignalTap embedded logic analyzer. EXTEST BYPASS Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins. Places 1-bit bypass register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation. Selects 32-bit USERCODE register places between pins, allowing USERCODE serially shifted TDO. Selects IDCODE register places between TDO, allowing IDCODE serially shifted TDO. Places 1-bit bypass register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation, while tri-stating pins. Places 1-bit bypass register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation while holding pins state defined data boundary-scan register. Used when configuring APEX device JTAG port with MasterBlasteror ByteBlasterMVdownload cable, when using File Byte-Code File embedded processor. Monitors internal device operation with SignalTap embedded logic analyzer.
USERCODE IDCODE HIGHZ
CLAMP
instructions
SignalTap instructions Note:
hold weak pull-up features override high-impedance state HIGHZ, CLAMP, EXTEST.
APEX device instruction register length bits. APEX device USERCODE register length bits. Tables show boundary-scan register length device IDCODE information APEX devices.
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APEX Programmable Logic Device Family
Preliminary Information
Table APEX JTAG Boundary-Scan Register Length Device
EP2A15 EP2A25 EP2A40 EP2A70 EP2A90
Boundary-Scan Register Length
1,470 1,884
Table 32-Bit APEX Device IDCODE Device Version Bits)
EP2A15 EP2A25 EP2A40 EP2A70 EP2A90 Notes tables:
Contact Altera Applications up-to-date information this device. most significant (MSB) left. IDCODE's least significant (LSB) always
IDCODE Bits) Part Number Bits)
1100 0100 0000 0000 1100 0110 0000 0000
Manufacturer Identity Bits)
0110 1110 0110 1110 0110 1110 0110 1110 0110 1110
Bit)
0000 0000
Figure shows timing requirements JTAG signals.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Figure APEX JTAG Waveforms
tJPZX tJSSU Signal Captured Signal Driven tJSH JPCO JPXZ JPSU
tJSZX
tJSCO
tJSXZ
Table shows JTAG timing parameters values APEX devices. Table APEX JTAG Timing Parameters Values Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output Update register high impedance valid output Update register valid output high impedance
Parameter
Unit
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
more information, following documents:
Application Note (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) Programming Test Language Specification
Generic Testing
Each APEX device functionally tested. Complete testing each configurable static random access memory (SRAM) logic functionality ensures 100% yield. test measurements APEX devices made under conditions equivalent those shown Figure Multiple test patterns used configure devices during stages production flow. test criteria include:
Power supply transients affect measurements. Simultaneous transitions multiple outputs should avoided accurate measurement. Threshold tests must performed under conditions. Large-amplitude, fast-ground-current transients normally occur device outputs discharge load capacitances. When these transients flow through parasitic inductance between device ground test system ground, significant reductions observable noise immunity result.
Figure APEX Test Conditions
Device Output Test System
Device input rise fall times
(includes capacitance)
Operating Conditions
APEX devices offered both commercial industrial grades. However, industrial-grade devices have limited speed-grade availability.
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Preliminary Information
APEX Programmable Logic Device Family
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, capacitance 1.5-V APEX devices. Table APEX Device Absolute Maximum Ratings Symbol
VCCINT VCCIO IOUT TSTG TAMB input voltage output current, Storage temperature Ambient temperature Junction temperature bias Under bias packages under bias
Notes (1), Minimum
-0.5 -0.5 -0.5
Parameter
Supply voltage
Conditions
With respect ground
Maximum
Unit
Table APEX Device Recommended Operating Conditions Symbol
VCCINT VCCIO
Parameter
Supply voltage internal logic input buffers
Conditions
Minimum
1.425 3.00 (3.135) 2.375 1.71 -0.5
Maximum
1.575 3.60 (3.465) 2.625 1.89 VCCIO
Unit
Supply voltage output buffers, (4), 3.3-V operation Supply voltage output buffers, 2.5-V operation Supply voltage output buffers, 1.8-V operation Supply voltage output buffers, 1.5-V operation
Input voltage Output voltage Operating junction temperature
(3), commercial industrial
Input rise time Input fall time
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APEX Programmable Logic Device Family
Preliminary Information
Table APEX Device Operating Conditions Symbol
ICC0
Note Minimum
Parameter
Input leakage current Tri-stated leakage current supply current (standby) (All ESBs power-down mode)
Conditions
VCCIO VCCIO ground, load, toggling inputs, speed grade ground, load, toggling inputs, speed grades
Typical
Maximum
Unit
RCONF
Value pull- VCCIO resistor before VCCIO 2.375 during VCCIO 1.71 configuration
Table LVTTL Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
-0.5
Maximum
0.45
Units
VCCIO (10) (10)
Table LVCMOS Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
-0.5
Maximum
Units
VCCIO VCCIO 3.0, -0.1 VCCIO 3.0,
VCCIO
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APEX Programmable Logic Device Family
Table 2.5-V Specifications Symbol
VCCIO
Note (10) Conditions Minimum
2.375 -0.5 VCCIO -0.1
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage
Maximum
2.625
Units
Low-level output voltage
Table 1.8-V Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
1.65 0.65 VCCIO -0.5
Maximum
1.95 0.35 VCCIO 0.45
Units
VCCIO (10)
(10) VCCIO 0.45
Table 1.5-V Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
0.65 VCCIO -0.5
Maximum
0.35 VCCIO 0.25 VCCIO
Units
VCCIO (10) (10)
0.75 VCCIO
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APEX Programmable Logic Device Family
Preliminary Information
Table 3.3-V LVDS Specifications Symbol
VCCIO
Parameter
supply voltage Differential output voltage Change between high Output offset voltage Change between high
Conditions
Minimum
3.135
Typical
Maximum
3.465
Units
1.125
1.25
1.375
Differential input threshold Receiver input voltage range Receiver differential input resistor (external APEX devices)
-100
Table PCML Specifications Symbol
VCCIO
Parameter
supply voltage Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Output termination voltage Differential output voltage Rise time 80%) Fall time 80%) Output load Receiver differential input resistor
Conditions
Minimum
3.135
Typical
Maximum
3.465 VCCIO
Units
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table LVPECL Specifications Symbol
VCCIO
Note (11) Conditions Minimum
3.135 2,100 1,450 2,275
Parameter
supply voltage Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Differential input voltage Differential output voltage Rise time 80%) Fall time 80%)
Typical
Maximum
3.465 1,700 VCCIO 1,650 2,420 2,500
Units
Table HyperTransport Specifications Symbol
VCCIO VOCM VICM
Parameter
supply voltage Differential output voltage Output common mode voltage Differential input voltage Input common mode voltage Receiver differential input resistor
Conditions
Minimum
2.375
Typical
Maximum
2.625
Units
Table 3.3-V Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
VCCIO -0.5
Typical
Maximum
VCCIO VCCIO
Units
VCCIO IOUT -500 IOUT 1,500
VCCIO
VCCIO
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APEX Programmable Logic Device Family
Preliminary Information
Table PCI-X Specifications Symbol
VCCIO VIPU LPIN
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input pull-up voltage Input leakage current High-level output voltage Low-level output voltage inductance
Conditions
Minimum
VCCIO -0.5 VCCIO
Typical
Maximum
VCCIO 0.35 VCCIO
Units
VCCIO IOUT -500 IOUT 1,500
VCCIO
VCCIO
Table GTL+ Specifications Symbol
VREF
Parameter
Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage
Conditions
Minimum
1.35 0.88 VREF
Typical
Maximum
1.65 1.12 VREF
Units
(10)
0.65
Table SSTL-2 Class Specifications Symbol
VCCIO VREF
Parameter
Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF 0.04 1.15 VREF 0.18 -0.3
Typical
VREF 1.25
Maximum
2.625 VREF 0.04 1.35 VREF 0.18
Units
-7.6 (10) (10)
0.57 0.57
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APEX Programmable Logic Device Family
Table SSTL-2 Class Specifications Symbol
VCCIO VREF
Parameter
Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.04 1.15 VREF 0.18 -0.3
Typical
VREF 1.25
Maximum
VREF 0.04 1.35 VCCIO VREF 0.18
Units
-15.2 (10) 15.2 (10)
0.76 0.76
Table SSTL-3 Class Specifications Symbol
VCCIO VREF
Parameter
Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.05 VREF -0.3
Typical
VREF
Maximum
VREF 0.05 VCCIO VREF
Units
(10) (10)
Table SSTL-3 Class Specifications Symbol
VCCIO VREF
Parameter
Output supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.05 VREF -0.3
Typical
VREF
Maximum
VREF 0.05 VCCIO VREF
Units
(10) (10)
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APEX Programmable Logic Device Family
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Table 3.3-V Specifications Symbol
VCCIO VREF
Parameter
Output supply voltage Reference voltage High-level input voltage (12) Low-level input voltage (12) High-level output voltage Low-level output voltage Input leakage current
Conditions
Minimum
3.15 0.39 VCCIO VCCIO
Typical
Maximum
3.45 0.41 VCCIO VCCIO VCCIO
Units
IOUT IOUT VCCIO
VCCIO
VCCIO
Table 3.3-V Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage (12) Low-level input voltage (12) High-level output voltage Low-level output voltage Input leakage current
Conditions
Minimum
3.15 VCCIO
Typical
Maximum
3.45 VCCIO VCCIO
Units
IOUT IOUT VCCIO
VCCIO
VCCIO
Table 1.5-V HSTL Class Specifications Symbol
VCCIO VREF (DC) (DC) (AC) (AC)
Parameter
Output supply voltage Input reference voltage Termination voltage high-level input voltage low-level input voltage high-level input voltage low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
0.68 VREF -0.3 VREF
Typical
0.75 0.75
Maximum
VREF VREF
Units
(10) (10)
VCCIO
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APEX Programmable Logic Device Family
Table 1.5-V HSTL Class Specifications Symbol
VCCIO VREF (DC) (DC) (AC) (AC)
Parameter
Output supply voltage Input reference voltage Termination voltage high-level input voltage low-level input voltage high-level input voltage low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
0.68 VREF -0.3 VREF
Typical
0.75 0.75
Maximum
VREF VREF
Units
(10) VCCIO (10)
Table 1.5-V Differential HSTL Specifications Symbol
VCCIO VDIF (DC) (DC) VDIF (AC)
Parameter
supply voltage input differential voltage common mode input voltage differential input voltage
Conditions
Minimum
0.68
Typical
Maximum
Units
Table Specifications Symbol
VCCIO VTT/VREF
Parameter
Output supply voltage Termination input reference voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage Output leakage current (when output high
Conditions
Minimum
1.35 VREF
Typical
Maximum
1.65
Units
VREF VCCIO VOUT VCCIO VREF VREF
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APEX Programmable Logic Device Family
Preliminary Information
Table Hold Parameters Parameter Conditions
sustaining current (maximum)
VCCIO Level
-200
Units
-300 -500
High sustaining current (minimum) overdrive current High overdrive current VCCIO VCCIO
Table APEX Device Capacitance Symbol
CINCLK COUT
Parameter
Input capacitance Input capacitance dedicated clock Output capacitance
Conditions
Minimum
Maximum
Unit
Notes tables:
Operating Requirements Altera Devices Data Sheet. Conditions beyond those listed Table cause permanent damage device. Additionally, device operation absolute maximum ratings extended periods time have adverse affects device. Minimum input -0.5 During transitions, inputs undershoot overshoot input currents less than periods shorter than Maximum rise time must rise monotonically. VCCIO maximum minimum conditions LVPECL, LVDS, RapidIO, PCML shown parentheses. pins, including dedicated inputs, clock, I/O, JTAG pins, driven before VCCINT VCCIO powered. Typical values VCCINT VCCIO This value specified normal device operation. value vary during power-up. pull-up resistance values will lower external source drives higher than VCCIO. (10) Drive strength programmable according values Table page (11) When APEX devices drive LVPECL signals, APEX LVPECL outputs must terminated with resistor network. (12) VREF specifies center point switching range.
Timing Model
high-performance FastTrack MegaLAB interconnect routing structures ensure predictable performance, accurate simulation timing analysis. contrast, unpredictable performance FPGAs caused their segmented connection scheme.
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Preliminary Information
APEX Programmable Logic Device Family
specifications always representative worst-case supply voltage junction temperature conditions. output-pin-timing specifications reported maximum drive strength. Figure shows fMAX timing model APEX devices. These parameters used estimate fMAX multiple levels logic. However, Quartus software timing analysis provides more accurate timing information because Quartus software usually more upto-date timing information than data sheet until timing model final. Also, Quartus software model delays caused loading distance effects more accurately than using numbers this data sheet. Figure fMAX Timing Model
Routing Delay
F1-4 F5-20 F20+
ESBARC ESBSRC ESBAWC ESBSWC ESBWASU ESBWDSU ESBSRASU ESBWESU ESBDATASU ESBWADDRSU ESBRADDRSU ESBDATACO1 ESBDATACO2 ESBDD PTERMSU PTERMCO
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APEX Programmable Logic Device Family
Preliminary Information
Figure shows timing model bi-directional, input, output timing. Figure Synchronous External TIming Model
Register
Dedicated Clock
tOUTCO
Bidirectional
CLRN Output Register
CLRN Input Register
tINSU tINH
CLRN
Notes Figure
output enable register controlled "Fast Output Enable Register option Quartus software. output register controlled "Fast Output Register option Quartus software. input register controlled "Fast Input Register option Quartus software.
Tables through show APEX ESB, routing delays minimum pulse-width timing parameters fMAX timing model. Table APEX fMAX Timing Parameters Symbol
tLUT register setup time before clock register hold time before clock register clock-to-output delay delay data-in data-out
Parameter
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Preliminary Information
APEX Programmable Logic Device Family
Table APEX fMAX Timing Parameters Symbol
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO asynchronous read cycle time synchronous read cycle time asynchronous write cycle time synchronous write cycle time write address setup time with respect write address hold time with respect data setup time with respect data hold time with respect read address setup time with respect read address hold time with respect setup time before clock when using input register data setup time before clock when using input register write address setup time before clock when using input registers read address setup time before clock when using input registers clock-to-output delay when using output registers clock-to-output delay without output registers data-in data-out delay mode macrocell input non-registered output macrocell register setup time before clock macrocell register clock-to-output delay
Parameter
Table APEX fMAX Routing Delays Symbol
tF1-4 tF5-20 tF20+
Parameter
Fan-out delay estimate using local interconnect; estimate routing delay signal with fan-out Fan-out delay estimate using MegaLab interconnect; estimate routing delay signal with fan-out Fan-out delay estimate using FastTrack interconnect; estimate routing delay signal with fan-out greater than
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APEX Programmable Logic Device Family
Preliminary Information
Table APEX Minimum Pulse Width Timing Parameters Symbol
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Parameter
Minimum clock high time from clock Minimum clock time from clock clear pulse width preset pulse width Clock high time Clock time Write pulse width Read pulse width
Table APEX External Timing Parameters Symbol
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL Note Table
Note Conditions
Parameter
Setup time with global clock input register Hold time with global clock input register
Clock-to-output delay with global clock output register Clock-to-output buffer disable delay Clock-to-output buffer enable delay Setup time with clock input register Hold time with clock input register Clock-to-output delay with clock output register Clock-to-output buffer disable delay Clock-to-output buffer enable delay Slow slew rate Slow slew rate
External timing parameters factory tested, worst-case values specified Altera. These timing parameters sample-tested only.
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Preliminary Information
APEX Programmable Logic Device Family
Tables through show APEX device fMAX functional timing parameters. Table EP2A15 fMAX Timing Parameters Symbol Speed Grade
tLUT
Note Speed Grade Speed Grade
Unit
Table EP2A15 fMAX Timing Parameters Symbol Speed Grade
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO
Note Speed Grade Speed Grade
Unit
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APEX Programmable Logic Device Family
Preliminary Information
Table EP2A15 fMAX Routing Delays Symbol Speed Grade
tF1-4 tF5-20 tF20+
Note Speed Grade Speed Grade
Unit
Table EP2A15 Minimum Pulse Width Timing Parameters Symbol Speed Grade
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Note Speed Grade
Speed Grade
Unit
Table EP2A25 fMAX Timing Parameters Symbol Speed Grade
tLUT
Note Speed Grade Speed Grade
Unit
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Preliminary Information
APEX Programmable Logic Device Family
Table EP2A25 fMAX Timing Parameters Symbol Speed Grade
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO
Note Speed Grade Speed Grade
Unit
Table EP2A25 fMAX Routing Delays Symbol Speed Grade
tF1-4 tF5-20 tF20+
Note Speed Grade Speed Grade
Unit
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table EP2A25 Minimum Pulse Width Timing Parameters Symbol Speed Grade
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Note Speed Grade
Speed Grade
Unit
Table EP2A40 fMAX Timing Parameters Symbol Speed Grade
tLUT
Note Speed Grade Speed Grade
Unit
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table EP2A40 fMAX Timing Parameters Symbol Speed Grade
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO
Note Speed Grade Speed Grade
Unit
Table EP2A40 fMAX Routing Delays Symbol Speed Grade
tF1-4 tF5-20 tF20+
Note Speed Grade Speed Grade
Unit
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table EP2A40 Minimum Pulse Width Timing Parameters Symbol Speed Grade
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Note Speed Grade
Speed Grade
Unit
Table EP2A70 fMAX Timing Parameters Symbol Speed Grade
tLUT
Note Speed Grade Speed Grade
Unit
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table EP2A70 fMAX Timing Parameters Symbol Speed Grade
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO
Note Speed Grade Speed Grade
Unit
Table EP2A70 fMAX Routing Delays Symbol Speed Grade
tF1-4 tF5-20 tF20+
Note Speed Grade Speed Grade
Unit
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table EP2A70 Minimum Pulse Width Timing Parameters Symbol Speed Grade
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Note Speed Grade
Speed Grade
Unit
Table EP2A90 fMAX Timing Parameters Symbol Speed Grade
tLUT
Note Speed Grade Speed Grade
Unit
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table EP2A90 fMAX Timing Parameters Symbol Speed Grade
tESBARC tESBSRC tESBAWC tESBSWC tESBWASU tESBWAH tESBWDSU tESBWDH tESBRASU tESBRAH tESBWESU tESBDATASU tESBWADDRSU tESBRADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO
Note Speed Grade Speed Grade
Unit
Table EP2A90 fMAX Routing Delays Symbol Speed Grade
tF1-4 tF5-20 tF20+
Note Speed Grade Speed Grade
Unit
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table EP2A90 Minimum Pulse Width Timing Parameters Symbol Speed Grade
tCLRP tPREP tESBCH tESBCL tESBWP tESBRP Notes Tables
Note Speed Grade
Speed Grade
Unit
Timing information preliminary. Final timing information will released future version this data sheet. Timing information these devices will released future version this data sheet.
Tables through show external timing parameter values APEX devices. Table EP2A15 External Timing Parameters Symbol Speed Grade
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL
Note Speed Grade Speed Grade
Unit
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table EP2A25 External Timing Parameters Symbol Speed Grade
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL
Note Speed Grade Speed Grade
Unit
Table EP2A40 External Timing Parameters Symbol Speed Grade
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL
Note Speed Grade Speed Grade
Unit
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table EP2A70 External Timing Parameters Symbol Speed Grade
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL
Note Speed Grade Speed Grade
Unit
Table EP2A90 External Timing Parameters Symbol Speed Grade
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL
Note Speed Grade Speed Grade
Unit
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table APEX Selectable Standards Input Adder Delays Symbol Speed Grade
LVCMOS LVTTL 3.3-V 3.3-V PCI-X GTL+ SSTL-3 Class SSTL-3 Class SSTL-2 Class SSTL-2 Class HSTL Class HSTL Class Differential HSTL LVDS LVPECL 3.3-V
Note Speed Grade
Speed Grade
Unit
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table APEX Selectable Standards Output Adder Delays Symbol Speed Grade
LVCMOS LVTTL 3.3-V 3.3-V PCI-X GTL+ SSTL-3 Class SSTL-3 Class SSTL-2 Class SSTL-2 Class HSTL Class HSTL Class Differential HSTL LVDS LVPECL 3.3-V Notes Tables
Note Speed Grade
Speed Grade
Unit
Timing information preliminary. Final timing information will released future version this data sheet. These timing adjustment factors will released future version this data sheet.
Power Consumption Device PinOuts
Detailed power consumption information APEX devices will released future interactive power estimator Altera site.
Altera site (http://www.altera.com) Altera Digital Library pin-out information.
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APEX Programmable Logic Device Family
Revision History
information contained APEX Programmable Logic Device Family Data Sheet version supersedes information published previous versions. following changes were made APEX Programmable Logic Device Family Data Sheet version 1.1:
Updated Table Added preliminary timing information, including Tables through
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Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Printed Recycled Paper.
Copyright 2001 Altera Corporation. rights reserved. Altera, AMPP, APEX, APEX 20K, APEX 20KE, APEX ByteBlasterMV, ClockBoost, ClockLock, ClockShift, FastRow, FastTrack, FineLine BGA, FlexibleLVDS, Jam, LogicLock, MasterBlaster, MegaCore, MegaLAB, MegaWizard, MultiVolt, NativeLink, Quartus, Quartus SignalTap, True-LVDS, Turbo Bit, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
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