SOB8UL6484-(67/84/100/125)T-S 64MByte CMOS Synchronous DRAM Modul

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

SOB8UL6484-(67/84/100/125)T-S 64MByte CMOS Synchronous DRAM Modul

Datasheet Thumbnail

Top Searches for this datasheet

December 1997 Revision
SOB8UL6484-(67/84/100/125)T-S
64MByte CMOS Synchronous DRAM Module
General Description
SOB8UL6484-(67/84/100/125)T-S high performance, 64-megabyte synchronous, dynamic module organized words bits, 144-pin, small outline dual-in-line memory module (SODIMM) package. module utilizes eight Fujitsu MB81164842A-(67/84/100/125)LFN CMOS 8Mx8 synchronous dynamic RAMs surface mount package (TSOP) epoxy laminated substrate. Each device accompanied decoupling capacitor improved noise immunity. Byte Serial EEPROM contains module configuration information.
Features
High Density Cycle Time: Power: 64MByte (125 MHz), 10ns (100 MHz), 12ns MHz), 15ns MHz) Active 5.9W (125 MHz), 5.2W (100 MHz), 4.8W MHz), 4.3W MHz)
LVTTL-compatible inputs outputs Separate power ground planes improve noise immunity Single power supply 3.3V±0.3V Height: 1.060 inch
ABSOLUTE MAXIMUM RATINGS
Item Voltage relative Power Dissipation Operating Temperature Storage Temperate Short Circuit Output Current Symbol Topr Tstg Ratings -0.5 +4.6 10.4 +125 Unit
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Supply Voltage Ground Input High voltage Input voltage -0.5 VCC+0.5 Unit
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
December 1997 Revision
SOB8UL6484-(67/84/100/125)T-S
Functional Diagram
DQMB7 DQMB6 DQMB5 DQMB4 DQMB3 DQMB2 DQMB1 DQMB0 RAS* CAS* CLK0 CS0* CKE0 CLK1
BLOCK
BLOCK
BLOCK
BLOCK
DQ0~DQ15
DQ16~DQ31
DQ32~DQ47
DQ48~DQ63
DQ0~DQ63
0.01µF
EEPROM
Decoupling capacitors devices
(All specifications device subject change without notice.) Notes: A~A11 devices. CLKs terminated using series resistors. A0~A2 serial EEPROM grounded. Each 8mx16 Block comprises 8Mx8 SDRAMs. DQMs Data I/Os DQMB0 controls DQMB1 controls DQMB2 controls DQMB3 controls DQMB4 controls DQMB5 controls DQMB6 controls DQMB7 controls DQ15 DQ16 DQ23 DQ24 DQ31 DQ32 DQ39 DQ40 DQ47 DQ48 DQ55 DQ56 DQ63
Clock Wiring CLK0,CLK1
SDRAM1 SDRAM2 SDRAM3 SDRAM4
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
December 1997 Revision
SOB8UL6484-(67/84/100/125)T-S
Name
A0~A11 A0~A8 BA0, DQ0~DQ63 CLK0, CLK1 RAS* CAS* CKE0
Addresses Column Addresses Bank Select Address Data Inputs/Outputs Clock Inputs Address Strobes Column Address Strobes Clock Enables
Designation
DQMB0-DQMB7 CS0*
Mask Enables Chip Select Write Enable Serial Clock Serial Data Input/Output Power Supply Ground Connection
Designation
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB4 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CKE0 CAS*
Designation
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 A10/AP (Note) DQMB2 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Designation
CLK1 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 (Note) (Note) DQMB6 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CLK0 RAS* CS0*
Notes: Address Initiates Auto-Precharge Address BA0,BA1 Bank select within SDRAM devices.
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
December 1997 Revision
SOB8UL6484-(67/84/100/125)T-S
SERIAL INFORMATION
Byte#
32-61
Function Described
Bytes Written into serial memory module Total bytes memory device Fundamental memory type Address this assembly Column Addresses this assembly Module Banks this assembly Data Width this assembly Data Width this assembly (continued) Voltage interface standard this assembly SDRAM cycle time CL=3 (tCLK) SDRAM Access from Clock CL=3 (tAC) DIMM configuration type Refresh Rate/Type SDRAM Width Primary DRAM SDRAM Data Width Min. clock delay, Back Back Random Column Addresses (ICCD) Burst Length Supported Banks each SDRAM device CAS# Latency Latency Write Latency SDRAM Module Attribute SDRAM Device Attribute Clock cycle Time CL=2 (tCLK) Max. Data Access Time from clock CL=2 (tAC) Clock cycle Time CL=1 (tCLK) Max. Data Access Time from clock CL=1 (tAC) Min. Precharge Time (tRP) Min. Active Delay (tRRD) Min. Delay (tRCD) Min. Pulse Width (tRAS) Module Bank Density Superset Information Revision Checksum bytes 0-62
Function Supported
bytes bytes SDRAM bits LVTTL 10ns 12ns 8.5ns 8.5ns Non-Parity S/R, Normal 15.6 1CLK
Value
7.5ns
15ns 9.0ns
Full Non-Buffered/Registered Vcc, B/R, S/W, P/A, 12ns 15ns 17ns 9.0ns 9.0ns 10ns 29ns 30ns 35ns 16ns 20ns 20ns 24ns 30ns 30ns 48ns 60ns 65ns 64MB Rev. JEDEC Calculation
20ns 10ns
40ns 20ns 30ns 70ns
JEDEC Calculation
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
December 1997 Revision
SOB8UL6484-(67/84/100/125)T-S
SERIAL INFORMATION (CONTINUED)
Function Supported Byte#
66-71 95-98 128-255
Value
None
Function Described
Manufacturers JEDEC code JEP-106E Manufacturers JEDEC code JEP-106E Manufacturers JEDEC code JEP-106E Manufacturing location Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Revision Code Revision Code Manufacturing Date Manufacturing Date Assembly Serial Number Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data INTEL specification frequency INTEL specification CAS# Latency Support Open Read Write
Continuation code SMART's None Specific Data None None None None Specific Data None DATE DATE Serial Number None None None None
Specific Data DATE DATE S.No.
INTEL specification extension: These bytes required compatibility with previously released systems.
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
December 1997 Revision
SOB8UL6484-(67/84/100/125)T-S
CHARACTERISTICS
(VCC 3.3V±0.3V,
Parameter Symbol Test Condition Min. Burst, min. min. Operating Current ICC1 Burst, min., min. Banks Active -VIL, min. Banks Idle VIH, min. Banks Idle VIL, min. Bank Active VIH, min. Bank Active min. min., min., tRRD min. Auto Refresh Vout Dout Disable High Iout -2mA Iout Max. Min. Max. Min. Max. Min. Max. Unit Note
1280
1120
1040
1440
1200
1040
Precharge Standby Current
ICC2
Active Standby Current
ICC3
Burst Mode Current
ICC4 ICC5 ICC6
Refresh Current Self Refresh Current Input Leakage Output Leakage Current Output High Voltage Output Voltage CAS* Latency Notes:
1640
1440
1320
1200
depends output load condition when device selected (max.) specified output open condition. initial pulse 200µs required after power-up followed minimum eight Auto-Refresh-Cycles.
CAPACITANCE
=+25°C, 3.3V±0.3V)
Parameter Input Capacitance (Address, WE*, RAS*, CAS*) Input Capacitance (DQMBs) Input Capacitance (CS0*, CKE0) Input Capacitance (CLK0,CLK1) Input/Output Capacitance (DQ0~DQ63) Notes: Symbol CI/O Max. Unit Note
Capacitance measured with Boonton Meter effective capacitance method. CAS* disable Dout.
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
December 1997 Revision
SOB8UL6484-(67/84/100/125)T-S
CHARACTERISTICS
+70°C, 3.3V±0.3V,
Parameter Clock Period Transition Time Clock High Time Clock Time Input Setup Time Input Hold Time Output Valid from Clock Output Low-Z Output High-Z Output Hold Time Time between Refresh Cycle Time Access Time Access Time Precharge Time Active Time Delay Time Write Recovery Time Delay Time Power-down Exit Time Clock Disable Output High-Z Input Data Delay Last Output Write Command Delay Write Command Input Data Delay Precharge Output High-Z Delay Burst Stop Command Output High-Z Delay CL=3 CL=2 CL=3 CL=2 CL=3 CL=2 CL=3 CL=2 Symbol tREF tRAC tCAC tRAS tRCD tRRD tPDE ICKE IDQZ IDQD IOWD IDWD IROH IBSH IMRD ICCD ICBD CL=3 CL=2 IRWL Unit cycle cycle cycle cycle cycle cycle
Notes
65.6 100000
65.6 100000
65.6 100000
65.6 100000
cycle cycle cycle cycle cycle
Mode Register Access Bank Active (min.) Delay Bank Delay Write Precharge Read Delay
Notes:
initial pulse least 200µs required after power-up followed minimum eight auto refresh cycles. characteristics assume 50pF capacitive load. longer than 1ms, reference level measuring time input signal (min.) (max.). 1.4V reference level measuring timing input signals. defines time which outputs achieve ±200mV. Actual clock output will clock tRAS tRP. 20ns supported SPD.
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
December 1997 Revision
SOB8UL6484-(67/84/100/125)T-S
Physical Dimensions
144-pin (72x2) DIMM
Front View
2.661 2.503 0.158x2 1.060 0.787 0.236 0.140 (max.)
0.913 1.291 0.181 0.098
070x2
0.130
0.040 ±±0.004 0.031
0.145
0.083
0.157 0.100 0.010 0.024 0.098 0.059 0.031 0.157
Back View
dimensions inches with 0.005" tolerance unless otherwise specified)
Detail
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
December 1997 Revision
SOB8UL6484-(67/84/100/125)T-S Ordering Information
(8a) (10) Memory Type SDRAM SGRAM Module Shape SIMM DIMM Small Outline DIMM Module Count 72-pin 144-pin 168-pin 200-pin Word Depth 256K 512K Buffer Type Buffered Unbuffered Operating Voltage Power Consumption 3.3V Standard Power 3.3V Power Data Width (ex. 64=x64, 72=x72 etc.) Device Configuration Refresh 2krf 4krf
(11) (12) Interface Level Blank LVTTL SSTL
(13) (14)
(10)
Module Revision Applied "Standard" Blank Rev. Rev. Rev. (etc.) When DRAM device revised, revision changed
(11) Clock Frequency 67Mhz 84Mhz 100Mhz 125Mhz (12) Package Component TSOP (13) Private Brand Name Blank Common Products Brand This column applicable custom modules, applicable JEDEC standard commodity products (14) Assembly Test Site Smart Modular Technologies
(8a)
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
December 1997 Revision
SOB8UL6484-(67/84/100/125)T-S
FUJITSU LIMITED
further information please contact:
Japan
FUJITSU LIMITED Memory Marketing Dept. 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki 211-88, Japan Tel: +81-44-754-3767 Fax: +81-44-754-3343 Internet: http://www.fujitsu.co.jp/
North South America
FUJITSU MICROELECTRONICS, INC. 3545 North First Street Jose, 95134-1804, USA. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center (Mon-Fri: 7am-5pm (PST)) Tel: +1-800-866-8608 Fax: +1-408-922-9179 Internet: http://www.fujitsumicro.com/ Rights Reserved. Circuit diagrams utilizing Fujitsu products included means illustrating typical semiconductor applications. Complete information sufficient construction purposes necessarily given. information given this document have been carefully checked believed reliable. However, Fujitsu assumes responsibility inaccuracies. information contained this document does convey licence under copyrights, patent rights trademarks claimed owned Fujitsu. Fujitsu reserves right change products specifications without notice. part this publication copied reproduced form means, transferred third party without prior written consent Fujitsu. information contained this document intended with equipments which require extremely high reliability such aerospace equipments, undersea repeaters, nuclear control systems medical equipments life support.
Europe
FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 Internet: http://www.fujitsu-ede.com/
Asia
FUJITSU MICROELECTRONICS ASIA LIMITED #05-08, Lorong Chuan NewTechPark Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 Internet: http://www.fsl.com.sg/
LIMITED 1997
MP-DRAMM-DS-20559-11/97
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH

SOB8UL6484-(67/84/100/125)T-S 64MByte CMOS Synchronous DRAM Modul

Top Searches for this datasheet

Other recent searches