POB8UV6414A-(102/103)T-S 64MByte CMOS, PC/100 Synchronous DRAM Mo
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November 1998 Revision
POB8UV6414A-(102/103)T-S
64MByte CMOS, PC/100 Synchronous DRAM Module
General Description
POB8UV6414A-(102/103)T-S high performance, 64-megabyte synchronous, dynamic module organized words bits, 144-pin, small outline dual-in-line memory module (SODIMM) package. module utilizes eight Fujitsu MB81F641642C-(102/103)FN CMOS 4Mx16 synchronous dynamic RAMs surface mount package (TSOP) epoxy laminated substrate. Each device accompanied decoupling capacitor improved noise immunity. Byte Serial EEPROM contains module configuration information.
Features
High Density Cycle Time: Power: 64MByte 10ns Active 6.9W
LVTTL-compatible inputs outputs Separate power ground planes improve noise immunity Single power supply 3.3V±0.3V Height: 1.250 inch
ABSOLUTE MAXIMUM RATINGS
Item Voltage relative Power Dissipation Operating Temperature Storage Temperate Short Circuit Output Current Symbol Topr Tstg Ratings -0.5 +4.6 +125 Unit
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Supply Voltage Ground Input High voltage Input voltage -0.5 VCC+0.5 Unit
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
November 1998 Revision
POB8UV6414A-(102/103)T-S
Funktional Diagram
DQM0 DQ(7:0) DQM1 DQ(15:8)
DQM4 DQ(39:32) DQM5 DQ(47:40)
DQM2 DQ(23:16) DQM3 DQ(31:24)
DQM6 DQ(55:48) DQM7 DQ(63:56)
SERIAL CKE1 CKE0 /RAS /CAS A(10:0) LOADS LOADS CKE: SDRAM CKE: SDRAM /RAS: SDRAM /CAS: SDRAM /WE: SDRAM A(10:0): SDRAM
SDRAM
Recommended bypass: 0.33uF 0.1uF SDRAM device
SDRAM
Note: obtain most advantageous board layout, byte lanes swapped. Bits within byte also swapped, however, bits between bytes swapped
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
November 1998 Revision
POB8UV6414A-(102/103)T-S
Name
A0~A11 A0~A7 BA0, DQ0~DQ63 CLK0, CLK1 RAS* CAS* CKE0, CKE1 Addresses Column Addresses Bank Select Address Data Inputs/Outputs Clock Inputs Address Strobes Column Address Strobes Clock Enables DQMB0-DQMB7 CS0*, CS1* Mask Enables Chip Select Write Enable Serial Clock Serial Data Input/Output Power Supply Ground Connection
Designation DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CLK0 RAS* CS0*
Designation DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB4 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CKE0 CAS* CKE1
Designation DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 A10/AP (Note) DQMB2 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Designation CLK1 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 (Note) (Note) DQMB6 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Notes Address Initiates Auto-Precharge Address BA0,BA1 Bank select within SDRAM devices.
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
November 1998 Revision
POB8UV6414A-(102/103)T-S
SERIAL INFORMATION
Byte#
36-61
Function Described
Bytes Written into serial memory module Total bytes memory device Fundamental memory type Address this assembly Column Addresses this assembly Module Banks this assembly Data Width this assembly Data Width this assembly (continued) Voltage interface standard this assembly SDRAM cycle time CL=3 (tCLK) SDRAM Access from Clock CL=3 (tAC) DIMM configuration type Refresh Rate/Type SDRAM Width Primary DRAM SDRAM Data Width Min. clock delay, Back Back Random Column Addresses (ICCD) Burst Length Supported Banks each SDRAM device CAS# Latency Latency Write Latency SDRAM Module Attribute SDRAM Device Attribute Clock cycle Time CL=2 (tCLK) Max. Data Access Time from clock CL=2 (tAC) Clock cycle Time CL=1 (tCLK) Max. Data Access Time from clock CL=1 (tAC) Min. Precharge Time (tRP) Min. Active Delay (tRRD) Min. Delay (tRCD) Min. Pulse Width (tRAS) Module Bank Density Address Command Input Setup Time (tSI) Address Command Input Hold Time (tHI) Data Input Setup Time (tSI) Data Input Hold Time (tHI) Superset Information Revision Checksum bytes 0-62
Function Supported -102 -103
bytes bytes SDRAM bits LVTTL 10ns Non-Parity S/R, Normal 15.6 1CLK Full Non-Buffered/Registered Vcc, B/R, S/W, P/A, 10ns 15ns 6.0ns 8.0ns 20ns 20ns 20ns 50ns 32MB Rev. JEDEC Calculation
Value -102 -103
JEDEC Calculation
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
November 1998 Revision
POB8UV6414A-(102/103)T-S
SERIAL INFORMATION (CONTINUED)
Function Supported Byte#
66-71 95-98 128-255
Value -102
Function Described
Manufacturers JEDEC code JEP-106E Manufacturers JEDEC code JEP-106E Manufacturers JEDEC code JEP-106E Manufacturing location Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Manufacturer's Part Number Revision Code Revision Code Manufacturing Date Manufacturing Date Assembly Serial Number Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Manufacturer Specific Data Intel Spec. Frequency Intel Spec. Detail 100Mhz Open Read Write
-102
-103
-103
Continuation code None Specific Data None None Specific Data None DATE DATE Serial Number None None None 100Mhz 1100-1111 None
Specific Data DATE DATE S.No.
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
November 1998 Revision
POB8UV6414A-(102/103)T-S
CHARACTERISTICS
recommended operating conditions unless otherwise noted) Notes
Value Parameter Output High Voltage Output Voltage Input Leakage Current (Any Input) Symbol VOH(DC) VOL(DC) -2mA VCC; other pins under test Dout Disable Burst: Length=4, BL=4, min. bank- active, Outputs open, Addresses changed 3-times during (min), Burst: Length=4 (each bank), BL=4 (each bank), min. banks active, Output open, Addresses changed 3-times during (min), CKE=VIL, banks idle, tCK=min, Power down mode, CKE=VIL, banks idle, CLK=H Power down mode, CKE=VIH, banks idle, tCK=min, commands only, Input signals (except CMD) changed time during clock cycles, CKE=VIH, banks idle, CLK=H Input signals stable, Conditions Min. Max. Unit
Output Leakage Current
ICC1S
Operating Current (Average Power Supply Current)
ICC1D
ICC2P Precharge Standby Current (Power Supply Current) ICC2PS
Precharge Standby Current (Power Supply Current)
ICC2N
Precharge Standby Current (Power Supply Current)
ICC2NS
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
November 1998 Revision
POB8UV6414A-(102/103)T-S
(Continued)
Value Parameter Symbol Test Condition Min. CKE=VIL, bank active, tCK=min, CKE=VIL, bank active, CKE=VIH, bank active, tCK=min, commands only, Input signals (except CMD) changed time during clock cycles, CKE=VIH, bank active, tCK=min, Burst length=4, Outputs open, Multiple-banks active, Gapless data, Auto-refresh; tCK=min, tRC=min, Self-refresh; tCK=min, 0.2V, Max. Unit
ICC3P
ICC3PS
Active Standby Current (Power Supply Current)
ICC3N
ICC3NS
Burst mode Current (Average Power supply current)
ICC4
Refresh Current (Average Power Supply Current)
ICC5
1920
Refresh Current (Average Power Supply Current)
ICC6
CAS* Latency Notes: depends output termination load conditions, clock cycle rate, signal clocking rate; specified values obtained with output open termination register. initial pause (DESL NOP) required after power-up followed minimum eight Auto-refresh cycles.
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
November 1998 Revision
POB8UV6414A-(102/103)T-S
CAPACITANCE
=+25°C, 3.3V±0.3V) Parameter Input Capacitance (Address, WE*, CKE, RAS*, CAS*) Input Capacitance (DQMBs) Input Capacitance (CLK0* CS1*) Input Capacitance (CLK0, CLK1) Input/Output Capacitance (DQ0~DQ63) Notes: Symbol CI/O Max. Unit Note
Capacitance measured with Boonton Meter effective capacitance method. CAS* disable Dout.
CHARACTERISTIC: MB81F641642C-(102/103)
recommended operating conditions unless otherwise noted) Notes 2,3,4 -102 Min. Max. 65.6 Min. -103 Max. 65.6
Parameter Latency=2 Latency=3
Symbol tCK2 tCK3 Latency=2 Latency=3 tAC2 tAC3 Latency=2 Latency=3 Latency=2 Latency=3 tHZ2 tHZ3 tREFI tCKSP
Unit
Notes
Clock Period Clock High Time Clock Time Input Setup Time Input Hold Time Access time from Clock (tCK=min) Output Low-Z Output High-Z
Output Hold Time
Time between Auto-Refresh command Interval Transition Time time Power Down Exit
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
November 1998 Revision
POB8UV6414A-(102/103)T-S
BASE VALUES CLOCK COUNT/LATENCY: MB81F641642C-(102/103)
Parameter Cycle Time Precharge Time Active Time Delay Time Write Recovery Time Data-in Precharge Lead Time Data-in Active/ Refresh command period Mode Register cycle Time Bank Active Delay Time Latency=2 Latency=3 Symbol tRAS tRCD tDPL tDAL2 tDAL3 tRSC tRRD Unit -102 Min. 1cyc+tRP 2cyc+tRP Max. 110000 Min. 1cyc+tRP 2cyc+tRP -103 Max. 110000 Notes
CLOCK COUNT FORMULA
(Note Base Value Clock Period
Clock
(Round whole number)
LATENCY-FIXED VALUES: MB81F641642C-(102/103)
(The latency values these parameters fixed regardless clock period) Parameter Clock Disable Output High-Z Input Data Delay Last Output Write Command Delay Write Command Input Data Delay Precharge Output High-Z Delay Burst Stop Command Output High-Z Delay Delay (min) Bank Delay (min)
Notes:
Symbol ICKE IDQZ IDQD IOWD IDWD IROH2 IROH3 IBSH2 IBSH3 ICCD ICBD
Unit cycle cycle cycle cycle cycle cycle
-102
-103
Notes
cycle cycle cycle
depends output termination load conditions, clock cycle rate, signal clocking rate; specified values obtained with output open termination register. initial pause (DESL NOP) required after power-up followed minimum eight Auto-refresh cycles. characteristics assume capacitive load. reference level measuring timing input signals. Transition times measured between (min) (max). Assumes tRCD satisfied. also specifies access time burst mode. Specified where output buffer longer driven. Actual clock count (IRC) will clock count tRAS (IRAS) (IRP). Operation within tRCD (min) ensures that access time determined tRCD (min) (max); tRCD greater than specified tRCD (min), access time determined tAC. base values measured from clock edge command input clock edge next command input. clock counts calculated simple formula: clock count equals base value divided clock period (round whole number).
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
November 1998 Revision
POB8UV6414A-(102/103)T-S
Fig. EXAMPLE TEST LOAD CIRCUIT
50ohm Output 1.4V
50pF
LVTTL
Note: characteristics measured this condition. This load circuits applicable VOL.
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
November 1998 Revision
POB8UV6414A-(102/103)T-S
Physical Dimensions
144-pin (72x2) DIMM
Front View
2.661 2.503 0.158
0.150 (max.)
1.250 0.787
0.236
0.913
1.291
0.130
0.181 0.098
0.040 ±0.004
0.145
0.083
0.031
0.157 0.100 0.010 0.024 0.098 0.059 Detail 0.031 0.157
Back View
(All dimensions inches with 0.005" tolerance unless otherwise specified.)
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
November 1998 Revision
POB8UV6414A-(102/103)T-S
Ordering Information
(10) (11) (12) (13) Memory Type SDRAM (PC/66) SGRAM SDRAM-Fast (PC/100) Module Shape SIMM DIMM Small Outline DIMM Module Count 72-pin 144-pin 168-pin 200-pin Word Depth 256K 512K Buffer Type Buffered Unbuffered Registered Operating Voltage Power Consumption 3.3V LVTTL Standard Power 3.3V LVTTL Power 3.3V SSTL Standard Power Data Width (ex. 64=x64, 72=x72 etc.) Device Configuration Refresh 2krf 4krf 8krf
(10)
Module Revision Applied "Standard" Blank Rev. Rev. Rev. (etc.) When DRAM device revised, revision changed
(11) Clock Frequency SDRAM (PC/66) 100Mhz SDRAM-Fast (100Mhz, PC/100) CL=2; tRCD=2; tRP=2 CL=3; tRCD=2; tRP=2 CL=3; tRCD=3; tRP=3 (12) Package Component TSOP (13) Assembly Test Site Smart Modular Technologies
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
November 1998 Revision
POB8UV6414A-(102/103)T-S
FUJITSU LIMITED
further information please contact:
Japan
FUJITSU LIMITED Memory Marketing Dept. 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki 211-88, Japan Tel: +81-44-754-3767 Fax: +81-44-754-3343 Internet: http://www.fujitsu.co.jp/
North South America
FUJITSU MICROELECTRONICS, INC. 3545 North First Street Jose, 95134-1804, USA. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center (Mon-Fri: 7am-5pm (PST)) Tel: +1-800-866-8608 Fax: +1-408-922-9179 Internet: http://www.fujitsumicro.com/ Rights Reserved. Circuit diagrams utilizing Fujitsu products included means illustrating typical semiconductor applications. Complete information sufficient construction purposes necessarily given. information given this document have been carefully checked believed reliable. However, Fujitsu assumes responsibility inaccuracies. information contained this document does convey licence under copyrights, patent rights trademarks claimed owned Fujitsu. Fujitsu reserves right change products specifications without notice. part this publication copied reproduced form means, transferred third party without prior written consent Fujitsu. information contained this document intended with equipments which require extremely high reliability such aerospace equipments, undersea repeaters, nuclear control systems medical equipments life support.
Europe
FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 Internet: http://www.fujitsu-ede.com/
Asia
FUJITSU MICROELECTRONICS ASIA LIMITED #05-08, Lorong Chuan NewTechPark Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 Internet: http://www.fmap.com.sg/
©FUJITSU LIMITED 1998
Printed Germany
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
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