MEMORY SYNCHRONOUS DYNAMIC MB81F641642D-75/-102/-10 CMO

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MEMORY SYNCHRONOUS DYNAMIC MB81F641642D-75/-102/-10 CMO

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AE1E
MEMORY
SYNCHRONOUS DYNAMIC
MB81F641642D-75/-102/-10
CMOS 4-Bank 1,048,576-Word Synchronous Dynamic Random Access Memory DESCRIPTION
Fujitsu MB81F641642D CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing 67,108,864 memory cells accessible 16-bit format. MB81F641642D features fully synchronous operation referenced positive edge clock whereby operations synchronized clock input which enables high performance simple user interface coexistence. MB81F641642D SDRAM designed reduce complexity using standard dynamic (DRAM) which requires many control signal timing constraints, improve data bandwidth memory much times more than standard DRAM. MB81F641642D ideally suited workstations, personal computers, laser printers, high resolution graphic adapters/accelerators other applications where extremely large memory bandwidth required where simple interface needed.
CMOS
PRODUCT LINE FEATURES
Parameter
tRCD Clock Frequency Burst Mode Cycle Time Access Time From Clock Operating Current banks active) Power Down Mode Current (ICC2P) Self Refresh Current (ICC6) MB81F641642D -102
min. max. min. max. max. max. max.
min. max. min. max. max. max. max.
min. max. min. max. max. max. max.
Single +3.3 Supply ±0.3 tolerance LVTTL compatible refresh cycles every Four bank operation Burst read/write operation burst read/single write operation capability
Standard power versions Programmable burst type, burst length, latency Auto-and Self-refresh (every 15.6 power down mode Output Enable Input Data Mask
MB81F641642D-75/-102/-10
PACKAGE
Plastic TSOP(II) Package
Marking side
(FPT-54P-M02) (Normal Bend)
Package Ordering Information
54-pin plastic (400 mil) TSOP-II, order
MB81F641642D-75/-102/-10
ASSIGNMENTS DESCRIPTIONS
54-Pin TSOP(II) (TOP VIEW) <Normal Bend: FPT-54P-M02>
VCCQ VSSQ VCCQ VSSQ DQML A10/AP DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 VCCQ N.C. DQMU N.C.
(Marking side)
Number
Symbol VCC, VCCQ DQ15 VSS, VSSQ N.C. (BA0), (BA1) DQML, DQMU Supply Voltage Data Ground Connection Write Enable
Function
Column Address Strobe Address Strobe Chip Select Bank Select (Bank Address) Auto Precharge Enable Address Input Clock Enable Clock Input Input Mask/Output Enable Row: Column:
These pins connected internally chip.
MB81F641642D-75/-102/-10
BLOCK DIAGRAM
Fig. MB81F641642D BLOCK DIAGRAM
each block
CLOCK BUFFER
BANK-3 BANK-2 BANK-1 BANK-0
CONTROL SIGNAL LATCH COMMAND DECODER
DRAM
MODE REGISTER
A11, A10/AP
CORE (4,096
ADDRESS BUFFER/ REGISTER
(BA1) (BA0)
ADDR.
DQMU
COLUMN ADDRESS COUNTER DATA BUFFER/ REGISTER
COL. ADDR.
VCCQ VSS/VSSQ
DQ15
MB81F641642D-75/-102/-10
FUNCTIONAL TRUTH TABLE Note
COMMAND TRUTH TABLE
Function Device Deselect Operation Burst Stop Read Read with Auto-precharge Write Write with Auto-precharge Bank Active (RAS) Precharge Single Bank Precharge Banks Mode Register Notes:
Note
DESL READ A13, (BA) (AP)
Notes Symbol
READA WRIT
WRITA ACTV PALL
Valid, Logic Low, Logic High, either commands assumes CSUS command previous rising edge clock. commands assumed valid state transitions. inputs latched rising edge clock. DESL commands have same effect part. READ, READA, WRIT WRITA commands should only issued after corresponding bank been activated (ACTV command). Refer STATE DIAGRAM. ACTV command should only issued after corresponding bank been precharged (PRE PALL command). Required after power command should only issued after banks have been precharged (PRE PALL command). Refer STATE DIAGRAM.
MB81F641642D-75/-102/-10
TRUTH TABLE
Function Data Write/Output Enable Lower Byte Data Write/Output Enable Upper Byte Data Mask/Output Disable Lower Byte Data Mask/Output Disable Upper Byte Command ENBL ENBL MASK MASK DQML DQMU
TRUTH TABLE
Current State Function Notes Symbol SELF SELFX Idle Power Down Entry Power Down Power Down Exit Notes: Self Refresh Self-refresh Exit A13, (AP) (BA)
Bank Active Clock Suspend Mode Entry CSUS Clock Suspend Continue (Except Idle) Clock Suspend Idle Idle Clock Suspend Mode Exit Auto-refresh Command Self-refresh Entry
CSUS command requires that least bank active. Refer STATE DIAGRAM. SELF commands should only issued after banks have been precharged (PRE PALL command). Refer STATE DIAGRAM. SELF commands should only issued after last read data have been appeared should held high within tRC.
MB81F641642D-75/-102/-10
OPERATION COMMAND TABLE (Applicable single bank)
Current State Idle Bank Active Addr MODE MODE Command DESL READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF Illegal Illegal Bank Active after tRCD Auto-refresh Self-refresh Mode Register (Idle after tRSC) Begin Read; Determine Begin Write; Determine Illegal Function Notes
Precharge; Determine Precharge Type Illegal Illegal (Continued)
MB81F641642D-75/-102/-10
Current State Read
Addr
Command DESL
Function
Notes
(Continue Burst Bank Active) (Continue Burst Bank Active) Burst Stop Bank Active Terminate Burst, Read; Determine Terminate Burst, Start Write; Determine Illegal Terminate Burst, Precharge Idle; Determine Precharge Type Illegal Illegal (Continue Burst Bank Active) (Continue Burst Bank Active) Burst Stop Bank Active Terminate Burst, Start Read; Determine Terminate Burst, Write; Determine Illegal Terminate Burst, Precharge Determine Precharge Type Illegal Illegal (Continued)
READ/READA
Write
MODE
WRIT/WRITA ACTV PRE/PALL REF/SELF DESL
READ/READA
MODE
WRIT/WRITA ACTV PRE/PALL REF/SELF
MB81F641642D-75/-102/-10
Current State Read with Autoprecharge
Addr
Command DESL
Function (Continue Burst Precharge Idle) (Continue Burst Precharge Idle) Illegal Illegal Illegal Illegal Illegal Illegal Illegal (Continue Burst Precharge Idle) (Continue Burst Precharge Idle) Illegal Illegal Illegal Illegal Illegal Illegal Illegal
Notes
Write with Autoprecharge
MODE
READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF DESL
MODE
READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF
(Continued)
MB81F641642D-75/-102/-10
Current State Precharge
Addr MODE MODE
Command DESL READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF DESL READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF
Function (Idle after tRP) (Idle after tRP) (Idle after tRP) Illegal Illegal Illegal (PALL affect other bank) Illegal Illegal (Bank Active after tRCD) (Bank Active after tRCD) (Bank Active after tRCD) Illegal Illegal Illegal Illegal Illegal Illegal
Notes
Bank Activating
(Continued)
MB81F641642D-75/-102/-10
(Continued) Current State Refreshing Addr Command DESL NOP/BST Function (Idle after tRC) (Idle after tRC) Notes
READ/READA/ Illegal WRIT/WRITA ACTV/ PRE/PALL REF/SELF/ DESL Illegal
Mode Register Setting
Illegal (Idle after tRSC) (Idle after tRSC) Illegal
READ/READA/ Illegal WRIT/WRITA ACTV/PRE/ PALL/REF/ SELF/MRS
Illegal
ABBREVIATIONS: Address Column Address Bank Address Auto Precharge
MB81F641642D-75/-102/-10
COMMAND TRUTH TABLE
Current State Selfrefresh Addr Invalid Exit Self-refresh (Self-refresh Recovery Idle after tRC) Exit Self-refresh (Self-refresh Recovery Idle after tRC) Illegal Illegal Illegal (Maintain Self-refresh) Invalid Idle after Idle after Illegal Illegal Illegal Illegal Illegal (Continued) Function Notes
Selfrefresh Recovery
MB81F641642D-75/-102/-10
Current State Power Down
Addr MODE MODE MODE MODE Invalid
Function
Notes
Exit Power Down Mode Idle
(Maintain Power Down Mode) Illegal Illegal Refer Operation Command Table. Refer Operation Command Table. Refer Operation Command Table. Auto-refresh Refer Operation Command Table. Power Down Power Down Illegal Illegal Illegal Self-refresh Illegal Invalid (Continued)
Banks Idle
MB81F641642D-75/-102/-10
(Continued) Current State Bank Active Bank Activating Read/Write Clock Suspend State Other Than Listed Above Notes: Addr Function Notes
Refer Operation Command Table. Begin Clock Suspend next cycle Invalid Invalid Exit Clock Suspend next cycle Maintain Clock Suspend Invalid Refer Operation Command Table. Illegal
entries assume High during proceeding clock cycle current clock cycle. Illegal means don't used command. used, power sequence asserted after power shut down. Illegal bank specified state; entry legal bank specified depending state that bank. Illegal bank idle. Must satisfy contention, turn around, and/or write recovery requirements. bank precharging idle state. precharge bank spesified (and AP). SELF command should only issued after last read data have been appeared command should only issued condition that Hi-Z.
MB81F641642D-75/-102/-10
FUNCTIONAL DESCRIPTION
SDRAM BASIC FUNCTION
Three major differences between this SDRAM conventional DRAMs are: synchronized operation, burst mode, mode register. synchronized operation fundamental difference. SDRAM uses clock input synchronization, where DRAM basically asynchronous memory although been using clocks, CAS. Each operation DRAM determined their timing phase differences while each operation SDRAM determined commands operations referenced positive clock edge. shows basic timing diagram differences between SDRAMs DRAMs. burst mode very high speed access mode utilizing internal column address generator. Once column addresses first access set, following addresses automatically generated internal column address counter. mode register justify SDRAM operation function into desired system conditions. MODE REGISTER TABLE shows SDRAM configured system requirement mode register programming.
CLOCK (CLK) CLOCK ENABLE (CKE)
input output signals SDRAM register type buffers. used trigger register internal burst counter increment. inputs latched positive edge CLK. outputs validated CLK. high active clock enable signal. When latched clock input during active cycle, next clock will internally masked. During idle state (all banks have been precharged), Power Down mode (standby) entered with this will make extremely standby current.
CHIP SELECT (CS)
enables commands inputs, RAS, CAS, address input. When High, command signals negated internal operation such burst cycle will suspended. such control isn't needed, tied ground level.
COMMAND INPUT (RAS,
Unlike conventional DRAM, RAS, CAS, directly imply SDRAM operation, such address strobe RAS. Instead, each combination RAS, CAS, input conjunction with input rising edge determines SDRAM operation. Refer FUNCTIONAL TRUTH TABLE page
ADDRESS INPUT A11)
Address input selects arbitrary location total 1,048,576 words each memory cell matrix. total fourteen address input signals required decode such matrix. SDRAM adopts address multiplexer order reduce count address line. Bank Active command (ACTV), twelve addresses initially latched remainder eight Column addresses then latched Column address strobe command either Read command (READ READA) Write command (WRIT WRITA).
BANK SELECT (A12, A13)
This SDRAM four banks each bank organized words 16-bit. Bank selection A13, occurs Bank Active command (ACTV) followed read (READ READA), write (WRIT WRITA), precharge command (PRE).
MB81F641642D-75/-102/-10
DATA INPUTS OUTPUTS (DQ0 DQ15)
Input data latched written into memory clock following write command input. Data output obtained following conditions followed read command input: tRAC from bank active command when tRCD (min) satisfied. (This parameter reference only.) tCAC from read command when tRCD greater than tRCD (min). (This parameter reference only.) from clock edge after tRAC tCAC. polarity output data identical that input. Data valid between access time (determined three conditions above) next positive clock edge (tOH).
DATA MASK (DQML/DQMU)
DQML DQMU active high enable input output disable input mask function. During burst cycle when DQML/DQMU High latched clock, input masked same clock output will masked second clock later while internal burst counter will increment will next stage depending burst type.
BURST MODE OPERATION BURST TYPE
burst mode provides faster memory access. burst mode implemented keeping same address automatic strobing column address. Access time cycle time Burst mode specified tCK, respectively. internal column address counter operation determined mode register which defines burst type burst count length bits boundary. order terminate move from current burst mode next stage while remaining burst count more than following combinations will required: Current Stage Burst Read Burst Read Burst Write Burst Write Burst Read Burst Write Next Stage Burst Read Step Burst Write Step Burst Write Burst Read Precharge Precharge Write Command after lOWD Write Command Read Command Precharge Command Precharge Command Method (Assert following command) Read Command Mask Command (Normally clock cycles)
burst type selected either sequential interleave mode burst length sequential mode incremental decoding scheme within boundary address determined count length, assigns previous initial) address until reaching boundary address then wraps round least significant address interleave mode scrambled decoding scheme first access column address even (0), next address will (1), vice-versa. (Continued)
MB81F641642D-75/-102/-10
(Continued) When full burst operation executed single write mode, Auto-precharge command valid only write operation. burst type selected either sequential interleave mode. only sequential mode usable full column burst. sequential mode incremental decoding scheme within boundary address determined burst length, assigns previous initial) address until reaching boundary address then wraps round least significant address Burst Length Starting Column Address Sequential Mode 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Interleave 0-1-2- 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
FULL COLUMN BURST BURST STOP COMMAND (BST)
full column burst option burst length available only sequential mode burst type. This full column burst mode repeatedly access same column. burst mode reaches column address, then wraps round first column address continues count until interrupted news read (READ) /write (WRIT), precharge (PRE), burst stop (BST) command. selection Auto-precharge option illegal during full column burst operation except write command BURST READ SINGLE WRITE mode. command applicable terminate burst operation. command asserted during burst mode, operation terminated immediately internal state moves Bank Active. When read mode interrupted command, output will High-Z. detail rule, please refer TIMING DIAGRAM-8. When write mode interrupted command, data applied same time with command will ignored.
BURST READ SINGLE WRITE
burst read single write mode provides single word write operation regardless burst length. this mode, burst read operation does affected this mode.
MB81F641642D-75/-102/-10
PRECHARGE PRECHARGE OPTION (PRE, PALL)
SDRAM memory core same conventional DRAMs', requiring precharge refresh operations. Precharge rewrites line reset internal address line executed Precharge command (PRE). With Precharge command, SDRAM will automatically standby state after precharge time (tRP). precharged bank selected combination A13, when Precharge command asserted. High, banks precharged regardless A13, (PALL). Low, bank selected A12, precharged (PRE). auto-precharge enters precharge mode burst mode read write without Precharge command assertion. This auto precharge entered High when read write command asserted. Refer FUNCTIONAL TRUTH TABLE.
AUTO-REFRESH (REF)
Auto-refresh uses internal refresh address counter. SDRAM Auto-refresh command (REF) generates Precharge command internally. banks SDRAM should precharged prior Auto-refresh command. Auto-refresh command should also asserted every total 4096 refresh commands within period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh internal timer well Auto-refresh will continue refresh function until cancelled SELFX. Self-refresh entered applying Auto-refresh command conjunction with (SELF). Once SDRAM enters self-refresh mode, inputs except will "don't care" (either logic high level state) outputs will High-Z state. During self-refresh mode, should maintained. SELF command should only issued after last read data been appeared
SELF-REFRESH EXIT (SELFX)
exit self-refresh mode, apply minimum tPDE after brought high, then command (NOP) Deselect command (DESL) should asserted within period. should held High within period after tPDE. Refer Timing Diagram detail. recommended assert Auto-refresh command just after period avoid violation refresh period.
MODE REGISTER (MRS)
mode register SDRAM provides variety different operations. register consists four operation fields; Burst Length, Burst Type, latency, Operation Code. Refer MODE REGISTER TABLE page mode register programmed Mode Register command (MRS). Each field address line. Once mode register programmed, contents register will held until re-programmed another command part loses power). command should only issued condition that Hi-Z. condition mode register undefined after power-up stage. required each field after initialization SDRAM. Refer POWER-UP INITIALIZATION below.
MB81F641642D-75/-102/-10
POWER-UP INITIALIZATION
SDRAM internal condition after power-up will undefined. required follow following Power Sequence execute read write operation. Apply power start clock. Attempt maintain either DESL command input. Maintain stable power, stable clock, condition minimum Precharge banks Precharge (PRE) Precharge command (PALL). Assert minimum Auto-refresh command (REF). Program mode register Mode Register command (MRS). addition, recommended track insure that output High-Z state. Mode Register command (MRS) before Auto-refresh command (REF).
MB81F641642D-75/-102/-10
Fig. BASIC TIMING CONVENTIONAL DRAM SYNCHRONOUS DYNAMIC
<SDRAM> Active Read/Write Precharge
Read Write Address *(A13, A12) Burst Length *(A13, A12) Latency *(A13, A12) (A10)
<Conventional DRAM> Adress Select
Column Address Select
Precharge
MB81F641642D-75/-102/-10
MINIMUM CLOCK LATENCY DELAY TIME BANK OPERATION
READA WRITA
Second command (same bank) First command
WRIT
PALL
READ
ACTV
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
tRCD
tRCD
tRCD
tRCD
tRAS
tRAS
READ
READA
tDPL tDPL
WRIT
WRITA
tDAL
tDAL
tDAL
tDAL
PALL
SELFX Notes:
Assume conflict. tCK, minimum latency Assume output High-Z state. Assume tRAS satisfied. Illegal Command
SELF
MB81F641642D-75/-102/-10
MINIMUM CLOCK LATENCY DELAY TIME MULTI BANK OPERATION
READA WRITA
Second command (other bank) First command
WRIT
PALL
READ
ACTV
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
tRRD
tRAS
READ
READA
WRIT
SELF
WRITA
tRAS
PALL
SELFX Notes:
Assume other bank (second command will asserted) idle state. Assume other bank (second command will asserted) active state. Assume conflict. tCK, minimum latency Assume PALL command dose affect operation other banks. Assume output High-Z sate. Assume tRAS other bank (second command will asserted) satisfied. Assume tRAS (ACTV PALL) satisfied. other bank (second command will asserted) should interrupted, tRAS bank satisfied. Illegal Command
MB81F641642D-75/-102/-10
Fig. STATE DIAGRAM (Simplified Single BANK Operation State Diagram)
MODE REGISTER IDLE
SELF SELFX SELF REFRESH CKE\(PD) AUTO REFRESH POWER DOWN
BANK ACTIVE SUSPEND
CKE\ WRIT WRIT WRITA READA READ WRIT WRITA READA PALL WRITA READA READ CKE\ READ SUSPEND CKE\ WRITE READ READ BANK ACTIVE
WRITE SUSPEND
WRITE SUSPEND
CKE\ CKE\
WRITE WITH AUTO PRECHARGE PALL
ACTV
READ WITH CKE\ AUTO PRECHARGE PALL
READ SUSPEND
POWER
PALL
PRECHARGE
POWER APPLIED DEFINITION ALLOWS Manual Input Automatic Sequence
MB81F641642D-75/-102/-10
ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Voltage Supply Relative Voltage Relative Short Circuit Output Current Power Dissipation Storage Temperature Symbol VCC, VCCQ VIN, VOUT IOUT TSTG Value -0.5 +4.6 -0.5 +4.6 +125 Unit
WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
(Referenced VSS)
Parameter Supply Voltage VSS, VSSQ Input High Voltage Input Voltage Ambient Temperature Notes: -0.5 Notes Symbol VCC, VCCQ Min. Typ. Max. Unit
Overshoot limit: (max) +1.5 with pulsewidth Undershoot limit: (min) -1.5 with pulsewidth
WARNING: Recommended operating conditions normal operating ranges semiconductor device. device's electrical characteristics warranted when operated within these ranges. Always semiconductor devices within recommended operating conditions. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representative beforehand.
CAPACITANCE
25°C, MHz) Parameter Input Capacitance, Except Input Capacitance Capacitance Symbol CIN1 CIN2 CI/O Min. Typ. Max. Unit
MB81F641642D-75/-102/-10
CHARACTERISTICS
recommended operating conditions unless otherwise noted.) Note
Parameter Output High Voltage Output Voltage Input Leakage Current (Any Input) Output Leakage Current MB81F641642D-75 MB81F641642D-102 MB81F641642D-10 Operating Current (Average Power Supply Current) ICC1S Symbol VOH(DC) VOL(DC) Condition VCC; other pins under test VCC; Data disabled Burst: Length bank active Outputs open Addresses changed 3-times during (min) Burst: Length (each Bank) (each Bank) banks active Outputs open Addresses changed 6-times during (min) banks idle Power down mode banks idle Power down mode banks idle, commands only, Input signals (except CMD) changed time during clock cycles banks idle Input signal stable Value Min. Max. Unit
MB81F641642D-75 MB81F641642D-102
ICC1D
MB81F641642D-10
ICC2P
ICC2PS Precharge Standby Current (Power Supply Current)
MB81F641642D-75 MB81F641642D-102 MB81F641642D-10 ICC2N
ICC2NS
(Continued)
MB81F641642D-75/-102/-10
(Continued) Parameter Symbol Condition bank active bank active bank active commands only, Input signals (except CMD) changed time during clock cycles bank active Burst Length Outputs open Multiple-banks active Gapless data Auto-refresh; Self-refresh; Value Min. Max. Unit
ICC3P
ICC3PS Active Standby Current (Power Supply Current)
MB81F641642D-75 MB81F641642D-102 MB81F641642D-10 ICC3N
ICC3NS
MB81F641642D-75 Burst mode Current MB81F641642D-102 (Average Power Supply Current) MB81F641642D-10 MB81F641642D-75 Refresh Current MB81F641642D-102 (Average Power Supply Current) MB81F641642D-10 Refresh Current (Average Power Supply Current) ICC4
ICC5
ICC6
MB81F641642D-75/-102/-10
CHARACTERISTICS
recommended operating conditions unless otherwise noted.) Note
MB81F641642D-75 MB81F641642D-102 MB81F641642D-10
Parameter
Notes
Symbol Min. tCK2 tCK3 tAC2 tAC3 tHZ2 tHZ3 Max. Min. Max. Min. Max.
Unit
Clock Period Clock High Time Clock Time Input Setup Time Input Hold Time Access Time from Clock (tCK min) Output Low-Z Output High-Z
Output Hold Time Time between Auto-Refresh command interval Time between Refresh Transition Time Setup Time Power Down Exit Time
tREFI tREF tCKSP
15.6
15.6
15.6
MB81F641642D-75/-102/-10
BASE VALUES CLOCK COUNT/LATENCY
MB81F641642D-75 MB81F641642D-102 MB81F641642D-10
Parameter Cycle Time Precharge Time Active Time Delay Time Write Recovery Time
Notes
Symbol
Unit Min. Max. 100000 Min. Max. 100000 Min. Max. 100000
tRAS
tRCD tRRD tDPL tDAL2 tDAL3 tRSC
Bank Active Delay Time Data-in Precharge Lead Time CL=2 Data-in Active/Refresh Command Period CL=3 Mode Resister Cycle Time
CLOCK COUNT FORMULA
Clock
Note (Round whole number)
Base Value Clock Period
MB81F641642D-75/-102/-10
LATENCY FIXED VALUES
(The latency values these parameters fixed regardless clock period.) Parameter Clock Disable Output High-Z Input Data Delay Last Output Write Command Delay Write Command Input Data Delay Precharge Output High-Z Delay Burst Stop Command Output High-Z Delay Delay (min) Bank Delay (min) Notes: *10. Notes Symbol lCKE lDQZ lDQD lOWD lDWD lROH2 lROH3 lBSH2 lBSH3 lCCD lCBD
MB81F641642D-75 MB81F641642D-102 MB81F641642D-10
Unit cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
depends output termination load conditions, clock cycle rate, signal clocking rate; specified values obtained with output open termination register. initial pause (DESL NOP) required after power-up followed minimum eight Auto-refresh cycles. characteristics assume capacitive load. reference level measuring timing input signals. Transition times measured between (min) (max). (See Fig. Maximum value depends tCK. also specifies access time burst mode except first access. Specified where output buffer longer driven. tOH, tLZ, define times which output level achieves ±200 Actual clock count (lRC) will clock count tRAS (lRAS) (lRP). Operation within tRCD (min) ensures that access time detetermined tRCD (min) (max); tRCD greater than specified tRCD (min), access time determined tAC. base values measured from clock edge command input clock edge next command input. clock counts calculated simple formula: clock count equals base value divided clock period (round whole number).
MB81F641642D-75/-102/-10
Fig. EXAMPLE TEST LOAD CIRCUIT
Output
LVTTL
Note: characteristics measured this condition. This load circuits applicable VOL.
MB81F641642D-75/-102/-10
Fig. TIMING DIAGRAM, SETUP, HOLD DELAY TIME
Input (Control, Addr. Data)
Output
Note: Reference level input signal LVTTL. Access time measured LVTTL.
Fig. TIMING DIAGRAM, DELAY TIME POWER DOWN EXIT
Don't Care
tCKSP (min)
clock (min)
Command
Don't Care
ACTV
MB81F641642D-75/-102/-10
Fig. TIMING DIAGRAM, PULSE WIDTH
Input (Control)
tRC, tRP, tRAS, tRCD, tWR, tREF, tDPL, tDAL, tRSC, tRRD, tCKSP
COMMAND COMMAND
Note: These parameter limit value rising edge clock from command input next input. tCKSP latency value from rising edge CKE. Measurement reference voltage
Fig. TIMING DIAGRAM, ACCESS TIME
tRAC
tRCD
tCAC
(CAS Latency
(Output)
Note: tRAC tCAC reference values. Data obtained after both tCAC (CL-1) satisfied.
(Valid)
MB81F641642D-75/-102/-10
MODE REGISTER TABLE
MODE REGISTER
Opcode ADDRESS MODE REGISTER
Latency Reserved Reserved Reserved Reserved Reserved Reserved
Burst Length Reserved Reserved Reserved Full Column Reserved Reserved Reserved Reserved Reserved
Op-code Burst Read Burst Write Burst Read Single Write
Burst Type Sequential (Wrap round, Binary-up) Interleave (Wrap round, Binary-up)
Notes: When burst length Write always regardless value. Full Column applicable interleave mode.
MB81F641642D-75/-102/-10
TIMING DIAGRAM CLOCK ENABLE READ WRITE SUSPEND
ICKE clock) (Internal)
ICKE clock)
(Read)
CHANGE)
CHANGE)
(Write)
WRITTEN
WRITTEN
Notes: latency (lCKE) clock. During read mode, burst counter will incremented/decremented next clock CSUS command. Output remain same data. During write mode, data next clock CSUS command ignored.
TIMING DIAGRAM CLOCK ENABLE POWER DOWN ENTRY EXIT
tCKSP
clock (min)
Command
PD(NOP)
DON'T CARE
ACTV
tREF (max)
Notes: Precharge command (PRE PALL) should asserted bank active burst mode. Precharge command posted conjunction with after last read data have been appeared ACTV command latched after tCKSP (min) clock (min). recommended apply command conjunction with CKE.
MB81F641642D-75/-102/-10
TIMING DIAGRAM COLUMN ADDRESS COLUMN ADDRESS INPUT DELAY
ICCD tRCD (min)
clock)
ICCD
ICCD
ICCD
Address
ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
Note: address delay more clock period.
TIMING DIAGRAM DIFFERENT BANK ADDRESS INPUT DELAY
tRRD (min) tRCD (min) tRCD (min) Address
ADDRESS ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS
ICBD
ICBD
A12, A13(BA)
Bank
Bank
Bank
Bank
Bank
Bank
MB81F641642D-75/-102/-10
TIMING DIAGRAM DQMU, DQML INPUT MASK OUTPUT DISABLE
DQML, DQMU Read) IDQZ clocks) Read)
Hi-Z
burst
DQML, DQMU Write) IDQD (same clock) Write)
MASKED
burst
TIMING DIAGRAM PRECHARGE TIMING (APPLIED SAME BANK)
tRAS (min) Command
ACTV
PRECHARGE
MB81F641642D-75/-102/-10
TIMING DIAGRAM READ INTERRUPTED PRECHARGE (EXAMPLE
Command
PRECHARGE
IROH clocks)
Hi-Z
Command
PRECHARGE
IROH clocks)
Hi-Z
Command
PRECHARGE
IROH clocks)
Hi-Z
Command
PRECHARGE effect (end burst)
Note: case lROH clock. case lROH clock.
MB81F641642D-75/-102/-10
TIMING DIAGRAM READ INTERRUPTED BURST STOP (EXAMPLE Full Column)
Command
lBSH clocks)
Hi-Z
Qn-2
Qn-1
Qn+1
Command
lBSH clocks)
Hi-Z Qn-2 Qn-1 Qn+1 Qn+2
TIMING DIAGRAM WRITE INTERRUPTED BURST STOP (EXAMPLE
Command
COMMAND
LAST DATA-IN
Masked
MB81F641642D-75/-102/-10
TIMING DIAGRAM WRITE INTERRUPTED PRECHARGE (EXAMPLE
Command
PRECHARGE
ACTIVE
tDPL (min)
(min)
DATA-IN
LAST DATA-IN
MASKED
Note: precharge command (PRE) should only issued after tDPL final data input, satisfied.
TIMING DIAGRAM READ INTERRUPTED WRITE (EXAMPLE
IOWD clocks) Command
Read
Write
(DQML, DQMU)
Note
Note
Note
IDQZ clocks)
IDWD (same clock)
DATA Masked DATA
DATA
Notes: First makes high-impedance state High-Z between last output first input data. Second makes internal output data mask avoid contention. Third illustrated above also makes internal output data mask. burst read ends (final data output) after second clock burst write, this third required avoid internal contention.
MB81F641642D-75/-102/-10
TIMING DIAGRAM WRITE READ TIMING (EXAMPLE
(min) Command
WRITE READ
(DQML, DQMU) (CL-1)
Masked Read
(max)
Note: Read command should issued after final data input satisfied read command applied same bank.
MB81F641642D-75/-102/-10
TIMING DIAGRAM READ WITH AUTO-PRECHARGE (EXAPLE Applied same bank)
tRAS (min) (min)
Command
ACTV
READA clocks (same value
DESL
ACTV
BL+tRP (min)
(DQML, DQMU)
Notes: Precharge read with Auto-precharge command (READA) started from number clocks that same Burst Length (BL) after READA command asserted. Next ACTV command should issued after BL+tRP (min) from READA command.
TIMING DIAGRAM WRITE WITH AUTO-PRECHARGE (EXAMPLE Applied same bank)
tRAS (min)
tDPL (min)
tDAL (min) BL+tRP (min)
Command
ACTV
WRITA
DESL
ACTV
(DQML, DQMU)
Notes: Precharge write with Auto-precharge started after tDPL from burst. Even final data masked DQM, precharge does start clock final data input. Once auto precharge command asserted, command within same bank issued. Auto-precharge command doesn't affect full column burst operation except Burst READ Single Write. Next command should issued after (min) BL+1+tRP (min) from WRITA command.
MB81F641642D-75/-102/-10
TIMING DIAGRAM AUTO-REFRESH TIMING
Command
Command
(min)
(min)
DON'T CARE
A12, A13(BA)
DON'T CARE
Notes: banks should precharged prior first Auto-refresh command (REF). Bank select ignored command. refresh address bank select selected internal refresh counter. Either DESL command should asserted during period while Auto-refresh mode. activation command such ACTV command other than command should asserted after from last comand.
TIMING DIAGRAM SELF-REFRESH ENTRY EXIT TIMING
tCKSP (min) (min) (min)
Command
SELF
DON'T CARE
SELFX
Command
Notes: Precharge command (PRE PALL) should asserted bank active prior Self-refresh Entry command (SELF). Self-refresh Exit command (SELFX) latched after tCKSP (min). recommended apply command conjunction with CKE. Either DESL command used during period. should held high within period after tCKSP.
MB81F641642D-75/-102/-10
TIMING DIAGRAM MODE REGISTER TIMING
tRSC
Command
DESL
ACTV
Address
MODE
ADRESS
Notes: Mode Register command (MRS) should only asserted after banks have been precharged.
MB81F641642D-75/-102/-10
PACKAGE DIMENSION
54-pin plasticTSOP(II) (FPT-54P-M02)
Resin protrusion. (Each side: 0.15 (.006) MAX)
Dimensions (inches)
MB81F641642D-75/-102/-10
MEMO
MB81F641642D-75/-102/-10
MEMO
MB81F641642D-75/-102/-10
MEMO
MB81F641642D-75/-102/-10
FUJITSU LIMITED
further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. Fri.: (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA #05-08, Lorong Chuan Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. FUJITSU semiconductor devices intended standard applications (computers, office automation other office equipment, industrial, communications, measurement equipment, personal household devices, etc.). CAUTION: Customers considering products special applications where failure abnormal operation directly affect human lives cause physical injury property damage, where extremely high levels reliability demanded (such aerospace systems, atomic energy controls, floor repeaters, vehicle operating controls, medical devices life support, etc.) requested consult with FUJITSU sales representatives before such use. company will responsible damages arising from such without prior approval. semiconductor devices have inherently certain rate failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Control Japan, prior authorization Japanese government should required export those products from Japan.
F9804 FUJITSU LIMITED Printed Japan

MEMORY SYNCHRONOUS DYNAMIC MB81F641642D-75/-102/-10 CMO

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