FLASH MEMORY (512K MBM29F040A 70/-90/-12 DISTINCTIVE CH

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FLASH MEMORY (512K MBM29F040A 70/-90/-12 DISTINCTIVE CH

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DS05-20810-3E
FLASH MEMORY
(512K
MBM29F040A 70/-90/-12
DISTINCTIVE CHARACTERISTICS
Single read, write erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands E2PROMs Compatible with JEDEC-standard byte-wide pinouts 32-pin PLCC (Package suffix: 32-pin TSOP (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type) Note: there special requirements specified above (such package), please contact Fujitsu sales office. Minimum 100,000 write/erase cycles High performance maximum access time Sector erase architecture equal size sectors bytes each combination sectors concurrently erased. Also supports full chip erase. Embedded EraseAlgorithms Automatically pre-programs erases chip sector Embedded ProgramAlgorithms Automatically writes verifies data specified address Data Polling Toggle feature detection program erase cycle completion power consumption typical active read current typical write/erase current typical standby current write inhibit Sector protection Hardware method disables combination sectors from write erase operations Erase Suspend/Resume Suspends erase operation allow read data another sector within same device
Embedded Eraseand Embedded Programare trademarks Advanced Micro Devices, Inc.
MBM29F040A -70/-90/-12
PACKAGE
Marking Side
32-pin Plastic (LCC-32P-M02) Marking Side Marking Side
32-pin Plastic TSOP (FPT-32P-M24 Assembly: Malaysia)
32-pin Plastic TSOP (FPT-32P-M25 Assembly: Malaysia)
MBM29F040A -70/-90/-12
GENERAL DESCRIPTION
MBM29F040A 4M-bit, V-only Flash memory organized 512K bytes bits each. MBM29F040A offered 32-pin PLCC 32-pin TSOP package. This device designed programmed in-system with standard system supply. 12.0 required write erase operations. device also reprogrammed standard EPROM programmers. standard MBM29F040A offers access times between allowing operation high-speed microprocessors without wait states. eliminate contention device separate chip enable write enable output enable controls. MBM29F040A command compatible with JEDEC standard 4M-bit E2PROMs. Commands written command register using standard microprocessor write timings. Register contents serve input internal state-machine which controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from 12.0 Flash EPROM devices. MBM29F040A programmed executing program command sequence. This will invoke Embedded Program Algorithm which internal algorithm that automatically times program pulse widths verifies proper cell margin. Typically, each sector programmed verified less than second. Erase accomplished executing erase command sequence. This will invoke Embedded Erase Algorithm which internal algorithm that automatically preprograms array already programmed before executing erase operation. During erase, device automatically times erase pulse widths verifies proper cell margin. entire chip individual sector typically erased verified seconds. already completely preprogrammed.) This device also features sector erase architecture. sector mode allows byte sectors memory erased reprogrammed without affecting other sectors. MBM29F040A erased when shipped from factory. device features single power supply operation both read write functions. Internally generated regulated voltages provided program erase operations. detector automatically inhibits write operations loss power. program erase detected Data Polling Toggle feature DQ6. Once program erase cycle been completed, device internally resets read mode. Fujitsu's Flash technology combines years EPROM E2PROM experience produce highest levels quality, reliability cost effectiveness. MBM29F040A memory electrically erases entire chip bits within sector simultaneously Fowler-Nordhiem tunneling. bytes programmed byte time using EPROM programming mechanism electron injection.
MBM29F040A -70/-90/-12
FLEXIBLE SECTOR-ERASE ARCHITECTURE
byte sector Individual-sector, multiple-sector, bulkerase capability Individual multiple-sector protection user definable 7FFFFH 6FFFFH byte sector 5FFFFH 4FFFFH 3FFFFH 2FFFFH 1FFFFH 0FFFFH 00000H
MBM29F040A -70/-90/-12
PRODUCT SELECTOR GUIDE
Part Ordering Part Max. Access Time (ns) Access (ns) Access (ns) MBM29F040A MBM29F040A MBM29F040A MBM29F040A
BLOCK DIAGRAM
Erase Voltage Generator Input/Output Buffers
State Control Command Register Program Voltage Generator Chip Enable Output Enable Logic Data Latch
Y-Decoder
Y-Gating
Detector
Timer
Address Latch
X-Decoder
Cell Matrix
MBM29F040A -70/-90/-12
CONNECTION DIAGRAMS
PLCC
LCC-32P-M02 TSOP
Marking Side
MBM29F040A Standard Pinout
FPT-32P-M24
Marking Side
MBM29F040A Reverse Pinout
FPT-32P-M25
MBM29F040A -70/-90/-12
LOGIC SYMBOL
Table MBM29F040A Configuration
Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Device Ground Device Power Supply (5.0
Table MBM29F040A User Operations Operation Auto-Select Manufacturer Code Auto-Select Device Code Read Standby Output Disable Write Enable Sector Protection Verify Sector Protection
Code Code DOUT HIGH-Z HIGH-Z Code
Legend: VIL, VIH, VIH. Characteristics voltage levels. Notes: Manufacturer device codes also accessed command register write sequence. Refer Table Refer section Sector Protection. VIL, initiates write operations.
MBM29F040A -70/-90/-12
ORDERING INFORMATION
Standard Products
Fujitsu standard products available several packages. order number formed combination
MBM29F040A
PACKAGE TYPE 32-Pin Rectangular Plastic Leaded Chip Carrier (PLCC) PFTN 32-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout SPEED OPTION Product Selector Guide
DEVICE NUMBER/DESCRIPTION MBM29F040A 4Mega-bit (512K 8-Bit) CMOS Flash Memory V-only Read, Write, Erase Byte Sectors
MBM29F040A -70/-90/-12
Read Mode
MBM29F040A control functions which must satisfied order obtain data outputs. power control should used device selection. output control should used gate data output pins device selected. Address access time (tACC) equal delay from stable addresses valid output data. chip enable access time (tCE) delay from stable addresses stable valid data output pins. output enable access time delay from falling edge valid data output pins (assuming addresses have been stable least tACC-tOE time).
Standby Mode
MBM29F040A standby modes, CMOS standby mode input held V.), when current consumed less than standby mode held VIH.) when current required reduced approximately standby mode outputs high impedance state, independent input. device deselected during erasure programming, device will draw active current until operation completed.
Output Disable
With input logic high level (VIH), output from device disabled. This will cause output pins high impedance state.
Autoselect
autoselect mode allows reading binary code from device will identify manufacturer type. This mode intended programming equipment purpose automatically matching device programmed with corresponding programming algorithm. This mode functional over entire temperature range device. activate this mode, programming equipment must force (11.5 12.5 address identifier bytes then sequenced from device outputs toggling address from VIH. addresses DON'T CARES except manufacturer device codes also read command register, instances when MBM29F040A erased programmed system without access high voltage pin. command sequence illustrated Table (Refer Autoselect Command section.) Table MBM29F040A Sector Protection Verify Autoselect Codes Type Manufacture's Code Device Code Sector Protection Code (HEX)
Sector Addresses
01H*
Outputs protected sector addresses unprotected sector addresses.
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Table Sector Address Tables Sector Address Address Range 00000H 0FFFFH 10000H 1FFFFH 20000H 2FFFFH 30000H 3FFFFH 40000H 4FFFFH 50000H 5FFFFH 60000H 6FFFFH 70000H 7FFFFH
Byte VIL) represents manufacture's code (Fujitsu 04H) byte VIH) device identifier code (MBM29F040A A4H). These bytes given Table identifiers manufactures device will exhibit parity with (DQ7) defined parity bit. order read proper device codes when executing autoselect, must VIL. (See Table
Write
Device erasure programming accomplished command register. contents register serve inputs internal state machine. state machine outputs dictate function device. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. command register written bringing VIL, while VIH. Addresses latched falling edge whichever happens later; while data latched rising edge whichever happens first. Standard microprocessor write timings used. Refer Write Characteristics Erase/Programming Waveforms specific timing parameters.
Sector Protection
MBM29F040A features hardware sector protection. This feature will disable both program erase operations number sectors through sector protection feature enabled using programming equipment user's site. device shipped with sectors unprotected. activate this mode, programming equipment must force address control (suggest 11.5 VIL. sector addresses (A18, A16) should sector protected. Table defines sector address each eight individual sectors. Programming protection circuitry begins falling edge pulse terminated with rising edge same. Sector addresses must held constant during pulse. Refer figures sector protection waveforms algorithm. verify programming protection circuitry, programming equipment must force address with VIH. Scanning sector addresses (A16, A17, A18) while (A6, will produce logical code device output protected sector. Otherwise device will produce unprotected sector. this mode, lower order addresses, except
MBM29F040A -70/-90/-12
DON'T CARES. Address locations with reserved Autoselect manufacturer device codes. also possible determine sector protected system writing Autoselect command. Performing read operation address location XX02H, where higher order addresses (A16, A17, A18) sector address will produce logical protected sector. Table Autoselect codes. Table MBM29F040A Command Definitions Fourth First Second Third Fifth Sixth Write Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Cycles Req'd Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data XXXXH
Command Sequence Read/Reset
Read/Reset* Read/Reset* Autoselect Byte Program Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume
5555H 2AAAH 5555H 5555H 2AAAH 5555H 5555H 2AAAH 5555H
5555H 2AAAH 5555H 5555H 2AAAH 5555H 5555H 2AAAH 5555H 5555H 2AAAH
Erase suspended during sector erase with Addr Data (B0H) Erase resumed after suspend with Addr Data (30H)
Notes: Address bits address commands except Program Address (PA) Sector Address (SA). operations defined Table Address memory location read. Address memory location programmed. Addresses latched falling edge pulse. Address sector erased. combination A18, A17, will uniquely select sector. Data read from location during read operation. Data programmed location Data latched falling edge Either reset commands will reset device.
Command Definitions
Device operations selected writing specific address data sequences into command register. Writing incorrect address data values writing them improper sequence will reset device read mode. Table defines valid register command sequences. Note that Erase Suspend (B0) Erase Resume (30) commands valid only while Sector Erase operation progress.
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Read/Reset Command
read reset operation initiated writing read/reset command sequence into command register. Microprocessor read cycles retrieve array data from memory. device remains enabled reads until command register contents altered. device will automatically power-up read/reset state. this case, command sequence required read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that spurious alteration memory content occurs during power transition. Refer Read Characteristics Waveforms specific timing parameters.
Autoselect Command
Flash memories intended applications where local alters memory contents. such, manufacture device codes must accessible while device resides target system. PROM programmers typically access signature codes raising high voltage (VID 11.5 12.5 However, multiplexing high voltage onto address lines generally desired system design practice. device contains autoselect command operation supplement traditional PROM programming methodology. operation initiated writing autoselect command sequence into command register. Following command write, read cycle from address XX00H retrieves manufacture code 04H. read cycle from address XX01H returns device code A4H. (See Table manufacturer device codes will exhibit parity with (DQ7) defined parity bit. Sector state (protection unprotection) will informed address XX02H. Scanning sector addresses (A16, A17, A18) while (A6, will produce logical device output protected sector. terminate operation, necessary write read/reset command sequence into register.
Byte Programming
device programmed byte-by-byte basis. Programming four cycle operation. There "unlock" write cycles. These followed program set-up command data write cycles. Addresses latched falling edge whichever happens later data latched rising edge whichever happens first. rising edge (whichever happens first) begins programming. Upon executing Embedded Program Algorithm command sequence system required provide further controls timings. device will automatically provide adequate internally generated program pulses verify programmed cell margin. automatic programming operation completed when data equivalent data written this (See Write Operation Status section.) which time device returns read mode addresses longer latched. Therefore, device requires that valid address device supplied system this particular instance time. Hence, Data Polling must performed memory location which being programmed. commands written chip during this period will ignored. Programming allowed sequence across sector boundaries. Beware that data cannot programmed back "1". Attempting will probably hang device (Exceed timing limits.), perhaps result apparent success according data polling algorithm read from reset/read mode will show that data still "0". Only erase operations convert "0"s "1"s. Figure illustrates Embedded Programming Algorithm using typical command strings operations.
Chip Erase
Chip erase cycle operation. There "unlock" write cycles. These followed writing
MBM29F040A -70/-90/-12
"set-up" command. more "unlock" write cycles then followed chip erase command. Chip erase does require user program device prior erase. Upon executing Embedded Erase Algorithm command sequence device automatically will program verify entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. automatic erase begins rising edge last pulse command sequence terminates when data (See Write Operation Status section.) which time device returns read mode. Figure illustrates Embedded Erase Algorithm using typical command strings operations.
Sector Erase
Sector erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed sector erase command. sector address (Any address location within desired sector.) latched falling edge while command (Data=30H) latched rising edge time-out from rising edge last sector erase command will initiate sector erase command(s). Multiple sectors erased concurrently writing cycle operations described above. This sequence followed with writes Sector Erase command addresses other sectors desired concurrently erased. time between writes must less than otherwise that command will accepted. recommended that processor interrupts disabled during this time guarantee this condition. interrupts re-enabled after last Sector Erase command written. time-out from rising edge last will initiate execution Sector Erase command(s). another falling edge occurs within time-out window timer reset. (Monitor determine sector erase timer window still open, section DQ3, Sector Erase Timer.) command other than Sector Erase Erase Suspend during this time-out period will reset device read mode, ignoring previous command string. Resetting device after begun execution will result data operated sectors being undefined (messed up). that case, restart erase those sectors allow them complete. (Refer Write Operation Status section Sector Erase Timer operation.) Loading sector erase buffer done sequence with number sectors Sector erase does require user program device prior erase. device automatically programs memory locations sector(s) erased prior electrical erase. When erasing sector sectors remaining unselected sectors affected. system required provide controls timings during these operations. automatic sector erase begins after time from rising edge pulse last sector erase command pulse terminates when data (See Write Operation Status section.) which time device returns read mode. During execution Sector Erase command, only Erase Suspend Erase Resume commands allowed. other commands will reset device read mode. Data polling must performed address within sectors being erased. Figure illustrates Embedded Erase Algorithm using typical command strings operations.
Erase Suspend
Erase Suspend command allows user interrupt chip then data reads (not program) from non-busy sector while middle Sector Erase operation (which take several seconds). This command applicable ONLY during Sector Erase operation will ignored written during chip Erase Programming operation. Erase Suspend command (B0) will allowed only during Sector Erase Operation that will include sector erase time-out period after Sector Erase commands (30). Writing this command during time-out will result immediate termination time-out period.
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subsequent writes Sector Erase command will taken Erase Resume command. Note that other commands during time will reset device read mode. addresses DON' CARES writing Erase Suspend Erase Resume commands. When Erase Suspend command written during Sector Erase operation, chip will take between suspend erase operation into erase suspended read mode (pseudo-read mode), during which user read from sector that being erased. read from sector being erased result invalid data. user must monitor toggle determine chip entered pseudo-read mode, which time toggle stops toggling. address sector being erased must used read toggle bit, otherwise user encounter intermittent problems. Note that user must keep track what state chip since there external indication whether chip pseudo-read mode actual read mode. After user writes Erase Suspend command waits until toggle stops toggling, data reads from device then performed. further writes Erase Suspend command this time will ignored. Every time Erase Suspend command followed Erase Resume command written, internal (pulse) counters reset. These counters used count number high voltage pulses memory cell requires program erase. count exceeds certain limit, then will (Exceeded Time Limit flag). This resetting counters necessary since Erase Suspend command potentially interrupt disrupt high voltage pulses. resume operation Sector Erase, Resume command (30) should written. further writes Resume command this point will ignored. Another Erase Suspend command written after chip resumed.
Write Operation Status
Table Hardware Sequence Flags Status Auto-programming progress Program/Erase Auto Erase Erase Suspend Read (Erase Suspended Sector) Erase Suspend Read (Non-Erase Suspended Sector) Auto-Programming Program/Erase Auto-Erase Data Toggle Data Toggle Toggle Data Data Toggle
Erase Suspended Mode
Exceeded Time Limits
Note: DQ0, reserve pins future use. Fujitsu internal only. Data Polling MBM29F040A device features Data Polling method indicate host that Embedded Algorithms progress completed. During Embedded Program Algorithm attempt read device will produce compliment data last written DQ7. Upon completion Embedded Program
MBM29F040A -70/-90/-12
Algorithm, attempt read device will produce true data last written DQ7. During Embedded Erase Algorithm, attempt read device will produce output. Upon completion Embedded Erase Algorithm attempt read device will produce output. flowchart Data Polling (DQ7) shown Figure chip erase, sector erase Data Polling valid after rising edge sixth pulse write pulse sequence. sector erase, Data Polling valid after last rising edge sector erase pulse. Data Polling must performed sector address within sectors being erased protected sector. Otherwise, status valid. Once Embedded Algorithm operation close being completed, MBM29F040A data pins (DQ7) change asynchronously while output enable asserted low. This means that device driving status information instant time then that byte's valid data next instant time. Depending when system samples output, read status valid data. Even device completed Embedded Algorithm operation valid data, data outputs still invalid. valid data will read successive read attempts. Data Polling feature only active during Embedded Programming Algorithm, Embedded Erase Algorithm, sector erase time-out (see Table Figure Data Polling timing specifications diagrams. Toggle MBM29F040A also features "Toggle Bit" method indicate host system that Embedded Algorithms progress completed. During Embedded Program Erase Algorithm cycle, successive attempts read toggling) data from device will result toggling between zero. Once Embedded Program Erase Algorithm cycle completed, will stop toggling valid data will read next successive attempts. During programming, Toggle valid after rising edge fourth pulse four write pulse sequence. chip erase sector erase, Toggle valid after rising edge sixth pulse write pulse sequence. Sector erase, Toggle valid after last rising edge sector erase pulse. Toggle active during sector time out. programming, sector being written protected, toggle will toggle about then stop toggling without data having changed. erase, device will erase selected sectors except ones that protected. selected sectors protected, chip will toggle toggle about then drop back into read mode, having changed none data. Either toggling will cause toggle. addition, Erase Suspend/Resume command will cause toggle. (See Figure Toggle timing specifications diagrams.) Exceeded Timing Limits will indicate program erase time exceeded specified limits (internal pulse count). Under these conditions will produce "1". This failure condition which indicates that program erase cycle successfully completed. Data Polling only operating function device under this condition. circuit will partially power down device under these conditions approximately mA). pins will control output disable functions described Table this failure condition occurs during sector erase operation, specifies that particular sector reused, however, other sectors still functional used program erase operation. device must reset other sectors. Write Reset command sequence device,
MBM29F040A -70/-90/-12
then execute program erase command sequence. This allows system continue other active sectors device. this failure condition occurs during chip erase operation, specifies that entire chip combination sectors bad. this failure condition occurs during byte programming operation, specifies that entire sector containing that byte this sector reused, (other sectors still functional reused). failure condition also appear user tries program blank location without erasing. this case device locks never completes Embedded Algorithm operation. Hence, system never reads valid data never stops toggling. Once device exceeded timing limits, will indicate "1." Please note that this device failure condition since device incorrectly used. Sector Erase Timer After completion initial sector erase command sequence sector erase time-out will begin. will remain until time-out complete. Data Polling Toggle valid after initial sector erase command sequence. Data Polling Toggle indicates device been written with valid erase command. used determine sector erase timer window still open. high ("1") internally controlled erase cycle begun; attempts write subsequent commands device will ignored until erase operation completed indicated Data Polling Toggle Bit. ("0"), device will accept additional sector erase commands. insure command been accepted, system software should check status prior following each subsequent sector erase command. were high second status check, command have been accepted. Refer Table Hardware Sequence Flags.
Data Protection
MBM29F040A designed offer protection against accidental erasure programming caused spurious system level signals that exist during power transitions. During power device automatically resets internal state machine Read mode. Also, with control register architecture, alteration memory contents only occurs after successful completion specific multi-bus cycle command sequences. device also incorporates several features prevent inadvertent write cycles resulting form power-up power-down transitions system noise.
Write Inhibit
avoid initiation write cycle during power-up power-down, write cycle locked less than (typically VLKO, command register disabled internal program/erase circuits disabled. Under this condition device will reset read mode. Subsequent writes will ignored until level greater than VLKO.
Write Pulse "Glitch" Protection
Noise pulses less than (typical) will initiate write cycle.
Logical Inhibit
Writing inhibited holding VIL, VIH, VIH. initiate write cycle
MBM29F040A -70/-90/-12
must logical zero while logical one.
Power-Up Write Inhibit
Power-up device with =VIL will accept commands rising edge internal state machine automatically reset read mode power-up.
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature .-45 +125 Ambient Temperature with Power Applied .-25 Voltage with Respect Ground pins except (Note -2.0 +7.0 (Note .-2.0 +7.0 (Note .-2.0 +13.5 Notes: Minimum voltage input pins -0.5 During voltage transitions, inputs negative overshoot -2.0 periods Maximum voltage output pins +0.5 During voltage transitions, outputs positive overshoot +2.0 periods Minimum input voltage pins -0.5 During voltage transitions, pins negative overshoot -2.0 periods Maximum input voltage pins +13.5 which overshoot 14.0 periods Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure device absolute maximum rating conditions extended periods affect device reliability.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Supply Voltages MBM29F040A-70 .+4.75 +5.25 MBM29F040A-90/-12 .+4.50 +5.50 Operating ranges define those limits between which functionality device guaranteed.
MBM29F040A -70/-90/-12
MAXIMUM OVERSHOOT
+0.8 -0.5 -2.0
Figure Maximum Negative Overshoot Waveform
CC+2.0 CC+0.5 +2.0
Figure Maximum Positive Overshoot Waveform
+13.5 +13.0 CC+0.5
*:This waveform applied RESET.
Figure Maximum Positive Overshoot Waveform
MBM29F040A -70/-90/-12
CHARACTERISTICS
TTL/NMOS Compatible Parameter Symbol ILIT ICC1 ICC2 ICC3 VLKO Parameter Description Input Leakage Current Output Leakage Current Inputs Leakage Current Active Current (Note Active Current (Note Standby Current Input Level Input High Level Voltage Autoselect Sector Protection (A9, Output Voltage Level Output High Voltage Level Lock-Out Voltage Min. -2.5 Min. Test Condition VCC, Max. VOUT VCC, Max. Max., 12.0 VIL, VIL, Max., Min. -0.5 11.5 Max. ±1.0 ±1.0 VCC+0.5 12.5 0.45 Unit
Notes: current listed includes both operating current frequency dependent component MHz). frequency component typically mA/MHz, with VIH. active while Embedded Algorithm (program erase) progress.
MBM29F040A -70/-90/-12
CMOS Compatible Parameter Symbol ILIT ICC1 ICC2 ICC3 VOH1 Output High Voltage Level VOH2 VLKO Lock-out Voltage Parameter Description Input Leakage Current Output Leakage Current Inputs Leakage Current Active Current (Note Active Current (Note Standby Current Input Level Input High Level Voltage Autoselect Sector Protection (A9, Output Voltage Level 12.0 Min. -2.5 Min. -100 Min. Test Condition VCC, Max. VOUT VCC, Max. Max., 12.0 VIL, VIL, Max., VCC±0.3 Min. -0.5 11.5 VCC-0.4 Max. ±1.0 ±1.0 VCC+0.3 12.5 0.45 Unit
Notes: current listed includes both operating current frequency dependent component MHz). frequency component typically mA/MHz, with VIH. active while Embedded Algorithm (program erase) progress.
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CHARACTERISTICS
Read Only Operations Characteristics Parameter Symbol JEDEC Standard tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tACC Read Cycle Time Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High-Z Output Enable Output High-Z Output Hold Time From Addresses, Whichever Occurs First Min.
Description
Test Setup
Unit (Note (Note (Note
Max.
Max.
Max. Max. Max. Min.
Notes: Test Conditions: Output Load: gate Input rise fall times: Input pulse levels: Timing measurement reference level Input: Output:
Test Conditions: Output Load: gate Input rise fall times: Input pulse levels: 0.45 Timing measurement reference level Input: Output:
IN3064 Equivalent Device Under Test Diodes IN3064 Equivalent
Note: -70: including capacitance others: including capacitance
Figure Test Conditions
MBM29F040A -70/-90/-12
Write/Erase/Program Operations Alternate Controlled Writes Parameter Symbol Description JEDEC Standard tAVAV tAVWL tWLAX tDVWH tWHDX tOES Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle Data Polling Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Typ. tWHWH2 tWHWH2 Sector Erase Operation (Note Max. tVCS tVLHT tWPP tOESP tCSP Setup Time Voltage Transition Time (Note Write Pulse Width (Note Setup Time Active (Note Setup Time Active (Note Min. Min. Min. Min. Min. Unit
tOEH
tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1
tGHWL tWPH tWHWH1
Read Recover Time Before Write Setup Time Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation
Notes: This does include preprogramming time. This timing Sector Protection operation.
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Write/Erase/Program Operations Alternate Controlled Writes Parameter Symbol JEDEC Standard tAVAV tAVEL tELAX tDVEH tEHDX tOES Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle Data Polling Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Typ. tWHWH2 tWHWH2 Sector Erase Operation (Note) Max. tVCS Setup Time Min. Description Unit
tOEH
tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1
tGHEL tCPH tWHWH1
Read Recover Time Before Write Setup Time Hold Time Pulse Width Pulse Width High Byte Programming Operation
Note: This does include preprogramming time.
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SWITCHING WAVEFORMS
Switching Waveforms
WAVEFORM INPUTS Must Steady Change from Change from Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing State Unknown Center Line HighImpedance "Off" State
Addresses
tACC
Addresses Stable
Outputs
High-Z
Output Valid
High-Z
Figure Waveforms Read Operations
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Cycle Addresses
5555H
Data Polling
tGHWL
tWHWH1
tWPH
Data
Notes: address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence.
Figure Alternate Controlled Program Operation Timings
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Cycle
Data Polling
Addresses
5555H
tGHEL
tWHWH1
tCPH
Data
Notes: address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence.
Figure Alternate Controlled Program Operation Timings
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Addresses
5555H
2AAAH
5555H
5555H
2AAAH
tGHWL
tWPH
Data
10H/30H
tVCS
Note: sector address Sector Erase. Addresses 5555H Chip Erase
Figure Waveforms Chip/Sector Erase Operations
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tOEH
Valid Data High-Z
tWHWH1 DQ6=Invalid
Valid Data (The device completed Embedded operation).
Valid Data
High-Z
Figure Waveforms Data Polling during Embedded Algorithm Operations
tOEH
tOES
Data
Toggle
Toggle
Stop Toggling
Valid
stops toggling (The device completed Embedded operation).
Figure Waveforms Toggle during Embedded Algorithm Operations
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tVLHT
tVLHT tWPP VLHT
tOESP
tCSP
Data
SAX: Sector Address initial sector SAY: Sector Address next sector
Figure Waveforms Sector Protection
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EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (See Below)
Data Polling Device
Increment Address
Last Address
Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
Figure Embedded Programming Algorithm
Table Embedded Programming Algorithm Operation Standby* Write Read Standby* Program Valid Address/Data Sequence Data Polling Verify Programming Compare Data Output Data Expected Command Sequence Comment
Device either powered-down, erase inhibit program inhibit.
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EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence (See Below) Data Polling Toggle Successfully Completed
Erasure Completed Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 5555H/AAH
Chip Erase Command Sequence (Address/Command): 5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
Sector Address/30H
Additional sector erase commands optional.
Sector Address/30H
Figure Embedded Erase Algorithm
Table Embedded Erase Algorithm Operation Standby* Write Read Standby* Erase Data Polling Verify Erasure Compare Output Command Sequence Comment
Device either powered-down, erase inhibit program inhibit.
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Start
Read Byte Addr
Byte address programming sector addresses within sector being erased during sector erase operation.
Data? Read Byte Addr
sector addresses within sector being protected during chip erase operation.
Data? Fail
Pass
Note: rechecked even because change simultaneously with DQ5.
Figure Data Polling Algorithm
MBM29F040A -70/-90/-12
Start
Read Byte Addr
Toggle Read Byte Addr
Byte address programming sector addresses within sector being erased during sector erase operation. XXXXH during chip erase sector addresses within sector being protected during chip erase operation.
Toggle Fail
Pass
Note: rechecked even because stop toggling same time changing
Figure Toggle Algorithm
MBM29F040A -70/-90/-12
Start
Sector Addr
PLSCNT
Activate Pulse
Increment PLSCNT
Time
should remain
Read from Sector Addr PLSCNT Remove from Write Reset Command Data 01H? Protect Another Sector? Device Failed Remove from Write Reset Command
Sector Protection Completed
Figure Sector Protection Algorithm
MBM29F040A -70/-90/-12
ERASE PROGRAMMING PERFORMANCE
Limit Parameter Min. Sector Erase Time Typ. Max. Excludes programming prior erasure Excludes system-level overhead Excludes system-level overhead Unit Comment
Byte Programming Time
1000
Chip Programming Time Erase/Program Cycle
100,000
1,000,000
Cycles
TSOP CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance VOUT Test Setup Typ. Max. Unit
Note: Test conditions
PLCC CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance VOUT Test Setup Typ. Max. Unit
Note: Test conditions
MBM29F040A -70/-90/-12
PACKAGE DIMENSIONS
(Suffix: Plastic LCC, 12.37±0.13 (LCC-32P-M02)
(.487±.005) 11.43±0.08 (.450±.003)
3.40±0.16 (.134±.006) 2.25±0.38 (.089±.015) 0.64(.025)
7.62(.300)REF 1.27±0.13 (.050±.005)
INDEX 13.97±0.08 14.94±0.13 (.550±.003) (.588±.005) 12.95±0.51 (.510±.020) 10.16(.400)
R0.95(.037)
0.66(.026) 0.20 -0.02 +.002 .008 -.001 0.43(.017) 10.41±0.51 (.410±.020)
+0.05
0.10(.004)
1994 FUJITSU LIMITED C32021S-2C-4
Dimensions (inches)
(Suffix: PFTN Assembly: Malaysia) Plastic TSOP, (FPT-32P-M24)
*Resin protrusion Each side 0.15 (.006) MAX.
LEAD
Details part 0.15(.006) 0.35(.014)
INDEX
0.15(.006)
0.25(.010)
0.15±0.05 (.006±.002) 20.00±0.20 (.787±.008) 18.40±0.20 (.724±.008) 0.50(.0197) 0.50±0.10 (.020±.004) 8.00±0.20 (.315±.008)
0.05(.002)MIN (STAND OFF) 1.10 -0.05 .043 -.002
+0.10 +.004
(MOUNTING HEIGHT)
0.10(.004) 19.00±0.20 (.748±.008)
7.50(.295) REF. 0.20±0.10 (.008±.004)
0.10(.004)
1994 FUJITSU LIMITED F32035S-2C-1
Dimensions (inches)
MBM29F040A -70/-90/-12
(Suffix: PFTR Assembly: Malaysia) Plastic TSOP, (FPT-32P-M25)
*Resin protrusion Each side 0.15 (.006) MAX.
LEAD
Details part 0.15(.006) 0.35(.014)
INDEX
0.15(.006)
0.25(.010)
0.20±0.10 (.008±.004) 0.15±0.05 (.006±.002) 19.00±0.20 (.748±.008) 0.10(.004) 0.50±0.10 (.020±.004) 0.50(.0197) 7.50(.295) REF.
0.10(.004)
0.05(.002)MIN (STAND OFF)
18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008)
1.10 -0.05 .043 -.002 8.00±0.20 (.315±.008)
+0.10
+.004
(MOUNTING HEIGHT)
1994 FUJITSU LIMITED F32036S-2C-1
Dimensions (inches)
MBM29F040A -70/-90/-12
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED Bras Basah Road, Plaza Park, #06-04 #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609
Rights Reserved. Circuit diagrams utilizing Fujitsu products included means illustrating typical semiconductor applications. Complete Information sufficient construction purposes necessarily given. information contained this document been carefully checked believed reliable. However, Fujitsu assumes responsibility inaccuracies. information contained this document does convey license under copyrights, patent rights trademarks claimed owned Fujitsu. Fujitsu reserves right change products specifications without notice. part this publication copied reproduced form means, transferred third party without prior written consent Fujitsu.
P9604 FUJITSU LIMITED Printed Japan

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