Input Output Architecture 28F400BX-T 28F400BX-B High Performance High
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4-MBIT (256K 512K BOOT BLOCK FLASH MEMORY FAMIL28F400BX-T 28F004BX-T
Input Output Architecture 28F400BX-T 28F400BX-B High Performance High Integration 16-bit 32-bit CPUs x8-only Input Output Architecture 28F004BX-T 28F004BX-B Space Constrained 8-bit Applications Upgradeable Intel's Smart Voltage Products Optimized High-Density Blocked Architecture 16-KB Protected Boot Block 8-KB Parameter Blocks 96-KB Main Block Three 128-KB Main Blocks Bottom Boot Locations Extended Cycling Capability Block Erase Cycles Automated Word Byte Write Block Erase Command User Interface Status Registers Erase Suspend Capability SRAM-Compatible Write Interface Automatic Power Savings Feature Typical Active Current Static Operation
Very High-Performance Read Maximum Access Time Maximum Output Enable Time Power Consumption Typical Active Read Current Reset Deep Power-Down Input Typical Acts Reset Boot Operations Extended Temperature Operation Write Protection Boot Block Hardware Data Protection Feature Erase Write Lockout During Power Transitions Industry Standard Surface Mount Packaging 28F400BX JEDEC Compatible 44-Lead PSOP 56-Lead TSOP 28F004BX 40-Lead TSOP Word Byte Write Block Erase Standard Option ETOX Flash Technology Read
Other brands names property their respective owners Information this document provided connection with Intel products Intel assumes liability whatsoever including infringement patent copyright sale Intel products except provided Intel's Terms Conditions Sale such products Intel retains right make changes these specifications time without notice Microcomputer Products have minor variations this specification known errata
COPYRIGHT
INTEL CORPORATION 1995
November 1995
Order Number 290451-005
28F400BX-T 28F004BX-T
Intel's 4-Mbit Flash Memory Family extension Boot Block Architecture which includes block-selective erasure automated write erase operations standard microprocessor interface 4-Mbit Flash Memory Family enhances Boot Block Architecture adding more density blocks input output control very high speed power industry standard compatible pinout surface mount packaging 4-Mbit flash family easy upgrade from Intel's 2-Mbit Boot Block Flash Memory Family Intel 28F400BX-T 16-bit wide flash memory offerings These high density flash memories provide user selectable operation either 8-bit 16-bit applications 28F400BX-T 28F400BX-B 304-bit non-volatile memories organized either bytes words information They offered 44-Lead plastic 56-Lead TSOP packages pinout conforms industry standard EPROM pinout Intel 28F004BX-T 8-bit wide flash memories with bits organized bytes information They offered 40-Lead TSOP package which ideal space-constrained portable systems These devices integrated Command User Interface (CUI) Write State Machine (WSM) simplified word byte write block erasure 28F400BX-T 28F004BX-T provide block locations compatible with Intel's MCS-186 family 80286 i386 i486 i860 80960CA microprocessors 28F400BX-B 28F004BX-B provide compatibility with Intel's 80960KX 80960SX families well other embedded microprocessors boot block includes data protection feature protect boot code critical applications With maximum access time these 4-Mbit flash devices very high performance memories which interface zero-wait-state wide range microprocessors microcontrollers deep power-down mode lowers total power consumption This critical handheld battery powered systems very power applications using supply refer Intel 28F400BL-T 28F004BL-T 4-Mbit Boot Block Flash Memory Family datasheet Manufactured Intel's micron ETOX process 4-Mbit flash memory family provides world class quality reliability cost-effectiveness 4-Mbit density level
28F400BX-T 28F004BX-T
Follow these guidelines ensure compatibility Connect SmartVoltage products) control signal adding switch write protection switch complete write protection Allow connecting disconnect from line desired
PRODUCT FAMILY OVERVIEW
Throughout this datasheet 28F400BX refers both 28F400BX-T 28F400BX-B devices 28F004BX refers both 28F004BX-T 28F004BX-B devices 4-Mbit flash memory family refers both 28F400BX 28F004BX products This datasheet comprises specifications four separate products 4-Mbit flash memory family Section provides overview 4-Mbit flash memory family including applications pinouts descriptions Sections describe detail specific memory organizations 28F400BX 28F004BX products respectively Section combines description family's principles operations Finally Section describes family's operating specifications Product Family Products 28F400BX-T 28F400BX-B X8-Only Products 28F004BX-T 28F004BX-B
Main Features
28F400BX 28F004BX boot block flash memory family very high performance 4-Mbit bit) memory family organized either KWords (262 words) bits each Kbytes (524 bytes) bits each Seven Separately Erasable Blocks including Hardware-Lockable boot block Bytes) parameter blocks Bytes each) Four main blocks block Bytes blocks Bytes) included 4-Mbit family erase operation erases main blocks typically seconds boot parameter blocks typically seconds independent remaining blocks Each block independently erased programmed times Boot Block located either (28F400BX-T 28F004BX-T) bottom (28F400BX-B 28F004BX-B) address order accommodate different microprocessor protocols boot code location hardware lockable boot block provides most secure code storage boot block intended store kernel code required booting-up system When between boot block unlocked program erase operations performed When below boot block locked program erase operations boot block ignored 28F400BX products available EPROM compatible pinout housed 44-Lead PSOP (Plastic Small Outline) package 56-Lead TSOP (Thin Small Outline thick) package shown Figures 28F004BX products available 40-Lead TSOP thick) package shown Figure Command User Interface (CUI) serves interface between microprocessor microcontroller internal operation 28F400BX 28F004BX flash memory products
Designing Upgrade SmartVoltage Products
Today's high volume boot block products upgradable Intel's SmartVoltage boot block products that provide program erase operation read operation Intel's SmartVoltage boot block products provide following enhancements boot block products described this data sheet replaced provide means lock unlock boot block with logic signals Program Erase operation uses proven program erase techniques with applied Enhanced circuits optimize performance Refer Mbit SmartVoltage Boot Block Flash Memory Data Sheets complete specifications When design with boot block products should provide capability your board design upgrade SmartVoltage products
28F400BX-T 28F004BX-T
Program Erase Automation allows program erase operations executed using twowrite command sequence internal Write State Machine (WSM) automatically executes algorithms timings necessary program erase operations including verifications thereby unburdening microprocessor microcontroller Writing memory data performed word byte increments 28F400BX family byte increments 28F004BX family typically within which 100% improvement over current flash memory products Status Register (SR) indicates status whether successfully completed desired program erase operation Maximum Access Time (tACC) achieved over commercial temperature range supply voltage range 25V) output load Maximum Access Time (tACC) achieved over commercial temperature range supply range output load maximum Program current operation operation Erase current maximum erase programming voltage (VPP under operating conditions option also vary between (VPP 10%) with guaranteed number block erase cycles Typical Active Current achieved products (28F400BX) Typical Active Current achieved products (28F400BX 28F004BX) Refer active current derating curves this datasheet 4-Mbit boot block flash memory family also designed with Automatic Power Savings (APS) feature minimize system battery current drain allows very power designs Once device accessed read array data mode will immediately memory static mode operation where active current typically until next read initiated When pins BYTE (28F400BX-only) either CMOS Standby mode enabled where typically Deep Power-Down Mode enabled when ground minimizing power consumption providing write protection during power-up conditions current during deep power-down mode typical initial maximum access time Reset Time required from switching until outputs valid Equivalently device maximum wake-up time until writes Command User Interface recognized When ground reset Status Register cleared entire device protected from being written This feature prevents data corruption protects code stored device during system reset system Reset tied reset memory normal read mode upon activation Reset With on-chip program erase automation 4-Mbit family functionality data protection when reset even program erase command issued device will recognize operation until returns normal state 28F400BX Byte-wide Word-wide Input Output Control possible controlling BYTE When BYTE logic device byte-wide mode (x8) data read written through During bytewide mode tri-stated DQ15 becomes lowest order address When BYTE logic high device word-wide mode (x16) data read written through
28F400BX-T 28F004BX-T
This increase software sophistication augments probability that code update will required after shipped 4-Mbit flash memory products provide inexpensive update solution notebook handheld personal computers while extending their product lifetime Furthermore 4-Mbit flash memory products' power-down mode provides added flexibility these batteryoperated portable designs which require operation very power levels 4-Mbit flash memory products also provide excellent design solutions Digital Cellular Phone Telecommunication switching applications requiring high performance high density storage capability coupled with modular software designs small form factor package (X8-only bus) 4-Mbit's blocking scheme allows easy segmentation embedded code with Kbytes Hardware-Protected Boot code Main Blocks program code Parameter Blocks Kbytes each frequently updatable data storage diagnostic messages phone numbers authorization codes) Figure example such application with 28F004BX-T These actual examples wide range applications 4-Mbit Boot Block flash memory family which enable system designers achieve best possible product design Only your imagination limits applicability such versatile product family
Applications
4-Mbit boot block flash memory family combines high density high performance cost-effective flash memories with blocking hardware protection capabilities flexibility versatility will reduce costs throughout product life cycle Flash memory ideal Just-In-Time production flow reducing system inventory costs eliminating component handling during production phase During product life cycle when code updates feature enhancements become necessary flash memory will reduce update costs allowing either user-performed code change floppy disk remote code change serial link 4-Mbit boot block flash memory family provides full function blocked flash memories suitable wide range applications These applications include Extended BIOS ROM-able applications storage Digital Cellular Phone program data storage Telecommunication boot firmware Printer firmware font storage various other embedded applications where both program data storage required Reprogrammable systems such personal computers ideal applications 4-Mbit flash memory products Portable handheld personal computer applications becoming more complex with addition power management software take advantage latest microprocessor technology availability ROM-based application software tablet code electronic hand writing diagnostic code Figure shows example 28F400BX-T application
28F400BX-T 28F004BX-T
290451
Figure 28F400BX Interface Intel386 Embedded Processor
290451
Figure 28F004BX Interface INTEL 80C188EB 8-Bit Embedded Processor
28F400BX-T 28F004BX-T
28F004BX 40-Lead TSOP pinout shown Figure 100% compatible provides density upgrade 2-Mbit Boot Block flash memory 28F002BX
Pinouts
28F400BX 44-Lead PSOP pinout follows industry standard EPROM pinout shown Figure Furthermore 28F400BX 56-Lead TSOP pinout shown Figure provides density upgrades future higher density boot block memories
290451
Figure PSOP Lead Configuration 28F400BX
28F400BX-T 28F004BX-T
290451
Figure TSOP Lead Configuration 28F400BX
290451
Figure TSOP Lead Configuration 28F004BX
28F400BX-T 28F004BX-T
28F400BX Descriptions
Symbol -A17 Type Name Function ADDRESS INPUTS memory addresses Addresses internally latched during write cycle ADDRESS INPUT When signature mode accessed During this mode decodes between manufacturer device ID's When BYTE logic only lower byte signatures read DQ15 don't care signature mode when BYTE DATA INPUTS OUTPUTS Inputs array data second cycle during program command Inputs commands command user interface when active Data internally latched during write program cycles Outputs array Intelligent Identifier Status Register data data pins float tri-state when chip deselected outputs disabled DATA INPUTS OUTPUTS Inputs array data second cycle during program command Data internally latched during write program cycles Outputs array data data pins float tri-state when chip deselected outputs disabled byte-wide mode (BYTE ``0'') byte-wide mode DQ15 becomes lowest order address data output DQ0-DQ7 CHIP ENABLE Activates device's control logic input buffers decoders sense amplifiers active high deselects memory device reduces power consumption standby levels high CMOS high level standby current will increase current flow through input stages RESET DEEP POWER-DOWN Provides three-state control Puts device deep powerdown mode Locks boot block from program erase When logic high level equals maximum boot block locked cannot programmed erased When minimum boot block unlocked programmed erased When logic level boot block locked deep power-down mode enabled reset preventing blocks from being programmed erased therefore providing data protection during power transitions When transitions from logic logic high flash memory enters read-array mode OUTPUT ENABLE Gates device's outputs through data buffers during read cycle active WRITE ENABLE Controls writes Command Register array blocks Addresses data latched rising edge pulse active
-DQ7
-DQ15
BYTE
BYTE ENABLE Controls whether device operates byte-wide mode (x8) word-wide mode (x16) BYTE must controlled CMOS levels meet 100A CMOS current standby mode BYTE ``0'' enables byte-wide mode where data read programmed DQ0-DQ7 DQ15 becomes lowest order address that decodes between upper lower byte -DQ14 tri-stated during byte-wide mode BYTE ``1'' enables word-wide mode where data read programmed -DQ15 PROGRAM ERASE POWER SUPPLY erasing memory array blocks programming data each block
Note VPPLMAX memory contents cannot altered
DEVICE POWER SUPPLY GROUND internal circuitry CONNECT driven left floating DON'T should connected anything
28F400BX-T 28F004BX-T
28F004BX Descriptions
Symbol -A18 -DQ7 Type Name Function ADDRESS INPUTS memory addresses Addresses internally latched during write cycle ADDRESS INPUT When signature mode accessed During this mode decodes between manufacturer device ID's DATA INPUTS OUTPUTS Inputs array data second cycle during program command Inputs commands command user interface when active Data internally latched during write program cycles Outputs array Intelligent Identifier status register data data pins float tri-state when chip deselected outputs disabled CHIP ENABLE Activates device's control logic input buffers decoders sense amplifiers active high deselects memory device reduces power consumption standby levels high CMOS high level standby current will increase current flow through input stages RESET DEEP POWERDOWN Provides Three-State control Puts device deep power-down mode Locks Boot Block from program erase When logic high level equals maximum Boot Block locked cannot programmed erased When minimum Boot Block unlocked programmed erased When logic level Boot Block locked deep power-down mode enabled reset preventing blocks from being programmed erased therefore providing data protection during power transitions When transitions from logic logic high flash memory enters read-array mode OUTPUT ENABLE Gates device's outputs through data buffers during read cycle active WRITE ENABLE Controls writes Command Register array blocks active Addresses data latched rising edge pulse PROGRAM ERASE POWER SUPPLY erasing memory array blocks programming data each block
NOTE VPPLMAX memory contents cannot altered
DEVICE POWER SUPPLY GROUND internal circuitry CONNECT driven left floating DON'T should connected anything
28F400BX-T 28F004BX-T
28F400BX WORD BYTE-WIDE PRODUCTS DESCRIPTION
290451-
Figure 28F400BX Word Byte Block Diagram
28F400BX-T 28F004BX-T
28F400BX Memory Organization
BLOCKING 28F400BX uses blocked array architecture provide independent erasure memory blocks block erased independently other blocks array when address given within block address range Erase Setup Erase Confirm commands written 28F400BX random read write memory only erasure performed block Boot Block Operation Data Protection 16-Kbyte boot block provides lock feature secure code storage intent boot block provide secure storage area kernel code that required boot system event power failure other disruption during code update This lock feature ensures absolute data integrity preventing boot block from being written erased when boot block erased written when held duration erase program operation This allows customers change boot code when necessary while providing security when needed Block Memory section address locations boot block 28F400BX-T 28F400BX-B Parameter Block Operation
BLOCK MEMORY versions 28F400BX product exist support different memory maps array blocks order accommodate different microprocessor protocols boot code location 28F400BX-T memory inverted from 28F400BX-B memory 28F400BX-B Memory 28F400BX-B device 16-Kbyte boot block located from 00000H 01FFFH accommodate those microprocessors that boot from bottom address 00000H 28F400BX-B first 8-Kbyte parameter block resides memory space from 02000H 02FFFH second 8-Kbyte parameter block resides memory space from 03000H 03FFFH 96-Kbyte main block resides memory space from 04000H 0FFFFH three 128-Kbyte main block resides memory space from 10000H 1FFFFH 20000H 2FFFFH 30000H 3FFFFH (word locations) Figure
(Word Addresses) 3FFFFH
128-Kbyte MAIN BLOCK 30000H 2FFFFH 128-Kbyte MAIN BLOCK
28F400BX parameter blocks (8-Kbytes each) parameter blocks intended provide storage frequently updated system parameters configuration diagnostic information parameter blocks also used store additional boot main code parameter blocks however have hardware write protection feature that boot block parameter blocks provide more efficient memory utilization when dealing with parameter changes versus regularly blocked devices Block Memory section address locations parameter blocks 28F400BX-T 28F400BX-B Main Block Operation Four main blocks memory exist 28F400BX 128-Kbyte blocks 96-Kbyte blocks) following section Block Memory address location these blocks 28F400BX-T 28F400BX-B products
20000H 1FFFFH 128-Kbyte MAIN BLOCK 10000H 0FFFFH 96-Kbyte MAIN BLOCK 04000H 03FFFH 03000H 02FFFH 02000H 01FFFH 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK 00000H
Figure 28F400BX-B Memory
28F400BX-T 28F004BX-T
28F400BX-T Memory 28F400BX-T device 16-Kbyte boot block located from 3E000H 3FFFFH accommodate those microprocessors that boot from address 28F400BX-T first 8-Kbyte parameter block resides memory space from 3D000H 3DFFFH second 8-Kbyte parameter block resides memory space from 3C000H 3CFFFH 96-Kbyte main block resides memory space from 30000H 3BFFFH three 128-Kbyte main blocks reside memory space from 20000H 2FFFFH 10000H 1FFFFH 00000H 0FFFFH shown below Figure
(Word Addresses) 3FFFFH 16-Kbyte BOOT BLOCK 3E000H 3DFFFH 3D000H 3CFFFH 3C000H 3BFFFH 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK 30000H 2FFFFH 128-Kbyte MAIN BLOCK 20000H 1FFFFH 128-Kbyte MAIN BLOCK 10000H 0FFFFH 128-Kbyte MAIN BLOCK
00000H
Figure 28F400BX-T Memory
28F400BX-T 28F004BX-T
28F004BX PRODUCT DESCRIPTION
290451-
Figure 28F004BX Byte-Wide Block Diagram
28F400BX-T 28F004BX-T
28F004BX Memory Organization
BLOCKING 28F004BX uses blocked array architecture provide independent erasure memory blocks block erased independently other blocks array when address given within block address range Erase Setup Erase Confirm commands written 28F004BX random read write memory only erasure performed block Boot Block Operation Data Protection 16-Kbyte boot block provides lock feature secure code storage intent boot block provide secure storage area kernel code that required boot system event power failure other disruption during code update This lock feature ensures absolute data integrity preventing boot block from being programmed erased when boot block erased programmed when held duration erase program operation This allows customers change boot code when necessary while still providing security when needed Block Memory section address locations boot block 28F004BX-T 28F004BX-B Parameter Block Operation 28F004BX parameter blocks (8-Kbytes each) parameter blocks intended provide storage frequently updated system parameters configuration diagnostic information parameter blocks also used store additional boot main code parameter blocks however have hardware write protection feature that boot block Parameter blocks provide more efficient memory utilization when dealing with small parameter changes versus regularly blocked devices Block Memory section address locations parameter blocks 28F004BX-T 28F004BX-B Main Block Operation
BLOCK MEMORY versions 28F004BX product exist support different memory maps array blocks order accommodate different microprocessor protocols boot code location 28F004BX-T memory inverted from 28F004BX-B memory 28F004BX-B Memory 28F004BX-B device 16-Kbyte boot block located from 00000H 03FFFH accommodate those microprocessors that boot from bottom address 00000H 28F004BX-B first 8-Kbyte parameter block resides memory from 04000H 05FFFH second 8-Kbyte parameter block resides memory space from 06000H 07FFFH 96-Kbyte main block resides memory space from 08000H 1FFFFH three 128-Kbyte main block reside memory space from 20000H 3FFFFH 40000H 5FFFFH 60000H 7FFFFH Figure
7FFFFH
128-Kbyte MAIN BLOCK 60000H 5FFFFH 128-Kbyte MAIN BLOCK 40000H 3FFFFH 128-Kbyte MAIN BLOCK 20000H 1FFFFH 96-Kbyte MAIN BLOCK 08000H 07FFFH 06000H 05FFFH 04000H 03FFFH 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK 00000H
Four main blocks memory exist 28F004BX 128-Kbyte blocks 96-Kbyte blocks) following section Block Memory address location these blocks 28F004BX-T 28F004BX-B
Figure 28F004BX-B Memory
28F400BX-T 28F004BX-T
28F004BX-T Memory 28F004BX-T device 16-Kbyte boot block located from 7C000H 7FFFFH accommodate those microprocessors that boot from address 28F004BX-T first 8-Kbyte parameter block resides memory space from 7A000H 7BFFFH second 8-Kbyte parameter block resides memory space from 78000H 79FFFH 96-Kbyte main block resides memory space from 60000H 77FFFH three 128-Kbyte main blocks reside memory space from 40000H 5FFFFH 20000H 3FFFFH 00000H 1FFFFH
PRODUCT FAMILY PRINCIPLES OPERATION
Flash memory augments EPROM functionality with in-circuit electrical write erase 4-Mbit flash family utilizes Command User Interface (CUI) internally generated timed algorithms simplify write erase operations allows 100% TTL-level control inputs fixed power supplies during erasure programming maximum EPROM compatibility absence high voltage 4-Mbit boot block flash family will only successfully execute following commands Read Array Read Status Register Clear Status Register Intelligent Identifier mode device provides standard EPROM read standby output disable operations Manufacturer Identification Device Identification data accessed through through standard EPROM high voltage access (VID) PROM programming equipment same EPROM read standby output disable functions available when high voltage applied addition high voltage allows write erase device functions associated with altering memory contents write erase Intelligent Identifier read Read Status accessed purpose Write State Machine (WSM) completely automate write erasure device will begin operation upon receipt signal from will report status back through Status Register will handle interface data address latches well system software requests status while operation
7FFFFH 16-Kbyte BOOT BLOCK 7C000H 7BFFFH 7A000H 79FFFH 78000H 77FFFH 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK 60000H 5FFFFH 128-Kbyte MAIN BLOCK 40000H 3FFFFH 128-Kbyte MAIN BLOCK 20000H 1FFFFH 128-Kbyte MAIN BLOCK
00000H
28F400BX Operations
Flash memory reads erases writes in-system local cycles from flash memory conform standard microprocessor cycles
Figure 28F004BX-T Memory
28F400BX-T 28F004BX-T
Table Operations WORD-WIDE Mode (BYTE Mode Read Output Disable Standby Deep Power-Down Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write Notes
VIH)
DQ0-15 DOUT High High High 0089H 4470H 4471H
Table Operations BYTE-WIDE Mode (BYTE Mode Read Output Disable Standby Deep Power-Down Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write Notes
VIL)
DQ0-7 DOUT High High High
DQ8-14 High High High High High High High
NOTES Refer Characteristics control pins addresses VPPL VPPH Characteristics VPPL VPPH voltages Manufacturer Device codes also accessed write sequence -A17 Device 4470H 28F400BX-T 4471H 28F400BX-B Refer Table valid during write operation Command writes Block Erase Word Byte Write only executed when VPPH write erase boot block hold must meet maximum deep power-down current
28F400BX-T 28F004BX-T
28F004BX Operations
Table Operations Mode Read Output Disable Standby Deep Power-Down Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write Notes DQ0-7 DOUT High High High
NOTES Refer Characteristics control pins addresses VPPL VPPH Characteristics VPPL VPPH voltages Manufacturer Device codes also accessed write sequence -A18 Device 28F004BX-T 28F004BX-B Refer Table valid during write operation Command writes Block erase byte program only executed when VPPH Program erase Boot block holding must meet maximum deep power-down current
Read Operations
4-Mbit boot block flash family three user read modes Array Intelligent Identifier Status Register Status Register read mode will discussed detail ``Write Operations'' section During power-up conditions (VCC supply ramping) takes maximum from when minimum valid data outputs READ ARRAY memory Read Array mode necessary write appropriate read mode command 4-Mbit boot block flash family three control functions which must logically active obtain data outputs Chip-Enable device selection control Power-Down device power control Output-Enable DATA INPUT OUTPUT direction control when active used drive data from selected memory Output Control With logic-high level (VIH) output from device disabled data input output pins tri-stated Data input then controlled
Input Control With logic-high level (VIH) input device disabled Data Input Output pins controlled INTELLIGENT IDENTIFIERS 28F400BX PRODUCTS manufacturer device codes read taking Writing places device into Intelligent Identifier read mode read location 00000H outputs manufacturer's identification code 0089H location 00001H outputs device code 4470H 28F400BX-T 4471H 28F400BX-B When BYTE logic only lower byte above signatures read DQ15 ``don't care'' during Intelligent Identifier mode read array command must written memory return read array mode 28F004BX PRODUCTS manufacturer device codes also read taking Writing places device into Intelligent Identifier read mode read location 00000H outputs manufacturer's identification code location 00001H outputs device code 28F004BX-T 28F004BX-B
28F400BX-T 28F004BX-T
However when program erase operation boot block attempted corresponding status register (Bit Program Erase refer Table Status Register Definitions) indicate failure complete operation COMMAND USER INTERFACE (CUI) Command User Interface (CUI) serves interface microprocessor points read write path appropriate circuit block described previous section After completed task will Status ``1'' which will also allow respond full command Note that after returned control will remain current state Command Command Codes Device Mode Invalid Reserved Alternate Program Setup Erase Setup Program Setup Clear Status Register Read Status Register Intelligent Identifier Erase Suspend Erase Resume Erase Confirm Read Array
Write Operations
Commands written using standard microprocessor write timings serves interface between microprocessor internal chip operation decipher Read Array Read Intelligent Identifier Read Status Register Clear Status Register Erase Program commands event read command simply points read path either array Intelligent Identifier status register depending specific read command given program erase cycle informs write state machine that write erase been requested During program cycle Write State Machine will control program sequences will only respond status reads Durlng erase cycle will respond status reads erase suspend After Write State Machine completed task will allow respond full command will stay current command state until microprocessor issues another command will successfully initiate erase write operation only when within voltage range Depending upon application system designer choose make power supply switchable available only when memory updates desired system designer also choose ``hard-wire'' 4-Mbit boot block flash family designed accommodate either design practice recommended that tied logical Reset data protection during unstable reset function described ``Product Family Overview'' section BOOT BLOCK WRITE OPERATIONS case Boot Block modifications (write erase) typically addition high voltage
Command Function Descriptions Device operations selected writing specific commands into Table defines 4-Mbit boot block flash family commands
28F400BX-T 28F004BX-T
Table Command Definitions Command Read Array Intelligent Identifier Read Status Register Clear Status Register Erase Setup Erase Confirm Word Byte Write Setup Write Erase Suspend Erase Resume Alternate Word Byte Write Setup Write Notes First Cycle Second Cycle Cycles Req'd Operation Address Data Operation Address Data Write Write Write Write Write Write Write Write Write Write Write Write Read Read
NOTES operations defined Tables Identifier Address manufacturer code device code Data read from Status Register Intelligent Identifier Data Following Intelligent Identifier Command read operations access manufacturer device codes Address within block being erased Address written Data written location Either commands valid When writing commands device upper data -DQ15 (28F400BX-only) which either avoid burning additional current
Invalid Reserved These unassigned commands recommended that customer command other than valid commands specified above Intel reserves right redefine these codes future functions Read Array (FFH) This single write command points read path array host performs controlled read immediately following two-write sequence that started then device will output status register contents Read Array command given after Erase Setup device reset read array Read Array command sequence (FFH) required reset Read Array after Program Setup Intelligent Identifier (90H) After this command executed points output path Intelligent Identifier circuits Only Intelligent Identifier values addresses read (only address used this mode other address inputs ignored)
Read Status Register (70H) This commands that executable while state machine operating After this command written read device will output contents status register regardless address presented device device automatically enters this mode after program erase completed Clear Status Register (50H) only Program Status Erase Status bits status register clear them reasons exist operating status register this fashion first synchronization does know when host read status register therefore would know when clear status bits Secondly programming string bytes more efficient query status register after programming string Thus errors exist while programming string status register will return accumulated error status
28F400BX-T 28F004BX-T
will control pins with exclusion immediately shut down remainder chip During suspend operation data address latches will remain closed address pads able drive address into read path Erase Resume (D0H) This command will cause clear Suspend state Status ``0'' only Erase Suspend command previously issued Erase Resume will have effect other conditions STATUS REGISTER 4-Mbit boot block flash family contains status register which read determine when program erase operation complete whether that operation completed successfully status register read time writing Read Status command After writing this command subsequent Read operations output data from status register until another command written Read Array command must written return Read Array mode status register bits output whether device byte-wide (x8) wordwide (x16) mode 28F400BX word-wide mode upper byte during Read Status command byte-wide mode tri-stated DQ15 retains order address function should noted that contents status register latched falling edge whichever occurs last read cycle This prevents possible errors which might occur contents status register change while reading status register must toggled with each subsequent status read completion program erase operation will evident Status Register interface between microprocessor Write State Machine (WSM) When active this register will indicate status will also hold bits indicating whether successful performing desired operation sets status bits ``Three'' through ``Seven'' clears bits ``Six'' ``Seven'' cannot clear status bits ``Three'' through ``Five'' These bits only cleared controlling through Clear Status Register command
Program Setup (40H 10H) This command simply sets into state such that next write will load address data registers Either used Program Setup Both commands included accommodate efforts achieve industry standard command code Program second write after program setup command will latch addresses data Also initiates begin execution program algorithm While finishes algorithm device will output Status Register contents Note that cannot suspended during programming Erase Setup (20H) Prepares Erase Confirm command other action taken next command Erase Confirm command then will both Program Status Erase Status bits Status Register ``1'' place device into Read Status Register state wait another command Erase Confirm (D0H) previous command Erase Setup command then will enable erase same time closing address data latches respond only Read Status Register Erase Suspend commands While executing device will output Status Register data when toggled Status Register data only updated toggling either Erase Suspend (B0H) This command only meaning while executing Erase operation therefore will only responded during erase operation After this command been executed will output that directs suspend Erase operations then return responding only Read Status Register Erase Resume commands Once reached Suspend state will output into which allows respond Read Array Read Status Register Erase Resume commands this mode will respond other commands will also Status ``1'' will continue idling SUSPEND state regardless state input
28F400BX-T 28F004BX-T
Status Register Definition Table Status Register Definitions
WSMS VPPS
NOTES WRITE STATE MACHINE STATUS Ready Busy Write State Machine Status must first checked determine byte word program block erase completion before Program Erase Status bits checked success When Erase Suspend issued halts execution sets both WSMS bits ``1'' remains ``1'' until Erase Resume command issued When this ``1'' applied maximum number erase pulses block still unable successfully perform erase verify When this ``1'' attempted failed Program byte word
ERASE SUSPEND STATUS Erase Suspended Erase Progress Completed
ERASE STATUS Error Block Erasure Successful Block Erase PROGRAM STATUS Error Byte Word Program Successful Byte Word Program STATUS Detect Operation Abort
Status unlike converter does provide continuous indication level interrogates level only after byte write block erase command sequences have been entered informs system been switched Status guaranteed report accurate feedback between VPPL VPPH These bits reserved future should masked when polling Status Register
RESERVED FUTURE ENHANCEMENTS
Clearing Status Register Certain bits status register write state machine only reset system software These bits indicate various failure conditions allowing system software control resetting these bits several operations performed (such cumulatively programming several bytes erasing multiple blocks sequence) status register then read determine error occurred during that programming erasure series This adds flexibility device programmed erased clear status register Clear Status Register command written Then other command issued Note again that before read cycle initiated Read Array command must written specify whether read data come from array status register Intelligent Identifier
PROGRAM MODE Program executed two-write sequence Program Setup command written followed second write which specifies address data programmed write state machine will execute sequence internally timed events Program desired bits addressed memory word (byte) Verify that desired bits sufficiently programmed Programming memory results specific bits within byte word being changed ``0'' user attempts program ``1''s there will change memory cell content error occurs
28F400BX-T 28F004BX-T
Similar erasure status register indicates whether programming complete While program sequence executing status register ``0'' status register polled toggling either determine when program sequence complete Only Read Status Register command valid while programming active When programming complete status bits which indicate whether program operation successful should checked programming operation unsuccessful status register ``1'' indicate Program Failure then within acceptable limits will execute programming sequence status register should cleared before attempting next operation instruction follow after programming completed however must recognized that reads from memory status register Intelligent Identifier cannot accomplished until given appropriate command Read Array command must first given before memory contents read Figure shows system software flowchart device byte programming operation Figure shows similar flowchart device word programming operation (28F400BX-only) ERASE MODE Erasure single block initiated writing Erase Setup Erase Confirm commands along with addresses 28F400BX 28F004BX identifying block erased These addresses latched internally when Erase Confirm command issued Block erasure results bits within block being ``1'' will execute sequence internally timed events Program bits within block Verify that bits within block sufficiently programmed Erase bits within block Verify that bits within block sufficiently erased While erase sequence executing status register ``0'' When status register indicates that erasure complete status bits which indicate whether erase operation successful should checked erasure operation unsuccessful status register ``1'' indicate Erase Failure within acceptable limits after Erase Confirm command issued will execute erase sequence instead Bits status register ``1'' indicate Erase Failure ``1'' identify that supply voltage within acceptable limits status register should cleared before attempting next operation instruction follow after erasure completed however must recognized that reads from memory array status register Intelligent Identifier accomplished until given appropriate command Read Array command must first given before memory contents read Figure shows system software flowchart Block Erase operation Suspending Resuming Erase Since erase operation typically requires seconds complete Erase Suspend command provided This allows erase-sequence interruption order read data from another block memory Once erase sequence started writing Erase Suspend command requests that Write State Machine (WSM) pause erase sequence predetermined point erase algorithm status register must read determine when erase operation been suspended this point Read Array command written order read data from blocks other than that which being suspended only other valid command this time Erase Resume command Read Status Register operation Figure shows system software flowchart detailing operation
28F400BX-T 28F004BX-T
During Erase Suspend mode chip into pseudo-standby mode taking active current maximum chip enabled while this mode taking Erase Resume command issued resume erase operation Upon completion reads from block other than block being erased Erase Resume command must issued When Erase Resume command given will continue with erase sequence complete erasing block with erase status register must read cleared next instruction issued order continue
EXTENDED CYCLING Intel designed extended cycling capability into ETOX flash memory technology 4-Mbit boot block flash family designed program erase cycles each seven blocks combination electric fields clean oxide processing minimized oxide area memory cell subjected tunneling electric field results very high cycling capability
28F400BX-T 28F004BX-T
Operation Write
Command
Comments
Setup Program
Data Address Byte programmed Data programmed Address Byte programmed
Write
Program
Read
Status Register Data Toggle update Status Register
Standby
Check Ready Busy
Repeat subsequent bytes Full status check done after each byte after sequence bytes
Write after last byte programming operation reset device Read Array Mode
290451
Full Status Check Procedure
Operation Standby
Command
Comments
Check Detect
Standby
Check Byte Program Error
MUST cleared during program attempt before further attempts allowed Write State Machine
290451
only cleared Clear Status Register Command cases where multiple bytes programmed before full status checked error detected clear Status Register before attempting retry other error recovery
Figure Automated Byte Programming Flowchart
28F400BX-T 28F004BX-T
Operation Write
Command
Comments
Setup Program
Data Address Word programmed Data programmed Address Word programmed
Write
Program
Read
Status Register Data Toggle update Status Register
Standby
Check Ready Busy
Repeat subsequent words Full status check done after each word after sequence words
290451
Write after last word programming operation reset device Read Array Mode
Full Status Check Procedure
Operation Standby
Command
Comments
Check Detect
Standby
Check Word Program Error
MUST cleared during program attempt before further attempts allowed Write State Machine
290451
only cleared Clear Status Register Command cases where multiple words programmed before full status checked error detected clear Status Register before attempting retry other error recovery
Figure Automated Word Programming Flowchart
28F400BX-T 28F004BX-T
Operation Write
Command
Comments
Setup Erase
Data Address Within block erased Data Address Within block erased
Write
Erase
Read
Status Register Data Toggle update Status Register
Standby
Check Ready Busy
Repeat subsequent blocks Full status check done after each block after sequence blocks
290451
Write after last block erase operation reset device Read Array Mode
Full Status Check Procedure
Operation Standby
Command
Comments
Check Detect
Standby
Check Both Command Sequence Error Check Block Erase Error
Standby
MUST cleared during erase attempt before further attempts allowed Write State Machine
290451
only cleared Clear Status Register Command cases where multiple blocks erased before full status checked error detected clear Status Register before attempting retry other error recovery
Figure Automated Block Erase Flowchart
28F400BX-T 28F004BX-T
Operation
Command
Comments
Write
Erase Suspend
Data
Read
Status Register Data Toggle update Status Register
Standby
Check Ready
Standby
Check Suspended
Write
Read Array
Data
Read
Read array data from block other than that being erased Erase Resume Data
Write
290451
Figure Erase Suspend Resume Flowchart
Power Consumption
ACTIVE POWER With logic-low level logichigh level device placed active mode device current maximum with input signals AUTOMATIC POWER SAVINGS Automatic Power Savings (APS) pwer feature during active mode operation 4-Mbit family products incorporate Power Reduction Control (PRC) circuitry which basically allows device itself into current state when being accessed After data read from memory array logic controls device's power consumption entering mode where
maximum current typical current device stays this static state with outputs valid until location read STANDBY POWER With logic-high level (VIH) read mode memory placed standby mode where maximum standby current with CMOS input signals standby operation disables much device's circuitry substantially reduces device power consumption outputs placed high-impedance state independent status signal When 4-Mbit boot block flash family deselected during erase program functions devices will continue perform erase program function consume program erase active power until program erase completed
28F400BX-T 28F004BX-T
active Since both must command write driving either signal will inhibit writes device architecture provides added level protection since alteration memory contents only occur after successful completion two-step command sequences Finally device disabled until brought regardless state control inputs This feature provides another level memory protection
RESET DEEP POWERDOWN 4-Mbit boot block flash family supports typical deep power-down mode target markets these devices portable equipment where power consumption machine prime importance 4-Mbit boot block flash family which places device deep powerdown mode When logic-low (GND circuits turned device typically draws current During read modes going deselects memory places output drivers high impedance state Recovery from deep power-down state requires maximum access valid data (tPHQV) During erase program modes will abort either erase program operation contents memory longer valid data been corrupted function read mode above internal circuitry turned achieve current level transitions turning power device will clear status register This during system reset important with automated write erase devices When system comes reset expects read from flash memory Automated flash memories provide status information when accessed during write erase modes reset occurs with flash memory reset proper initialization would occur because flash memory would providing status information instead array data Intel's Flash Memories allow proper initialization following system reset through input this application controlled same RESET signal that resets system
Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling methods System designers interested supply current issues
Standby current levels (ICCS) Active current levels (ICCR) Transient peaks produced falling rising
edges Transient current magnitudes depend device outputs' capacitive inductive loading Two-line control proper decoupling capacitor selection will suppress these transient voltage peaks Each flash device should have ceramic capacitor connected between each between These high frequency lowinherent inductance capacitors should placed close possible package leads TRACE PRINTED CIRCUIT BOARDS Writing flash memories while they reside target system requires special consideration power supply trace printed circuit board designer supplies flash memory cells current programming erasing should similar trace widths layout considerations given power supply trace Adequate supply traces decoupling will decrease spikes overshoots TRANSITIONS
Power-up Operation
4-Mbit boot block flash family designed offer protection against accidental block erasure programming during power transitions Upon powerup 4-Mbit boot block flash family indifferent which power supply powers-up first Power supply sequencing required 4-Mbit boot block flash family ensures reset read mode power-up addition power-up user must either drop present address ensure valid data outputs system designer must guard against spurious writes voltages above VLKO when
latches commands issued system software altered transitions actions state upon power-up after exit from deep power-down mode after transitions below VLKO (Lockout voltage) Read Array mode After word byte write block erase operation complete even after transitions down VPPL must reset Read Array mode Read Array command when accesses flash memory desired
28F400BX-T 28F004BX-T
ABSOLUTE MAXIMUM RATINGS
Commercial Operating Temperature During Read C(1) During Block Erase Word Byte Write Temperature Under Bias Extended Operating Temperature During Read During Block Erase Word Byte Write Temperature Under Bias Storage Temperature
NOTICE This production data sheet specifications subject change without notice
WARNING Stressing device beyond ``Absolute Maximum Ratings'' cause permanent damage These stress ratings only Operation beyond ``Operating Conditions'' recommended extended exposure beyond ``Operating Conditions'' affect device reliability
Voltage (except 0V(2) with Respect Voltage 5V(2 with Respect Program Voltage with Respect during Block Erase 0V(2 Word Byte Write Supply Voltage with Respect Output Short Circuit Current
0V(2)
mA(4)
OPERATING CONDITIONS
Symbol Parameter Operating Temperature Supply Voltage (10%) Supply Voltage (5%) Notes Units
NOTES Operating temperature commercial product defined this specification Minimum voltage input output pins During transitions this level undershoot periods Maximum voltage input output pins which during transitions overshoot periods Maximum voltage overshoot periods Maximum voltage overshoot periods Output shorted more than second more than output shorted time specifications reference 28F400BX-60 28F004BX-60 their standard test configuration 28F400BX-80 28F004BX-80 specifications reference 28F400BX-60 28F004BX-60 their high speed test configuration
CHARACTERISTICS
Symbol Parameter Input Load Current Output Leakage Current Notes
Unit
Test Condition VOUT
28F400BX-T 28F004BX-T
CHARACTERISTICS
Symbol ICCS Parameter Standby Current
(Continued) Notes Unit Test Conditions
28F400BX BYTE
ICCD ICCR
Deep Powerdown Current Read Current 28F400BX Word-Wide Byte-Wide Mode 28F004BX Byte-Wide Mode
(Max) (Typ) IOUT CMOS Inputs (Max) (Typ) IOUT Inputs Word Byte Write Progress Block Erase Progress Block Erase Suspended
ICCW ICCE ICCES IPPS IPPD IPPR IPPW IPPW IPPE IPPES
Word Byte Write Current Block Erase Current Erase Suspend Current Standby Current Deep PowerDown Current Read Current Word Write Current Byte Write Current Block Erase Current Erase Suspend Current Boot Block Unlock Current Intelligent Identifier Current Intelligent Identifier Voltage Input Voltage Input High Voltage Output Voltage
VPPH Word Write Progress VPPH Byte Write Progress VPPH Block Erase Progress VPPH Block Erase Suspended
28F400BX-T 28F004BX-T
CHARACTERISTICS
Symbol VOH1 VOH2 Parameter
(Continued) Notes Unit Test Conditions Boot Block Write Erase
Output High Voltage (TTL) Output High Voltage (CMOS)
VPPL VPPH VPPH VLKO
during Normal Operations during Erase Write Operations during Erase Write Operations Erase Write Lock Voltage Unlock Voltage
NOTES currents unless otherwise noted Typical values These currents valid product versions (packages speeds) ICCES specified with device deselected device read while Erase Suspend Mode current draw ICCES ICCR Block Erases Word Byte Writes inhibited when VPPL guaranteed range between VPPH VPPL Sampled 100% tested Automatic Power Savings (APS) reduces ICCR less than typical static operation CMOS Inputs either Inputs either applications requiring block erase cycles applications requiring wider tolerances block erase cycles 28F004BX address follows COUT capacitance numbers ICCR typical Active Read Current
EXTENDED TEMPERATURE OPERATING CONDITIONS
Symbol Parameter Operating Temperature Supply Voltage (10%) Notes
Unit
CHARACTERISTICS EXTENDED TEMPERATURE OPERATION
Symbol ICCS Parameter Input Load Current Output Leakage Current Standby Current Notes Unit
Test Conditions VOUT
28F400BX BYTE
ICCD
Deep Power-Down Current
28F400BX-T 28F004BX-T
CHARACTERISTICS EXTENDED TEMPERATURE OPERATION (Continued)
Symbol ICCR Parameter Notes Unit Test Conditions Read Current 28F400BX Word-Wide Byte-Wide Mode 28F004BX Byte-Wide Mode IOUT CMOS Inputs IOUT Inputs Word Write Progress Block Erase Progress Block Erase Suspended
ICCW ICCE ICCES IPPS IPPD IPPR IPPW IPPW IPPE IPPES VOH1
Word Write Current Block Erase Current Erase Suspend Current Standby Current Deep Power-Down Current Read Current Word Write Current Byte Write Current Block Erase Current Erase Suspend Current Boot Block Unlock Current Intelligent Identifier Current Intelligent Identifier Current Input Voltage Input High Voltage Output Voltage Output High Voltage (TTL)
VPPH Word Write Progress VPPH Byte Write Progress VPPH Block Erase Progress VPPH Block Erase Suspended
28F400BX-T 28F004BX-T
CHARACTERISTICS EXTENDED TEMPERATURE OPERATION (Continued)
Symbol VOH2 Parameter Output High Voltage (CMOS) Notes VPPL VPPH VPPH VLKO during Normal Operations during Erase Write Operations during Erase Write Operations Erase Write Lock Voltage Unlock Voltage Boot Block Write Erase Unit Test Conditions
NOTES currents unless otherwise noted Typical values These currents valid product versions (packages speeds) ICCES specified with device deselected device read while Erase Suspend Mode current draw ICCES ICCR Block Erases Word Byte Writes inhibited when VPPL guaranteed range between VPPH VPPL Sampled 100% tested Automatic Power Savings (APS) reduces ICCR less than typical static operation CMOS Inputs either Inputs either applications requiring block erase cycles applications requiring wider tolerances block erase cycles 28F004BX address follows COUT capacitance numbers ICCR typical Active Read Current
CAPACITANCE(1)
Symbol COUT
Parameter Unit Conditions VOUT
Input Capacitance Output Capacitance
NOTE Sampled 100% tested
28F400BX-T 28F004BX-T
STANDARD TEST CONFIGURATION(1)
STANDARD INPUT OUTPUT REFERENCE WAVEFORM STANDARD TESTING LOAD CIRCUIT
290451
test inputs driven VTTL) Logic ``1'' VTTL) logic ``0'' Input timing begins VTTL) VTTL) Output timing ends Input rise fall times (10% 90%)
290451
Includes Capacitance
HIGH SPEED TEST CONFIGURATION(2)
HIGH SPEED INPUT OUTPUT REFERENCE WAVEFORM HIGH SPEED TESTING LOAD CIRCUIT
290451
test inputs driven Logic ``1'' logic ``0'' Input timing begins output timing ends Input rise fall times (10% 90%)
290451
Includes Capacitance NOTES Testing characteristics 28F400BX-60 28F004BX-60 standard test configuration 28F400BX-80 28F004BX-80 Testing characteristics 28F400BX-60 28F004BX-60 high speed test configuration
28F400BX-T 28F004BX-T
CHARACTERISTICS
Versions Symbol tAVAV Parameter Read Cycle Time
Read Only Operations(1)
28F400BX-60(4) 28F004BX-60(4) 28F400BX-60(5) 28F004BX-60(5) 28F400BX-80(5) 28F004BX-80(5) 28F400BX-120(5) Unit 28F004BX-120(5)
Notes
tAVQV tACC Address Output Delay tELQV Output Delay
tPHQV tPWH High Output Delay tGLQV tELQX tEHQZ Output Delay Output
High Output High Output
tGLQX tOLZ tGHQZ
High Output High Output Hold from Addresses Change Whichever First Input Rise Time Input Fall Time BYTE Switching High BYTE Switching High Valid Output Delay BYTE Switching Output High
tELFL tELFH tFHQV
tFLQZ
NOTES Input Output Reference Waveform timing measurements delayed after falling edge without impact Sampled 100% tested High Speed Test Configuration Standard Test Configuration tFLQV BYTE switching valid output delay will equal tAVQV measured from time DQ15 becomes valid
28F400BX-T 28F004BX-T
EXTENDED TEMPERATURE OPERATION CHARACTERISTICS Read Only Operations(1)
Versions Symbol tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tACC tPWH tOLZ Parameter Read Cycle Time Address Output Delay Output Delay Notes T28F400BX-80(4) T28F004BX-80 Unit
High Output Delay Output Delay Output
High Output High Output
High Output High Output Hold from Addresses Change Whichever First Input Rise Time Input Fall Time BYTE Switching High BYTE Switching High Valid Output Delay BYTE Switching Output High
tELFL tELFH tFHQV
tFLQZ
NOTES Input Output Reference Waveform timing measurements delayed after falling edge without impact Sampled 100% tested Standard Test Configuration tFLQV BYTE switching valid output delay will equal tAVQV from time DQ15 becomes valid
28F400BX-T 28F004BX-T
Figure Waveforms Read Operations
290451-
28F400BX-T 28F004BX-T
290451
290451
Figure (RMS) Frequency (VCC Operation
Figure (RMS) Frequency (VCC Operation
290451
Figure TACC Output Load Capacitance
28F400BX-T 28F004BX-T
Figure BYTE
Timing Diagram Both Read Write Operations 28F400BX
290451-
28F400BX-T 28F004BX-T
CHARACTERISTICS
Versions Symbol tAVAV tPHWL Parameter
Controlled Write Operations(1)
28F400BX-60(9) 28F004BX-60(9) 28F400BX-60(10) 28F400BX-80(10) 28F400BX-120(10) Unit 28F004BX-60(10) 28F004BX-80(10) 28F004BX-120(10) Notes
Write Cycle Time High Recovery Going Setup Going
tELWL
tPHHWH tPHS Setup Going High tVPWH tAVWH tDVWH tVPS Setup Going High Address Setup Going High Data Setup Going High Pulse Width
tWLWH tWHDX tWHAX tWHEH
Data Hold from High Address Hold from High Hold from High
tWHWL tWPH Pulse Width High tWHQV1 Duration Word Byte Programming Operation Duration Erase Operation (Boot) Duration Erase Operation (Parameter) Duration Erase Operation (Main) tVPH Hold from Valid
tWHQV2 tWHQV3
tWHQV4 tQVVL
28F400BX-T 28F004BX-T
CHARACTERISTICS
Versions Symbol Parameter Notes
Controlled Write Operations(1) (Continued)
28F400BX-60(9) 28F004BX-60(9) 28F400BX-60(10) 28F004BX-60(10) 28F400BX-80(10) 28F004BX-80(10) 28F400BX-120(10) Unit 28F004BX-120(10)
tQVPH tPHH Hold from Valid tPHBR Boot-Block Relock Delay Input Rise Time Input Fall Time
NOTES Read timing characteristics during write erase operations same during read-only operations Refer characteristics during Read Mode on-chip completely automates program erase operations program erase algorithms controlled internally which includes verify margining operations Refer command definition table valid Refer command definition table valid Program Erase durations measured valid data (successful operation Boot Block Program Erase should held until operation completes successfully Time tPHBR required successful relocking Boot Block Sampled 100% tested High Speed Test Configuration Standard Test Configuration
BLOCK ERASE WORD BYTE WRITE PERFORMANCE Parameter Boot Parameter Block Erase Time Main Block Erase Time Main Block Byte Program Time Main Block Word Program Time Notes 28F400BX-60 28F004BX-60 Typ(1) 28F400BX-80 28F004BX-80 Typ(1) 28F400BX-120 28F004BX-120 Typ(1) Unit
NOTES Excludes System-Level Overhead
28F400BX-T 28F004BX-T
BLOCK ERASE WORD BYTE WRITE PERFORMANCE Parameter Boot Parameter Block Erase Time Main Block Erase Time Main Block Byte Program Time Main Block Word Program Time Notes 28F400BX-60 28F004BX-60 Typ(1) 28F400BX-80 28F004BX-80 Typ(1) 28F400BX-120 28F004BX-120 Typ(1) Unit
NOTES Excludes System-Level Overhead
EXTENDED TEMPERATURE OPERATION CHARACTERISTICS Controlled Write Operations(1)
Versions(4) Symbol tAVAV tPHWL tELWL tPHHWH tVPWH tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tWHQV1 tWHQV2 tPHS tVPS tWPH Parameter Write Cycle Time High Recovery Going Setup Going Notes T28F400BX-80(9) T28F004BX-80(9) High High Unit
Setup Going High Setup Going High
Address Setup Going High Data Setup Pulse Width Going High
Data Hold from
Address Hold from Hold from
High
Pulse Width High
Duration Word Byte Programming Operation Duration Erase Operation (Boot)
28F400BX-T 28F004BX-T
EXTENDED TEMPERATURE OPERATION CHARACTERISTICS Controlled Write Operations(1) (Continued)
Versions(4) Symbol tWHQV3 tWHQV4 tQVVL tQVPH tPHBR tVPH tPHH Parameter Duration Erase Operation (Parameter) Duration Erase Operation (Main) Hold from Valid Hold from Valid Boot-Block Relock Delay Input Rise Time Input Fall Time Notes T28F400BX-80(9) T28F004BX-80(9) Unit
NOTES Read timing characteristics during write erase operations same during read-only operations Refer characteristics during Read Mode on-chip completely automates program erase operations program erase algorithms controlled internally which includes verify margining operations Refer command definition table valid Refer command definition table valid Program Erase durations measured valid data (successful operation Boot Block Program Erase should held until operation completes successfully Time tPHBR required successful relocking Boot Block Sampled 100% tested Standard Test Configuration
EXTENDED TEMPERATURE OPERATION BLOCK ERASE WORD BYTE WRITE PERFORMANCE Parameter Boot Parameter Block Erase Time Main Block Erase Time Main Block Byte Program Time Main Block Word Program Time
NOTES Excludes System-Level Overhead
Notes
T28F400BX-80 T28F004BX-80 Typ(1)
Unit
28F400BX-T 28F004BX-T
Figure Waveforms Write Erase Operations -Controlled Writes)
290451-
28F400BX-T 28F004BX-T
CHARACTERISTICS
Versions Symbol tAVAV tPHEL Parameter
-CONTROLLED WRITE OPERATIONS(1
28F400BX-60(10) 28F004BX-60(10) 28F400BX-60(11) 28F400BX-80(11) 28F400BX-120(11) Unit 28F004BX-60(11) 28F004BX-80(11) 28F004BX-120(11)
Notes
Write Cycle Time High Recovery Going
tWLEL
Setup Going Setup Going High
tPHHEH tPHS tVPEH tAVEH tDVEH tELEH tEHDX tEHAX
tVPS Setup Going High Address Setup Going High Data Setup Going High Pulse Width
Data Hold from High Address Hold from High
tEHWH Hold from High tEHEL tEHQV1 tCPH Pulse Width High Duration Word Byte Programming Operation Duration Erase Operation (Boot) Duration Erase Operation (Parameter) Duration Erase Operation (Main) tVPH Hold from Valid tPHH Hold from Valid Boot-Block Relock Delay
tEHQV2 tEHQV3
tEHQV4 tQVVL tQVPH tPHBR
28F400BX-T 28F004BX-T
CHARACTERISTICS
Versions Symbol Parameter Notes
-CONTROLLED WRITE OPERATIONS(1 (Continued)
28F400BX-60(10) 28F004BX-60(10) 28F400BX-60(11) 28F004BX-60(11) 28F400BX-80(11) 28F400BX-120(11) Unit 28F004BX-80(11) 28F004BX-120(11)
Input Rise Time Input Fall Time
NOTES Chip-Enable Controlled Writes Write operations driven valid combination systems where defines write pulse-width (within longer timing waveform) set-up hold inactive times should measured relative waveform Refer Characteristics notes -Controlled Write Operations Read timing characteristics during write erase operations same during read-only operations Refer Characteristics during Read Mode High Speed Test Configuration Standard Test Configuration
EXTENDED TEMPERATURE OPERATION CHARACTERISTICS -CONTROLLED WRITE OPERATIONS(1
Versions Symbol tAVAV tPHEL tWLEL tPHHEH tVPEH tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tEHQV1 tPHS tVPS tCPH Parameter Write Cycle Time High Recovery Setup Setup Going Going Going High Going High Going High Going High High High High Notes T28F400BX-80(10) T28F004BX-80(10) Unit
Setup Data Setup Pulse Width Data Hold from
Address Setup
Address Hold from Hold from Pulse Width High
Duration Word Byte Programming Operation
28F400BX-T 28F004BX-T
Figure Alternate Waveforms Write Erase Operations -Controlled Writes)
290451-
28F400BX-T 28F004BX-T
EXTENDED TEMPERATURE OPERATION CHARACTERISTICS -CONTROLLED WRITE OPERATIONS(1 (Continued)
Versions Symbol tEHQV2 tEHQV3 tEHQV4 tQVVL tQVPH tPHBR tVPH tPHH Parameter Duration Erase Operation (Boot) Duration Erase Operation (Parameter) Duration Erase Operation (Main) Hold from Valid Hold from Valid Boot-Block Relock Delay Input Rise Time Input Fall Time Notes T28F400BX-80(10) T28F004BX-80(10) Unit
NOTES Chip-Enable Controlled Writes Write operations driven valid combination systems where defines write pulse-width (within longer timing waveform) set-up hold inactive times should measured relative waveform Refer Characteristics -Controlled Write Operations Read timing characteristics during write erase operations same during read-only operations Refer Characteristics during Read Mode Standard Test Configuration
ORDERING INFORMATION
290451
VALID COMBINATIONS E28F400BX-T60 PA28F400BX-T60 E28F400BX-B60 PA28F400BX-B60 E28F400BX-T80 PA28F400BX-T80 E28F400BX-B80 PA28F400BX-B80 E28F400BX-T120 PA28F400BX-T120 E28F400BX-B120 PA28F400BX-B120
TE28F400BX-T80 TE28F400BX-B80
TB28F400BX-T80 TB28F400BX-B80
290451
VALID COMBINATIONS E28F004BX-T60 E28F004BX-T80 E28F004BX-B60 E28F004BX-B80
TE28F004BX-T80 TE28F004BX-B80
E28F004BX-T120 E28F004BX-B120
28F400BX-T 28F004BX-T
ADDITIONAL INFORMATION References
Order Number 290448 290449 290450 290531 290530 290539 292098 292148 292178 292130 292154 Document 28F002 200BX-T 2-Mbit Boot Block Flash Memory Datasheet 28F002 200BL-T 2-Mbit Power Boot Block Flash Memory Datasheet 28F004 400BL-T 4-Mbit Power Boot Block Flash Memory Datasheet 2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet 4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet 8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet AP-363 ``Extended Flash BIOS Concepts Portable Computers'' AP-604 ``Using Intel's Boot Block Flash Memory Parameter Blocks Replace EEPROM'' AP-623 ``Multi-Site Layout Planning Using Intel's Boot Block Flash Memory'' AB-57 ``Boot Block Architecture Safe Firmware Updates'' AB-60 8-Mbit SmartVoltage Boot Block Flash Memory Family''
Revision History
Number -001 -002 Original Version Removed speed Integrated characteristics into speed Added Extended Temperature characteristics Modified BYTE Timing Diagram renamed JEDEC standardization compatibility Combined Read current 28F400BX Word-Wide Mode Byte-Wide Mode 28F004BX Byte-Wide Mode Characteristics tables Added Boot Black Unlock Current specifications Characteristics tables Improved ICCR ICCW Characteristics Extended Temperature Operation table Improved tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tFHQV tFLQZ specifications Extended Temperature Operations Characteristics Read Write Operations Added specifications access time product version 28F400BX-120 28F004BX-120 Included permanent change write timing parameters product versions Write pulse width (tWP tCP) increases from Write pulse width high (tWPH tCPH) decreases from Total write cycle time (tWC) remains unchanged Added ICCR test condition note typical frequency value Characteristics table Added CMOS specification Added 28F400BX interface Intel386 Embedded Processor block diagram Added description design upgrading SmartVoltage Boot Block products Added references input rise fall times Description
-003
-004
-005
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