Enable Disable Control Individual Requests Four Independent Channels I
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8237A HIGH PERFORMANCE PROGRAMMABLE CONTROLLER (8237A-5)
Enable Disable Control Individual Requests Four Independent Channels Independent Autoinitialization Channels Memory-to-Memory Transfers Memory Block Initialization Address Increment Decrement High Performance Transfers Bytes Second with 8237A-5
Directly Expandable Number Channels Process Input Terminating Transfers Software Requests Independent Polarity Control DREQ DACK Signals Available EXPRESS Standard Temperature Range Available 40-Lead Cerdip Plastic Packages
(See Packaging Spec Order 231369)
8237A Multimode Direct Memory Access (DMA) Controller peripheral interface circuit microprocessor systems designed improve system performance allowing external devices directly transfer information from system memory Memory-to-memory transfer capability also provided 8237A offers wide variety programmable control features enhance data throughput system optimization allow dynamic reconfiguration under program control 8237A designed used conjunction with external 8-bit address latch contains four independent channels expanded number channels cascading additional controller chips three basic transfer modes allow programmability types service user Each channel individually programmed Autoinitialize original condition following Process (EOP) Each channel full address word count capability
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Figure Configuration
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Figure Block Diagram
September 1993
Order Number 231466-005
8237A
Table Description Symbol Type POWER supply GROUND Ground CLOCK INPUT Clock Input controls internal operations 8237A rate data transfers input driven 8237A-5 CHIP SELECT Chip Select active input used select 8237A device during Idle cycle This allows communication data RESET Reset active high input which clears Command Status Request Temporary registers also clears first last flip flop sets Mask register Following Reset device Idle cycle READY Ready input used extend memory read write pulses from 8237A accommodate slow memories peripheral devices Ready must make transitions during specified setup hold time HOLD ACKNOWLEDGE active high Hold Acknowledge from indicates that relinquished control system busses REQUEST Request lines individual asynchronous channel request inputs used peripheral circuits obtain service fixed Priority DREQ0 highest priority DREQ3 lowest priority request generated activating DREQ line channel DACK will acknowledge recognition DREQ signal Polarity DREQ programmable Reset initializes these lines active high DREQ must maintained until corresponding DACK goes active DATA Data lines bidirectional three-state signals connected system data outputs enabled Program condition during Read output contents Address register Status register Temporary register Word Count register outputs disabled inputs read during Write cycle when programming 8237A control registers During cycles most significant bits address output onto data strobed into external latch ADSTB memory-to-memory operations data from memory comes into 8237A data during read-frommemory transfer write-to-memory transfer data outputs place data into memory location READ Read bidirectional active three-state line Idle cycle input control signal used read control registers Active cycle output control signal used 8237A access data from peripheral during Write transfer WRITE Write bidirectional active three-state line Idle cycle input control signal used load information into 8237A Active cycle output control signal used 8237A load data peripheral during Read transfer Name Function
RESET
READ
HLDA
DREQ0 -DREQ3
DB0-DB7
8237A
Table Description (Continued) Symbol Type Name Function PROCESS Process active bidirectional signal Information concerning completion services available bidirectional 8237A allows external signal terminate active service This accomplished pulling input with external signal 8237A also generates pulse when terminal count (TC) channel reached This generates signal which output through line reception either internal external will cause 8237A terminate service reset request Autoinitialize enabled write base registers current registers that channel mask status word will currently active channel unless channel programmed Autoinitialize that case mask remains unchanged During memory-to-memory transfers will output when channel occurs should tied high with pull-up resistor used prevent erroneous process inputs ADDRESS four least significant address lines bidirectional three-state signals Idle cycle they inputs used address register loaded read Active cycle they outputs provide lower bits output address ADDRESS four most significant address lines three-state outputs provide bits address These lines enabled only during service HOLD REQUEST This Hold Request used request control system corresponding mask clear presence valid DREQ causes 8237A issue ACKNOWLEDGE Acknowledge used notify individual peripherals when been granted cycle sense these lines programmable Reset initializes them active ADDRESS ENABLE Address Enable enables 8-bit latch containing upper address bits onto system address also used disable other system drivers during transfers active HIGH ADDRESS STROBE active high Address Strobe used strobe upper address byte into external latch MEMORY READ Memory Read signal active threestate output used access data from selected memory location during Read memory-to-memory transfer MEMORY WRITE Memory Write active three-state output used write data selected memory location during Write memory-to-memory transfer PIN5 This should always logic HIGH level internal pull-up resistor will establish logic high when left floating recommended however that PIN5 connected
A0-A3
A4-A7
DACK0-DACK3
ADSTB MEMR
MEMW
PIN5
8237A
valid requests pending While controller inactive Program Condition being programmed processor State (S0) first state service 8237A requested hold processor returned acknowledge 8237A still programmed until receives HLDA from acknowledge from will signal that transfers begin working states service more time needed complete transfer than available with normal timing wait states (SW) inserted between Ready line 8237A Note that data transferred directly from device memory vice versa) with MEMW MEMR IOW) being active same time data read into driven 8237A O-to-memory memory-to-I transfers Memory-to-memory transfers require read-from write-to-memory complete each transfer states which resemble normal working states digit numbers identification Eight states required single transfer first four states (S11 S14) used readfrom-memory half last four states (S21 S24) write-to-memory half transfer IDLE CYCLE When channel requesting service 8237A will enter Idle cycle perform ``SI'' states this cycle 8237A will sample DREQ lines every clock cycle determine channel requesting service device will also sample looking attempt microprocessor write read internal registers 8237A When HLDA 8237A enters Program Condition establish change inspect internal definition part reading from writing internal registers Address lines inputs device select which registers will read written lines used select time reads writes number size internal registers internal flip-flop used generate additional address This used determine upper lower byte 16-bit Address Word Count registers flip-flop reset Master Clear Reset separate software command also reset this flip-flop Special software commands executed 8237A Program Condition These commands decoded sets addresses with commands make data Instructions include Clear First Last Flip-Flop Master Clear
FUNCTIONAL DESCRIPTION
8237A block diagram includes major logic blocks internal registers data interconnection paths also shown shown various control signals between blocks 8237A contains bits internal memory form registers Figure lists these registers name shows size each detailed description registers their functions found under Register Description
Name Base Address Registers Base Word Count Registers Current Address Registers Current Word Count Registers Temporary Address Register Temporary Word Count Register Status Register Command Register Temporary Register Mode Registers Mask Register Request Register Size bits bits bits bits bits bits bits bits bits bits bits bits Number
Figure 8237A Internal Registers 8237A contains three basic blocks control logic Timing Control block generates internal timing external control signals 8237A Program Command Control block decodes various commands given 8237A microprocessor prior servicing Request also decodes Mode Control word used select type during servicing Priority Encoder block resolves priority contention between channels requesting service simultaneously Timing Control block derives internal timing from clock input 8237A systems this input will usually clock from 8224 from 8085AH 8284A duty cycle clock generators however meet clock high time requirement 8237A same frequency example 82C84A-5 output violates clock high time requirement 8237A-5 this case 82C84A simply inverted meet 8237A-5 clock high time requirements 8085AH-2 systems above 8085 CLK(OUT) does satisfy 8237A-5 clock HIGH time requirements this case external clock should used drive 8237A-5
OPERATION
8237A designed operate major cycles These called Idle Active cycles Each device cycle made number states 8237A assume seven separate states each composed full clock period State (SI) inactive state entered when 8237A
8237A
Process (EOP) encountered DREQ need only held active until DACK becomes active Again Autoinitialization will occur service channel been programmed Demand Transfer Mode Demand Transfer mode device programmed continue making transfers until external encountered until DREQ goes inactive Thus transfers continue until device exhausted data capacity After device chance catch service re-established means DREQ During time between services when microprocessor allowed operate intermediate values address word count stored 8237A Current Address Current Word Count registers Only cause Autoinitialize service generated either external signal DREQ before prevent another Transfer Cascade Mode This mode used cascade more than 8237A together simple system expansion HLDA signals from additional 8237A connected DREQ DACK signals channel initial 8237A This allows requests additional device propagate through priority network circuitry preceding device priority chain preserved device must wait turn acknowledge requests Since cascade channel initial 8237A used only prioritizing additional device does output address control
ACTIVE CYCLE When 8237A Idle cycle nonmasked channel requests service device will output microprocessor enter Active cycle this cycle that service will take place four modes Single Transfer Mode Single Transfer mode device programmed make transfer only word count will decremented address decremented incremented following each transfer When word count ``rolls over'' from zero FFFFH Terminal Count (TC) will cause Autoinitialize channel been programmed DREQ must held active until DACK becomes active order recognized DREQ held active throughout single transfer will inactive release system will again active upon receipt HLDA another single transfer will performed 8080A 8085AH 8088 8086 system this will ensure full machine cycle execution between transfers Details timing between 8237A other control protocols will depend upon characteristics microprocessor involved Block Transfer Mode Block Transfer mode device activated DREQ continue making transfers during service until caused word count going FFFFH external
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Figure Cascaded 8237As
8237A
signals These could conflict with outputs active channel added device 8237A will respond DREQ DACK other outputs except will disabled ready input ignored Figure shows additional devices cascaded into initial device using previous channels This forms level system More 8237As could added second level using remaining channels first level Additional devices also added cascading into channels second level device forming third level TRANSFER TYPES Each three active transfer modes perform three different types transfers These Read Write Verify Write transfers move data from device memory activating MEMW Read transfers move data from memory device activating MEMR Verify transfers pseudo transfers 8237A operates Read Write transfers generating addresses responding However memory control lines remain inactive ready input ignored verify mode Memory-to-Memory perform block moves data from memory address space another with minimum program effort time 8237A includes memory-to-memory transfer feature Programming Command register selects channels operate memory-tomemory transfer channels transfer initiated setting software DREQ channel 8237A requests service normal manner After HLDA true device using four state transfers Block Transfer mode reads data from memory channel Current Address register source address used decremented incremented normal manner data byte read from memory stored 8237A internal Temporary register Channel then performs four-state transfer data from Temporary register memory using address Current Address register incrementing decrementing normal manner channel current Word Count decremented When word count channel goes FFFFH generated causing output terminating service Channel programmed retain same address transfers This allows single word written block memory 8237A will respond external signals during memory-to-memory transfers Data comparators block search schemes this input terminate service when match found timing memory-to-memory transfers found Figure Memory-to-memory operations detected active with DACK outputs Autoinitialize programming Mode register channel Autoinitialize channel During Autoinitialize initialization original values Current Address Current Word Count registers automatically restored from Base Address Base Word count registers that channel following base registers loaded simultaneously with current registers microprocessor remain unchanged throughout service mask altered when channel Autoinitialize Following Autoinitialize channel ready perform another service without intervention soon valid DREQ detected order Autoinitialize both channels memory-to-memory transfer both word counts should programmed identically interrupted externally pulses should applied both cycles Priority 8237A types priority encoding available software selectable options first Fixed Priority which fixes channels priority order based upon descending value their number channel with lowest priority followed highest priority channel After recognition channel service other channels prevented from interfering with that service until completed After completion service will inactive 8237A will wait HLDA before activating service another channel second scheme Rotating Priority last channel service becomes lowest priority channel with others rotating accordingly
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8237A
With Rotating Priority single chip system device requesting service guaranteed recognized after more than three higher priority services have occurred This prevents channel from monopolizing system Compressed Timing order achieve even greater throughput where system characteristics permit 8237A compress transfer time clock cycles From Figure seen that state used extend access time read pulse removing state read pulse width made equal write pulse width transfer consists only state change address state perform read write states will still occur when A8-A15 need updating (see Address Generation) Timing compressed transfers found Figure Address Generation order reduce count 8237A multiplexes eight higher order address bits data lines State used output higher order address bits external latch from which they placed address falling edge Address Strobe (ADSTB) used load these bits from data lines latch Address Enable (AEN) used enable bits onto address through three-state enable lower order address bits output 8237A directly Lines A0-A7 should connected address Figure shows time relationships between ADSTB DB0- A0-A7 During Block Demand Transfer mode services which include multiple transfers addresses generated will sequential many transfers data held external address latch will remain same This data need only change when carry borrow from takes place normal sequence addresses save time speed transfers 8237A executes states only when updating A8-A15 latch necessary This means long services states Address Strobes occur only once every transfers savings clock cycles each transfers Current Word Register Each channel 16bit Current Word Count register This register determines number transfers performed actual number transfers will more than number programmed Current Word Count register programming count will result transfers) word count decremented after each transfer intermediate value word count stored register during transfer When value register goes from zero FFFFH will generated This register loaded read successive 8-bit bytes microprocessor Program Condition Following service also reinitialized Autoinitialization back original value Autoinitialize occur only when occurs Autoinitialized this register will have count FFFFH after Base Address Base Word Count Registers Each channel pair Base Address Base Word Count registers These 16-bit registers store original value their associated current registers During Autoinitialize these values used restore current registers their original values base registers written simultaneously with their corresponding current register 8-bit bytes Program Condition microprocessor These registers cannot read microprocessor Command Register This 8-bit register controls operation 8237A programmed microprocessor Program Condition cleared Reset Master Clear instruction following table lists function command bits Figure address coding Mode Register Each channel 6-bit Mode register associated with When register being written microprocessor Program Condition bits determine which channel Mode register written Request Register 8237A respond requests service which initiated software well DREQ Each channel request associated with 4-bit Request register These non-maskable subject prioritization Priority Encoder network Each register reset separately under software control cleared upon generation external entire register cleared Reset reset software loads proper form data word Figure register address coding order make software request channel must Block Mode
REGISTER DESCRIPTION
Current Address Register Each channel 16-bit Current Address register This register holds value address used during transfers address automatically incremented decremented after each transfer intermediate values address stored Current Address register during transfer This register written read microprocessor successive 8-bit bytes also reinitialized Autoinitialize back original value Autoinitialize takes place only after
8237A
Mask Register Each channel associated with mask which disable incoming DREQ Each mask when associated channel produces channel programmed Autoinitialize Each 4-bit Mask register also cleared separately under software control entire register also Reset This disables requests until clear Mask register instruction allows them occur instruction separately clear mask bits similar form that used with Request register Figure instruction addressing
Command Register
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four bits Mask register also written with single command
Mode Register
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Register Operation Command Mode Request Mask Mask Temporary Status Write Write Write Reset Write Read Read
Signals
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Request Register
Figure Definition Register Codes Status Register Status register available read 8237A microprocessor contains information about status devices this point This information includes which channels have reached terminal count which chan-
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8237A
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nels have pending requests Bits every time reached that channel external applied These bits cleared upon Reset each Status Read Bits whenever their corresponding channel requesting service Temporary Register Temporary register used hold data during memory-to-memory transfers Following completion transfers last word moved read microprocessor Program Condition Temporary register always contains last byte transferred previous memory-to-memory operation unless cleared Reset Software Commands These cial software commands which Program Condition They specific pattern data ware commands additional spebe executed depend three soft-
Clear First Last Flip-Flop This command must executed prior writing reading address word count information 8237A This initializes flip-flop known state that subsequent accesses register contents microprocessor will address upper lower bytes correct sequence Master Clear This software instruction same effect hardware Reset Command Status Request Temporary Internal First Last Flip-Flop registers cleared Mask register 8237A will enter Idle cycle Clear Mask Register This command clears mask bits four channels enabling them accept requests
Figure lists address codes software commands
Operation
Signals
Read Status Register Write Command Register Illegal Write Request Register Illegal Write Single Mask Register Illegal Write Mode Register Illegal Clear Byte Pointer Flip Flop Read Temporary Register Master Clear Illegal Clear Mask Register Illegal Write Mask Register Bits
Figure Software Command Codes
8237A
Channel
Register Base Current Address Current Address Base Current Word Count Current Word Count
Operation Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read
Internal Data Flip-Flop
Signals
Base Current Address Current Address Base Current Word Count Current Word Count
Base Current Address Current Address Base Current Word Count Current Word Count
Base Current Address Current Address Base Current Word Count Current Word Count
Figure Word Count Address Register Command Codes
8237A
channels unused invalid mode force control signals active same time APPLICATION INFORMATION (Note Figure shows convenient method configuring system with 8237A controller 8080A 8085AH microprocessor system multimode controller issues processor whenever there least valid request from peripheral device When processor replies with HLDA signal 8237A takes control address data control address first transfer operation comes bytes least significant bits eight address outputs most significant bits data contents data then latched into 8-bit latch complete full bits address 8282 high speed 8-bit three-state latch 20-pin package After initial transfer takes place latch updated only after carry borrow generated least significant address byte Four channels provided when 8237A used
PROGRAMMING 8237A will accept programming from host processor time that HLDA inactive this true even active responsibility host assure that programming HLDA mutually exclusive Note that problem occur request occurs unmasked channel while 8237A being programmed instance starting reprogram byte Address register channel when channel receives request 8237A enabled (bit command register channel unmasked service will occur after only byte Address register been reprogrammed This avoided disabling controller (setting command register) masking channel before programming other registers Once programming complete controller enabled unmasked After power-up suggested that internal locations especially Mode registers loaded with some valid value This should done even some
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Figure 8237A System Interface
NOTE Application Note AP-67 8086 design information
8237A
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias Case Temperature Storage Temperature Voltage with Respect Ground Power Dissipation
NOTICE This production data sheet specifications subject change without notice
WARNING Stressing device beyond ``Absolute Maximum Ratings'' cause permanent damage These stress ratings only Operation beyond ``Operating Conditions'' recommended extended exposure beyond ``Operating Conditions'' affect device reliability
Watt
CHARACTERISTICS
TCASE Symbol Parameter Output High Voltage Output Voltage Input HIGH Voltage Input Voltage Input Load Current Output Leakage Current Supply Current Output Capacitance Input Capacitance Capacitance
(Note
Unit
Test Conditions (HRQ Only)
VOUT Inputs
NOTE Typical values nominal supply voltage nominal processing parameters
8237A
CHARACTERISTICS
Symbol TAEL TAET TAFAB TAFC TAFDB TAHR TAHS TAHW
(MASTER) MODE
Parameter 8237A-5 TCY-100 TCY-50 Unit
TCASE
HIGH from (S1) Delay Time from HIGH (SI) Delay Time Active Float Delay from HIGH READ WRITE Float from HIGH Active Float Delay from HIGH from READ HIGH Hold Time from ADSTB Hold Time from WRITE HIGH Hold Time DACK Valid from Delay Time (Note 1)220 HIGH from HIGH Delay Time (Note from HIGH Delay Time
TASM TASS TDCL TDCTR TDCTW TDQ1 TDQ2 TEPS TEPW TFAAB TFAC TFADB TIDH TIDS TODH TODV TSTL TSTT
Stable from HIGH ADSTB Setup Time Clock High Time (Transitionss10 Clock Time (Transitionss10 Cycle Time HIGH READ WRITE Delay (Note READ HIGH from HIGH (S4) Delay Time (Note WRITE HIGH from HIGH (S4) Delay Time (Note Valid from HIGH Delay Time (Note from Setup Time Pulse Width Float Active Delay from HIGH READ WRITE Active from HIGH Float Active Delay from HIGH HLDA Valid HIGH Setup Time Input Data from MEMR HIGH Hold Time Input Data MEMR HIGH Setup Time Output Data from MEMW HIGH Hold Time Output Data Valid MEMW HIGH DREQ Setup Time (Note READY Hold Time READY Setup Time ADSTB HIGH from HIGH Delay Time ADSTB from HIGH Delay Time
8237A
CHARACTERISTICS
Symbol TRDE TRDF TRSTD TRSTS TRSTW TWWS
PERIPHERAL (SLAVE) MODE
Parameter 8237A-5 2TCY Unit
TCASE
Valid READ Valid WRITE HIGH Setup Time WRITE HIGH Setup Time Data Valid WRITE HIGH Setup Time Hold from READ HIGH Data Access from READ (Note Float Delay from READ HIGH Power Supply HIGH RESET Setup Time RESET First IOWR RESET Pulse Width READ Width from WRITE HIGH Hold Time HIGH from WRITE HIGH Hold Time Data from WRITE HIGH Hold Time Write Width Write Read Transfer
NOTES DREQ DACK signals active high active Timing diagrams assume active high mode open collector output This parameter assumes presence pullup MEMW Pulse width normal write will TCYb100 extended write will 2TCYb100 MEMR pulse width normal read will 2TCY compressed read will specified different output HIGH levels TDQ1 measured TDQ2 measured value TDQ2 assumes external pull-up resistor connected from Output Loading Data Gate plus capacitance
TESTING INPUT OUTPUT WAVEFORM
231466 Testing Inputs driven Logic ``1'' Logic Timing measurements made Logic ``1'' Logic Input timing parameters assume transition times less Waveform measurement points both input output signals HIGH unless otherwise noted
8237A
WAVEFORMS
SLAVE MODE WRITE TIMING
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NOTE Successive read write operations external processor program examine controller must timed allow least 8237A-5 recovery time between active read write pulses same recovery time needed between active read write pulse followed transfer
Figure Slave Mode Write SLAVE MODE READ TIMING
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NOTE Successive read write operations external processor program examine controller must timed allow least 8237A-5 recovery time between active read write pulses same recovery time needed between active read write pulse followed transfer
Figure Slave Mode Read
8237A
WAVEFORMS (Continued)
TRANSFER TIMING
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NOTE DREQ should held active until DACK returned
Figure Transfer
8237A
WAVEFORMS (Continued)
MEMORY-TO-MEMORY TRANSFER TIMING
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Figure Memory-to-Memory Transfer READY TIMING
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Figure Ready
8237A
WAVEFORMS (Continued)
COMPRESSED TRANSFER TIMING
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Figure Compressed Transfer RESET TIMING
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Figure Reset
8237A
DESIGN CONSIDERATIONS
Cascading from channel zero When using multiple 8237s always start cascading with channel zero Channel zero 8237 will operate incorrectly more channels used cascade mode while channel zero used mode other than cascade treat DREQ signal asynchronous input while channel ``demand'' ``cascade'' modes DREQ becomes inactive time during state illegal state occur causing 8237 operate improperly must remain active until HLDA becomes active goes inactive before HLDA received 8237 enter illegal state causing operate improperly Make sure MEMR line loading capacitance When doing memory memory transfers 8237 requires least loading capacitance MEMR signal proper operation most cases board capacitance sufficient Treat READY input synchronous input transition occurs during setup hold window erratic operation result channel cascade mode should have active DREQ before
DATA SHEET REVISION REVIEW
following list represents differences between this -003 data sheet Please review this summary carefully Item added ``Design Considerations'' section
REVISION SUMMARThe following list represents differences between 1994 8237A Data Sheet References specifications 8237A 8237A-4 removed Only 8237A-5 device remains production
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