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Pentium® Processor PGA370 Socket
Available 933, 866, 800EB, 733, 667, 600EB, 533EB system Available 850, 800, 750, 700, 650, 600E, 550E, 500E system System frequency ("E" denotes support Advanced Transfer Cache Advanced system buffering; denotes support 133MHz system where both frequencies available order each given core frequency; Table summary features each line item.) Available versions that incorporate Advanced Transfer Cache (on-die, full speed Level (L2) cache with Error Correcting Code (ECC)) Dual Independent (DIB) architecture: Separate dedicated external System dedicated internal high-speed cache Internet Streaming SIMD Extensions enhanced video, sound performance Binary compatible with applications running previous members Intel microprocessor line
Dynamic execution micro architecture Intel Processor Serial Number Power Management capabilities System Management mode Multiple low-power states Optimized 32-bit applications running advanced 32-bit operating systems Flip Chip Grid Array (FC-PGA) packaging technology; FC-PGA processors deliver high performance with improved handling protection socketability Integrated high performance instruction data, nonblocking, level cache Integrated Full Speed level cache allows latency read/store operations Double Quad Word Wide(256bit) cache data provides extremely high throughput read/store operations. 8-way cache associativity provides improved cache rate reads/store operations. Error-correcting code System data Enables systems which scaleable processor
Pentium® processor designed high-performance desktops workstations servers. binary compatible with previous Intel Architecture processors. Pentium processor provides great performance applications running advanced operating systems such Windows* Windows UNIX*. This achieved integrating best attributes Intel processors- dynamic execution, Dual Independent architecture plus Intel MMXtechnology Internet Streaming SIMD Extentions- bringing level performance systems buyers. Pentium® processor scaleable processors multiprocessor system extends power Pentium® processor with performance headroom business media, communication internet capabilities. Systems based Pentium® processors also include latest features simplify system management lower cost ownership large small business environments. Pentium® processor offers great performance today's tomorrow's applications. FC-PGA370 Package
2000 Order Number: 245264-005
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® processor contain design defects errors known errata which cause product deviate from published specifcations. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2000 *Third-party brands names property their respective owners.
Pentium® Processor PGA370 Socket
Content1.0 Introduction. Terminology. 1.1.1 Package Processor Terminology 1.1.2 Processor Naming Convention.9 Related Documents.10 Processor System VREF Clock Control Power States.12 2.2.1 Normal State-State 2.2.2 AutoHALT Powerdown State-State 2.13 2.2.3 Stop-Grant State-State 2.2.4 HALT/Grant Snoop State-State 2.2.5 Sleep State-State 5.14 2.2.6 Deep Sleep State-State 2.2.7 Clock Control.15 Power Ground Pins 2.3.1 Phase Lock Loop (PLL) Power.16 Decoupling Guidelines 2.4.1 Processor VCCCORE Decoupling.16 2.4.2 Processor System AGTL+ Decoupling.16 Processor System Clock Processor Clocking 2.5.1 Mixing Processors Differrent Frequencies Voltage Identification Processor System Unused Pins.19 Processor System Signal Groups 2.8.1 Asynchronous Synchronous System Signals 2.8.2 System Frequency Select Signals (BSEL[1:0]) Test Access Port (TAP) Connection.22 Maximum Ratings.22 Processor Specifications.23 AGTL+ System Specifications System Specifications 2.13.1 Buffer Model BCLK PICCLK Signal Quality Specifications Measurement Guidelines AGTL+ Signal Quality Specifications Measurement Guidelines AGTL+ Signal Quality Specifications Measurement Guidelines 3.3.1 Overshoot/Undershoot Guidelines 3.3.2 Overshoot/Undershoot Magnitude 3.3.3 Overshoot/Undershoot Pulse Duration.39 3.3.4 Activity Factor 3.3.5 Reading Overshoot/Undershoot Specification Tables.40 3.3.6 Determining System meets Overshoot/Undershoot Specifications
Electrical Specifications.11
2.10 2.11 2.12 2.13
Signal Quality Specifications
Pentium® Processor PGA370 Socket
Non-AGTL+ Signal Quality Specifications Measurement Guidelines. 3.4.1 Overshoot/Undershoot Guidelines 3.4.2 Ringback Specification. 3.4.3 Settling Limit Guideline Thermal Specifications. 4.1.1 Thermal Diode. FC-PGA Mechanical Specifications Processor Markings Processor Signal Listing. Mechanical Specifications. 6.1.1 Boxed Processor Thermal Cooling Solution Dimensions. 6.1.2 Boxed Processor Heatsink Weight. 6.1.3 Boxed Processor Thermal Cooling Solution Clip Boxed Processor Requirements 6.2.1 Heatsink Power Supply Thermal Specifications. 6.3.1 Boxed Processor Cooling Requirements Alphabetical Signals Reference Signal Summaries
Thermal Specifications Design Considerations.
Mechanical Specifications.
Boxed Processor Specifications.
Processor Signal Description
Pentium® Processor PGA370 Socket
List Figure1 Second Level (L2) Cache Implementation AGTL+ Topology Uniprocessor Configuration AGTL+ Topology Dual-Processor Configuration Stop Clock State Machine Processor VccCMOS Package Routing BSEL[1:0] Example 100/133 Only System Design BCLK, PICCLK, Generic Clock Waveform.33 System Valid Delay Timings System Setup Hold Timings.33 System Reset Configuration Timings.34 Power-On Reset Configuration Timings.34 Test Timings (TAP Connection) Test Reset Timings BCLK, PICCLK Generic Clock Waveform Processor Pins.37 High AGTL+ Receiver Ringback Tolerance.38 Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform Non-AGTL+ Overshoot/Undershoot, Settling Limit, Ringback Processor Functional Layout Package Dimensions.48 Side Processor Markings Intel® Pentium® Processor Pinout Conceptual Boxed Intel® Pentium® Processor PGA370 Socket Side View Space Requirements Boxed Processor Side View Space Requirements Boxed Processor Dimensions Mechanical Step Feature Heatsink Base.64 Clip Keepout Requirements Boxed Intel® Pentium® Processors Boxed Processor Heatsink Power Cable Connector Description.65 Motherboard Power Header Placement Relative Boxed Intel® Pentium® Processor Thermal Airspace Requirement Boxed Intel® Pentium® Processor Heatsinks PGA370 Socket.67
Pentium® Processor PGA370 Socket
List Table1 Processor Identification. Voltage Identification Definition. System Signal Groups Frequency Select Truth Table BSEL[1:0] Absolute Maximum Ratings Voltage Current Specifications AGTL+ Signal Groups Specifications Non-AGTL+ Signal Group Specifications Processor AGTL+ Specifications System Specifications (Clock) Valid System Core Frequency Ratios System Specifications (AGTL+ Signal Group) System Specifications (CMOS Signal Group) System Specifications (Reset Conditions) System Specifications (APIC Clock APIC I/O) System Specifications (TAP Connection) BCLK/PICCLK Signal Quality Specifications Simulation Processor Pins AGTL+ Signal Groups Ringback Tolerance Specifications Processor Pins Example Platform Information. AGTL+ Signal Group Overshoot/Undershoot Tolerance Processor Pins AGTL+ Signal Group Overshoot/Undershoot Tolerance CMOS Signal Group Overshoot/Undershoot Tolerance Processor Pins Signal Ringback Specifications Non-AGTL+ Signal Simulation Processor Pins Intel® Pentium® Processor PGA370 Socket Thermal Specification. Thermal Diode Parameters Thermal Diode Interface. Intel® Pentium® Processor Package Dimensions Processor Loading Parameters Signal Listing Order Signal Name Signal Listing Order Number Boxed Processor Heatsink Spatial Dimensions. Heatsink Power Signal Specifications. Signal Description Output Signals. Input Signals Input/Output Signals (Single Driver). Input/Output Signals (Multiple Driver)
Pentium® Processor PGA370 Socket
Introduction
Intel® Pentium® processor PGA370 socket next member family, Intel IA-32 processor line hereafter will referred "Pentium processor", simply "the processor". processor uses same core offers same performance Intel® Pentium® processor SC242 connector, utilizes package technology called flip-chip grid array, FC-PGA. This package utilizes same 370-pin zero insertion force socket (PGA370) used Intel® Celeronprocessor. Thermal solutions attached directly back processor core package without thermal plate heat spreader. Pentium processor, like predecessors family processors, implements Dynamic Execution microarchitecture-a unique combination multiple branch prediction, data flow analysis, speculative execution. This enables these processors deliver higher performance than Intel Pentium processor, while maintaining binary compatibility with previous Intel Architecture processors. processor also executes Intel® MMXtechnology instructions enhanced media communication performance just it's predecessor, Intel Pentium processor. Additionally, Pentium processor executes Streaming SIMD (singleinstruction, multiple data) Extensions enhanced floating point application performance. concept processor identification, CPUID, extended processor family with addition processor serial number. Refer Intel® Processor Serial Number application note more detailed information. processor utilizes multiple low-power states such AutoHALT, Stop-Grant, Sleep, Deep Sleep conserve power during idle times. processor includes integrated on-die, 8-way associative level-two (L2) cache. cache implements Advanced Transfer Cache Architecture with 256-bit wide bus. processor also includes level (L1) instruction cache data cache. These cache arrays full speed processor core. with Intel Pentium processor SC242 connector, Pentium processor PGA370 socket dedicated cache bus, thus maintaining dual independent architecture deliver high bandwidth performance (see Figure Memory cacheable addressable memory space, allowing significant headroom desktop systems. Refer Specification Update document this processor determine cacheability cache configuration options specific processor. Specification Update document requested your nearest Intel sales office. processor utilizes same multiprocessing system technology Pentium processor. This allows higher level performance both uni-processor two-way multiprocessor systems. system uses variant GTL+ signaling technology called Assisted Gunning Transceiver Logic (AGTL+) signaling technology.
Figure Second Level (L2) Cache Implementation
Processor Core Processor Core
Intel Pentium SECC2 Processor
Intel Pentium FC-PGA Processor
Pentium® Processor PGA370 Socket
Terminology
this document, symbol after signal name refers active signal. This means that signal active state (based name signal) when driven level. example, when FLUSH# low, flush been requested. When high, nonmaskable interrupt occurred. case signals where name does imply active state describes part binary sequence (such address data), symbol implies that signal inverted. example, D[3:0] `HLHL' refers `A', D[3:0]# `LHLH' also refers High logic level, logic level). term "system bus" refers interface between processor, system core logic (a.k.a. chipset components), other agents.
1.1.1
Package Processor Terminology
following terms used often this document explained here clarification:
Pentium® processor entire product including internal components. PGA370 socket 370-pin Zero Insertion Force (ZIF) socket which FC-PGA PPGA
packaged processor plugs into.
FC-PGA Flip Chip Grid Array. package technology used Pentium processorfor PGA370 socket.
Advanced Transfer Cache (ATC) cache architecture unique 0.18 micron
Pentium processors. consists microarchitectural improvements that provide higher data bandwidth interface into processor core that completely scaleable with processor core frequency.
Keep-out zone area near FC-PGA packaged processor that system designs
utilize.
Keep-in zone area FC-PGA packaged processor that thermal solutions utilize. OLGA Organic Land Grid Array. package technology core used S.E.C.C.
processors that permits attachment heatsink directly die.
PPGA Plastic Grid Array. package technology used Intel® Celeronprocessors that utilize PGA370 socket.
Processor this document, term processor generic form Pentium
processor PGA370 socket FC-PGA package.
Processor core processor's execution engine. S.E.C.C. processor package technology called "Single Edge Contact Cartridge". Used
with Intel® Pentium® processors.
S.E.C.C. follow-on S.E.C.C. processor package technology. This differs from itpredecessor that extended thermal plate, thus reducing thermal resistance. Used with Intel® Pentium® processors latest versions Intel® Pentium® processor.
SC242 242-contact slot connector (previously referred slot connector) that
S.E.C.C. S.E.C.C. plug into, just Intel® Pentium® processor uses socket cache cache industry designated names.
Pentium® Processor PGA370 Socket
1.1.2
Processor Naming Convention
letter(s) added certain processors (e.g., 600EB MHz) when core freqnency alone uniquely identify processor. Below summary what each letter means well table listing available Pentium processors PGA370 socket. System Frequency Processor with "Advanced Transfer Cache" (CPUID 068xh greater)
Table
Processor Identification
Processor 500E 533EB 550E 600E 600EB 800EB Core Frequency (MHz) System Frequency (MHz) Cache Size (Kbytes) Cache Type2 CPUID1 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh
NOTES: Refer Pentium® Processor Specification Update exact CPUID each processor. Advanced Transfer Cache. Cache integrated same processor core. With ATC, interface between processor core Cache 256-bits wide, runs same frequency processor core enhanced buffering. This item currently POR.
Pentium® Processor PGA370 Socket
Related DocumentThe reader this specification should also familiar with material concepts presented following documents 1,2:
Document AP-485, Intel Order Number 241618 243330 243334 245087 245085 245125 243193 243190 243191 243192 244001 243565 243502 244452 244453 243658 243748 244410 245025
Intel®
Processor Identification CPUID Instruction
AP-585, Pentium Processor GTL+ Guidelines AP-589, Design AP-905, AP-907,
Pentium® Pentium® Intel®
Processor Thermal Design Guidelines Processor Power Distribution Guideline
AP-909,
Processor Serial Number
Intel® Architecture Software Developer's Manual
Volume Basic Architecture Volume Instruction Reference Volume III: System Programming Guide
Family Processors Hardware Developer's Manual
IA-32 Processors Related Products 1999 Databook
Pentium®
Processor Developer's Manual
Pentium Processor Datasheet Pentium® Processor Specification Update
Intel® Intel®
CeleronCeleron
Processor Datasheet Processor Specificiation Update
370-Pin Socket (PGA370) Design GuidelinePGA370 Heat Sink Cooling MicroATX Chassis Intel 810E Chipset Platform Design Guide Intel® Chipset Platform Design Guide Intel® Chipset Platform Design Guide CK98 Clock Synthesizer/Driver Specification
Intel® 810E Chipset Clock Synthesizer/Driver Specification DC-DC Converter Design Guidelines
Pentium Processor PGA370 Socket Buffer Models, XTK/XNS* Format Pentium® Processor BIOS Writer's Guide Extensions Pentium® Processor BIOS Writer's Guide Pentium Thermal/Mechanical Solution Functional Guidelines 245241
Note: Unless otherwise noted, this reference material found Intel Developer's Website located http://developer.intel.com. complete listing Intel® Pentium® processor reference material, please refer Intel Developer's Website This material available through Intel field sales representative.
Pentium® Processor PGA370 Socket
Electrical SpecificationProcessor System VREF
Pentium processor signals variation voltage Gunning Transceiver Logic (GTL) signaling technology. Intel® Pentium® processor system specification similar specification, enhanced provide larger noise margins reduced ringing. improvements accomplished increasing termination voltage level controlling edge rates. This specification different from specification, referred GTL+. more information GTL+ specifications, GTL+ buffer specification Intel® Pentium® Processor Developer's Manual. Current family processors vary from Intel Pentium processor their output buffer implementation. buffers that drive system signals Intel® CeleronTM, Pentium Pentium processors actively driven VCCCORE clock cycle after high transition improve rise times. These signals should still considered open-drain require termination supply that provides high signal level. Because this specification different from standard GTL+ specification, referred AGTL+, Assisted GTL+ this other documentation. AGTL+ logic GTL+ logic compatible with each other both used same system bus. more information AGTL+ routing, appropriate platform design guide. AGTL+ inputs differential receivers which require reference signal (VREF). VREF used receivers determine signal logical logical supplied motherboard PGA370 socket processor core. Local VREF copies should also generated motherboard other devices AGTL+ system bus. Termination (usually resistor each signal trace) used pull high voltage level control reflections transmission line. processor contains on-die termination resistors that provide termination AGTL+ bus, except RESET#. These specifications assume another resistor each signal trace ensure adequate signal quality AGTL+ signals provide backwards compatibility Intel Celeron processor; Table termination voltage specifications AGTL+. Refer Intel® Pentium® Processor Developer's Manual AGTL+ specification. Solutions exist single-ended termination well, though this implementation changes system design eliminate backwards compatibility Intel Celeron processors PPGA package. Single-ended termination designs must still provide AGTL+ termination resistor motherboard RESET# signal. Figure schematic representation AGTL+ topology Pentium processors PGA370 socket. Figure schematic representation AGTL+ topoplogy dualprocessor configuration with Pentium processors PGA370 socket. AGTL+ depends incident wave switching. Therefore, timing calculations AGTL+ signals based flight time opposed capacitive deratings. Analog signal simulation system including trace lengths highly recommended when designing system with heavily loaded AGTL+ bus, especially systems using single termination resistors (i.e., those processor die). Such designs will match solution space allowed installation termination resistors baseboard.
Pentium® Processor PGA370 Socket
Figure AGTL+ Topology Uniprocessor Configuration
Processor
Chipset
Figure AGTL+ Topology Dual-Processor Configuration
Processor
Chipset
Processor
Clock Control Power StateProcessors allow AutoHALT, Stop-Grant, Sleep, Deep Sleep states reduce power consumption stopping clock internal sections processor, depending each particular state. Figure visual representation processor power states.
Figure Stop Clock State Machine
HALT Instruction HALT Cycle Generated Auto HALT ower Down tate BCLK running. Snoops interrupts allowed. INIT#, BINIT#, INTR, RESE ,NMI Norm State Norm execution.
STPCLK# sserted Snoop Event Occurs Snoop Event Serviced STPCLK# De-asserted STPCLK# Asserted STPCLK# De-asserted
rant from
Snoop Event Occurs Snoop Event Serviced
HALT/Grant Snoop State BCLK running. Service snoops caches.
Stop Grant State BCLK running. Snoops interrupts allowed.
SLP# Asserted
SLP# De-asserted
Sleep State BCLK running. snoops interrupts allowed. BCLK Input Stopped BCLK Input Restarted
Deep Sleep State BCLK stopped. snoops interrupts allowed.
PCB757a
Pentium® Processor PGA370 Socket
processor fully realize current consumption Stop-Grant, Sleep Deep Sleep states, Model Specific Register (MSR) must set. 02AH (Hex), must (this power default setting) processor stop internal clocks during these modes. more information, Intel Architecture Software Developer's Manual, Volume System Programming Guide.
2.2.1
Normal State-State
This normal operating state processor.
2.2.2
AutoHALT Powerdown State-State
AutoHALT power state entered when processor executes HALT instruction. processor transitions Normal state upon occurrence SMI#, INIT#, LINT[1:0] (NMI, INTR). RESET# causes processor immediately initialize itself. return from System Management Interrupt (SMI) handler either Normal Mode AutoHALT Power Down state. Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide more information. FLUSH# serviced during AutoHALT state, processor will return AutoHALT state. system generate STPCLK# while processor AutoHALT Power Down state. When system deasserts STPCLK# interrupt, processor returns execution HALT state.
2.2.3
Stop-Grant State-State
Stop-Grant state processor entered when STPCLK# signal asserted. Since AGTL+ signal pins receive power from system bus, these pins should driven (allowing level return VTT) minimum power drawn termination resistors this state. addition, other input pins system should driven inactive state. BINIT# FLUSH# serviced during Stop-Grant state. RESET# causes processor immediately initialize itself, processor stays Stop-Grant state. transition back Normal state occurs with deassertion STPCLK# signal. transition HALT/Grant Snoop state occurs when processor detects snoop system (see Section 2.2.4). transition Sleep state (see Section 2.2.5) occurs with assertion SLP# signal. While Stop-Grant State, SMI#, INIT#, LINT[1:0] latched processor, only serviced when processor returns Normal state. Only occurrence each event recognized serviced upon return Normal state.
Pentium® Processor PGA370 Socket
2.2.4
HALT/Grant Snoop State-State
processor responds snoop transactions system while Stop-Grant state AutoHALT Power Down state. During snoop transaction, processor enters HALT/Grant Snoop state. processor stays this state until snoop system been serviced (whether processor another agent system bus). After snoop serviced, processor returns Stop-Grant state AutoHALT Power Down state, appropriate.
2.2.5
Sleep State-State
Sleep state very power state which processor maintains context, maintains phase-locked loop (PLL), stopped internal clocks. Sleep state only entered from Stop-Grant state. Once Stop-Grant state, SLP# asserted, causing processor enter Sleep state. SLP# recognized Normal AutoHALT states. Snoop events that occur while Sleep State during transition into Sleep state will cause unpredictable behavior. Sleep state, processor incapable responding snoop transactions latching interrupt signals. transitions assertions signals (with exception SLP# RESET#) allowed system while processor Sleep state. transition input signal before processor returned Stop-Grant state will result unpredictable behavior. RESET# driven active while processor Sleep state, held active specified RESET# specification, then processor will reset itself, ignoring transition through Stop-Grant State. RESET# driven active while processor Sleep State, SLP# STPCLK# signals should deasserted immediately after RESET# asserted ensure processor correctly executes reset sequence. While Sleep state, processor capable entering lowest power state, Deep Sleep state, stopping BCLK input (see Section 2.2.6). Once Sleep Deep Sleep states, SLP# deasserted another asynchronous system event occurs. SLP# minimum assertion BCLK period.
2.2.6
Deep Sleep State-State
Deep Sleep state lowest power state processor enter while maintaining context. Deep Sleep state entered stopping BCLK input (after Sleep state entered from assertion SLP# pin). processor Deep Sleep state immediately after BLCK stopped. recommended that BLCK input held during Deep Sleep State. Stopping BCLK input lowers overall current consumption leakage levels. re-enter Sleep state, BLCK input must restarted. period allow stabilization) must occur before processor considered Sleep state. Once Sleep state, SLP# deasserted re-enter Stop-Grant state. While Deep Sleep state, processor incapable responding snoop transactions latching interrupt signals. transitions assertions signals allowed system while processor Deep Sleep state. transition input signal before processor returned Stop-Grant state will result unpredictable behavior.
Pentium® Processor PGA370 Socket
2.2.7
Clock Control
BCLK provides clock signal processor cache. During AutoHALT Power Down Stop-Grant states, processor will process system snoop. processor does stop clock cache during AutoHALT Power Down Stop-Grant states. Entrance into Halt/Grant Snoop state allows cache snooped, similar Normal state. When processor Sleep Deep Sleep states, does respond interrupts snoop transactions. During Sleep state, internal clock cache stopped. During Deep Sleep state, internal clock cache stopped. internal clock cache restarted only after internal clocking mechanism processor stable (i.e., processor re-entered Sleep state). PICCLK should removed during AutoHALT Power Down Stop-Grant states. PICCLK removed during Sleep Deep Sleep states. When transitioning from Deep Sleep state Sleep state, PICCLK must restarted with BCLK.
Power Ground PinThe operating voltage Pentium processor PGA370 socket same core cache; VCCCORE. There four pins defined package voltage identification (VID). These pins specify voltage required processor core. These have been added cleanly support voltage specification variations current future processors. clean on-chip power voltage reference distribution, Pentium processors FC-PGA package have VCCCORE, VREF, VTT, (ground) inputs. VCCCORE inputs supply processor core, including on-die cache. inputs (1.5V) used provide AGTL+ termination voltage processor, VREF inputs used AGTL+ reference voltage processor. Note that inputs must connected supply. Refer Section more details. motherboard, VCCCORE pins must connected voltage island island portion power plane that been divided, entire plane). addition, motherboard must implement pins voltage island large trace. Similarly, pins must connected system ground plane. Three additional power related pins exist processors utilizing PGA370 socket. They VCC1.5, VCC2.5 VCCCMOS. VCCCMOS provides CMOS voltage pull-up resistors required system platform. 2.5V source must provided VCC2.5 1.5V source must provided VCC1.5 pin. source VCC1.5 must same supplying VTT. processor routes compatible CMOS voltage source (1.5V 2.5V) through package VCCCMOS output pin. Processors based 0.25 micron technology (e.g., Intel Celeron processor) utilize 2.5V CMOS buffers. Processors based 0.18 micron technology (e.g., Pentium processor PGA370 socket) utilize 1.5V CMOS buffers. signal VCOREDET used hardware motherboard detect which CMOS voltage processor requires. VCOREDET connected within processor indicates 1.5V requirement VCCCMOS. Refer Figure Each power signal must meet specifications stated Table page
Pentium® Processor PGA370 Socket
Figure Processor VCCCMOS Package Routing
2.5V 2.5V Supply CMOS Intel Pentium Processor 1.5V 1.5V Supply CMOS Signals CMOS Pullups *ICH Other Logic Note: *Ensure this logic compatible with 1.5V signal levels Intel® Pentium processor PGA370 socket.
2.3.1
Phase Lock Loop (PLL) Power
highly critical that phase lock loop power delivery processor meets Intel's requirements. pass filter required power delivery pins PLL1 PLL2. This serves isolated, decoupled power source internal PLL. Please refer Phase Lock Loop Power section appropriate platform design guide recommended filter specifications.
Decoupling GuidelineDue large number transistors high internal clock speeds, processor capable generating large average current swings between full power states. fluctuations cause voltages power planes below their nominal values bulk decoupling adequate. Care must taken board design ensure that voltage provided processor remains within specifications listed Table Failure result timing violations event voltage sag) reduced lifetime component event voltage overshoot). Unlike SC242 based designs, motherboards utilizing PGA370 socket must provide high frequency decoupling capacitors power planes processor.
2.4.1
Processor VCCCORE Decoupling
regulator VCCCORE input must capable delivering dICCCORE/dt (defined Table while maintaining required tolerances (also defined Table Failure meet these specifications result timing violations (during VCCCORE sag) reduced lifetime component (during VCCCORE overshoot).
2.4.2
Processor System AGTL+ Decoupling
processor requires both high frequency bulk decoupling system motherboard proper AGTL+ operation. AGTL+ buffer specification Intel® Pentium® Processor Developer's Manual more information. Also, refer appropriate platform design guide recommended capacitor component placement.
Pentium® Processor PGA370 Socket
Processor System Clock Processor Clocking
BCLK input directly controls operating speed system interface. AGTL+ system timing parameters specified with respect rising edge BCLK input. Family Processors Hardware Developer's Manual further details.
2.5.1
Mixing Processors Differrent FrequencieIn two-way (multi-processor) systems, mixing processors different internal clock frequencies supported been validated. Pentium processors support variable multiplier ratio; therefore, adjusting ratio setting common clock frequency valid. However, mixing processors same frequency different steppings supported. Details support mixed steppings provided Pentium® Processor Specification Update. Note: Pentium processors PGA370 socket validated dual processor (DP) systems. Refer Pentium® Processor Specification Update determine which processors capable.
Voltage Identification
There four voltage identification pins PGA370 socket. These pins used support automatic selection VCCCORE voltages. These pins signals, either open circuit short circuit processor. combination opens shorts defines voltage required processor core. pins needed cleanly support voltage specification variations current future processors. VID[3:0] defined Table this table refers open refers short ground. voltage regulator must supply voltage that requested disable itself. ensure system ready current future processors, range values bold Table should supported. smaller range will risk ability system migrate higher performance processor and/or maintain compatibility with current processors.
Pentium® Processor PGA370 Socket
Table
Voltage Identification Definition
VID3 VID2 VID1 VID0 VccCORE 1.30 1.35 1.40 1.45 1.50 1.55 1.603 1.653 1.703 1.753 1.80 1.85 1.90 1.95 2.00 2.05 Core
NOTES: Processor connected VSS. Open processor; pulled baseboard. ensure system ready Intel® Pentium® Intel® Celeronprocessors, values BOLD Table should supported.
Note that `1111' (all opens) used detect absence processor core given socket long power supply used does affect these lines. Detection logic pull-ups should affect inputs power source (see Section 7.0). pins should pulled TTL-compatible level with external resistors power source regulator only required regulator external logic monitoring VID[3:0] signals. power source chosen must guaranteed stable whenever supply voltage regulator stable. This will prevent possibility processor supply going above specified VCCCORE event failure supply lines. case DC-toDC converter, this accomplished using input voltage converter line pull-ups. resistor greater than equal used connect signals converter input. Note that changes have been made physical connector definitions between Intel-enabled specifications. Intel requires that designs utilize specifications meet Pentium processor requirements.
Pentium® Processor PGA370 Socket
Processor System Unused PinAll RESERVED pins must remain unconnected unless specifically noted. Connection these pins VCCCORE, VREF, VSS, VTT, other signal (including each other) result component malfunction incompatibility with future processors. Section listing processor location each RESERVED pin. PICCLK must driven with valid clock input PICD[1:0] signals must pulled-up VCCCMOS even when APIC will used. separate pull-up resistor must provided each PICD signal. reliable operation, always connect unused inputs bidirectional signals their deasserted signal level. pull-up pull-down resistor values system dependent should chosen such that logic high (VIH) logic (VIL) requirements met. Table specifications non-AGTL+ signals. Unused AGTL+ inputs must properly terminated PGA370 socket motherboards which support Intel Celeron Pentium processors. designs that intend only support Pentium processor, unused AGTL+ inputs will terminated processor's ondie termination resistors thus need terminated motherboard. However, RESET# must always terminated motherboard Pentium processor PGA370 socket does provide on-die termination this AGTL+ input. unused CMOS inputs, active signals should connected through pull-up resistor VCCCMOS meet requirements. Unused active high CMOS inputs should connected through pull-down resistor ground (VSS) meet requirements. Unused CMOS outputs left unconnected. resistor must used when tying bidirectional signals power ground. When tying signal power ground, resistor will also allow system testability.
Processor System Signal GroupTo simplify following discussion, processor system signals have been combined into groups buffer type. family processor system outputs open drain require high-level source provided termination resistors. However, Pentium processor PGA370 socket includes on-die termination. Motherboard designs that also support Intel Celeron processors PPGA package will need provide AGTL+ termination system motherboard well. Platform designs that support dual processor configurations will need provide AGTL+ termination, termination package, socket populated with processor. AGTL+ input signals have differential input buffers which VREF reference signal. AGTL+ output signals require termination this document, term "AGTL+ Input" refers AGTL+ input group well AGTL+ group when receiving. Similarly, "AGTL+ Output" refers AGTL+ output group well AGTL+ group when driving. PWRGOOD, BCLK, PICCLK inputs each driven from ground Other CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, STPCLK#) only tolerant must pulled VCCCMOS. CMOS, APIC, outputs open drain must pulled high VCCCMOS. This ensures correct operation current Intel Pentium Intel Celeron processors. groups signals contained within each group shown Table Refer Section description these signals.
Pentium® Processor PGA370 Socket
Table
System Signal Groups
Group Name AGTL+ Input AGTL+ Output AGTL+ CMOS Input3 CMOS Input4 CMOS Output3 Signals BPRI#, BR1#7, DEFER#, RESET# RS[2:0]#, RSP#, TRDY# PRDY# A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#2, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#, STPCLK# PWRGOOD FERR#, IERR#, THERMTRIP# BCLK PICCLK PICD[1:0] TCK, TDI, TMS, TRST# BSEL[1:0], CLKREF, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL, THERMDN, THERMDP, RTTCTRL8, VCOREDET, VID[3:0], VCC1.5, VCC2.5, VCCCMOS, VCCCORE, VREF, VSS, VTT, Reserved
System Clock4 APIC Clock4 APIC I/O3 Input3 Output3
Power/Other5
NOTES: Section information these signals. BR0# only BREQ# signal that bidirectional. Section more information. internal BREQ# signals mapped onto BR[1:0]# pins after agent determined. These signals specified VccCMOS (1.5 Pentium processor) operation. These signals tolerant. VCCCORE power supply processor core described Section 2.6. VID[3:0] described Section 2.6. used terminate system generate VREF motherboard. system ground. VCC1.5, VCC2.5, VccCMOS described Section 2.3. BSEL[1:0] described Section 2.8.2 Section 7.0. other signals described Section 7.0. RESET# must always terminated motherboard, on-die termination provided this signal. This signal supported processors. Refer Pentium® Processor Specification Update complete listing processors that support this pin. This signal used control value processor on-die termination resistance. Refer platform design guide recommended pulldown resistor value.
2.8.1
Asynchronous Synchronous System SignalAll AGTL+ signals synchronous BCLK. CMOS, Clock, APIC, signals applied asynchronously BCLK. APIC signals synchronous PICCLK. signals synchronous TCK.
Pentium® Processor PGA370 Socket
2.8.2
System Frequency Select Signals (BSEL[1:0])
These signals used select system frequency. Table defines possible combinations signals frequency associated with each combination. frequency determined processor(s), chipset, clock synthesizer. system agents must operate same frequency. Pentium processor PGA370 socket operates system frequency; system operation supported. Individual processors will only operate their specified front side (FSB) frequency, either MHz, both. motherboards that support operation either MHz, BSEL1 signal must pulled logic high resistor located motherboard provided frequency selection signal clock driver/synthesizer. This signal also incorporated into RESET# logic motherboard only operation supported (thus forcing RESET# signal remain active long BSEL1 signal low. BSEL0 signal will float from processor should pulled logic high resistor located motherboard. BSEL0 signal incorporated into RESET# logic motherboard operation unsupported, demonstrated Figure Refer appropriate clock synthesizer design guidelines platform design guide more details frequency select signals. 2-way system design, these BSEL[1:0] signals must connect pins both processors.
Figure BSEL[1:0] Example 100/133 Only System Design
3.3V 3.3V Processor
BSEL0
BSEL1 Note Clock Driver
Note
Note
Chipset
NOTES: Some clock drivers require series resistor their BSEL1 input. Some chipsets connect BSEL[1:0] signals require series resistor. appropriate platform design guide implementation details.
Table
Frequency Select Truth Table BSEL[1:0]
BSEL1 BSEL0 Frequency (unsupported) Reserved
Pentium® Processor PGA370 Socket
Test Access Port (TAP) Connection
voltage levels supported other components Test Access Port (TAP) logic, recommended that processor first chain followed other components within system. translation buffer should used connect rest chain unless other components capable accepting 1.5V input. Similar considerations must made TCK, TMS, TRST# signals. two-way system design, cautious when including empty PGA370 socket scan chain. sockets scan chain must have processor installed complete chain system must support method bypass empty socket; PGA370 termination packages should connect order avoid placing pull-up resistor parallel.
2.10
Maximum RatingTable contains processor stress ratings only. Functional operation absolute maximum minimum implied guaranteed. processor should receive clock while subjected these conditions. Functional operating conditions given tables Section 2.11 through Section 2.13. Extended exposure maximum ratings affect device reliability. Furthermore, although processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields.
Table
Absolute Maximum RatingSymbol TSTORAGE VCCCORE VinAGTL VinCMOS1.5 VinCMOS2.5 IVID ICPUPRES# Parameter Processor storage temperature Processor core voltage termination supply voltage with respect AGTL+ buffer input voltage CMOS buffer input voltage with respect CMOS buffer input voltage with respect current CPUPRES# current -0.5 2.18 2.18 -0.58 2.18 2.18 3.18 Unit Note
NOTES: Input voltage never exceed 2.18 volts. Input voltage never below 2.18 volts. Parameter applies CMOS (except BCLK, PICCLK, PWRGOOD), APIC, signal groups only. Parameter applies CMOS signals BCLK, PICCLK, PWRGOOD only.
Pentium® Processor PGA370 Socket
2.11
Processor SpecificationThe processor specifications this section defined PGA370 socket pins (bottom side motherboard). Section processor signal descriptions Section signal listings. Most signals processor system AGTL+ signal group. These signals specified terminated 1.5V. specifications these signals listed Table page allow connection with other devices, clock, CMOS, APIC, signals designed interface non-AGTL+ levels. specifications these pins listed Table page Table through Table list specifications Pentium processor PGA370 socket. Specifications valid only while meeting specifications junction temperature, clock frequency, input voltages. Care should taken read notes associated with each parameter.
Pentium® Processor PGA370 Socket
Table
Voltage Current Specifications (Sheet
Symbol Parameter Core Freq 500E 533EB 550E 600E 600EB 667B 733B 800EB 1.455 1.365 1.169 1.60 1.65 1.60 1.65 1.65 1.65 1.65 1.65 1.65 1.65 1.65 1.65 1.65 1.65 1.65 1.50 1.50 1.25 1.545 1.635 1.331 Unit Notes ±3%, ±9%, ±2%, ±6.5%,
VCCCORE
processor core
VTT, VCC1.5 VTT, VCC1.5 VREF VCLKREF Baseboard VCCCORE Tolerance, Static Baseboard VCCCORE Tolerance, Transient
Static AGTL+ termination voltage Transient AGTL+ termination voltage AGTL+ input reference voltage CLKREF input reference voltage Processor core voltage static tolerance level PGA370 socket pins Processor core voltage transient tolerance level PGA370 socket pins 500E 533EB 550E 600E 600EB 667B 733B 800EB
-0.080
0.040
-0.130 -0.110
0.080 0.080 10.0 10.6 11.0 12.0 12.0 13.0 13.3 14.0 14.6 15.0 16.0 16.0 16.2 16.3 17.7
ICCCORE
processor core
ICCCMOS ICLKREF IVTT ISGnt ISLP
VccCMOS CLKREF voltage supply current Termination voltage supply current Stop-Grant processor core Sleep processor core
Pentium® Processor PGA370 Socket
Table
Voltage Current Specifications (Sheet
Symbol IDSLP dICCCORE/dt dIvTT/dt Parameter Deep Sleep processor core Power supply current slew rate Termination current slew rate Core Freq Unit A/µs A/µs Table Note
NOTES: Unless otherwise noted, specifications this table apply processor frequencies. specifications this table apply only Pentium processor. motherboard compatibility with Intel® Celeronprocessor, Intel® CeleronProcessor Datasheet. VccCORE IccCORE supply processor core on-die cache. "typical voltage" specification with "tolerance specifications" provide correct voltage regulation processor. Vcc1.5 must held 1.5V while AGTL+ active. required that Vcc1.5 held 1.5V while processor system static (idle condition). range required design target; will come from transient noise added. This measured PGA370 socket pins bottom side baseboard. These tolerance requirements, across frequency bandwidth, measured processor socket soldered-side motherboard. VCCCORE must return within static voltage specification within after transient event; DC-DC Converter Design Guidelines further details. VREF should generated from voltage divider resistors matched resistors. Refer Intel® Pentium® Processor Developer's Manual more details VREF. Maximum measured typical voltage under maximum signal loading conditions. Voltage regulators designed with minimum equivalent internal resistance ensure that output voltage, maximum current output, greater than nominal (i.e., typical) voltage level VccCORE (VccCORE_TYP). this case, maximum current level regulator, IccCORE_REG, reduced from specified maximum current IccCORE _MAX calculated equation: IccCORE_REG IccCORE_MAX (VccCORE_TYP VccCORE_STATIC_TOLERANCE) VccCORE_TYP 10.The current specified current required single processor. similar amount current drawn through termination resistors opposite AGTL+ bus, unless single-ended termination used (see Section 2.1). current specified also AutoHALT state. 12.Maximum values specified design/characterization nominal VccCORE. 13.Based simulation averaged over duration change current. compute maximum inductance tolerable reaction time voltage regulator. This parameter tested. 14.dIcc/dt specifications measured specified PGA370 socket pins. 15.CLKREF must held 1.25V ±6.5%. This tolerance accounts power supply resistor divider tolerance. recommended that motherboard generate CLKREF reference from either 2.5V 3.3V supply. should used risk AGTL+ switching noise coupling this analog reference. 16.Static voltage regulation includes: output initial voltage point adjust, Output ripple noise, Output load ranges specified tables above. 17.FMB Flexible Motherboard recommendation 18.This specification applies PGA370 processors operating frequencies 933MHz higher. 19.Vcc=1.65V Core Stepping (CPUID 0683h); Vcc=1.60V Core Stepping (CPUID 0681h).
Pentium® Processor PGA370 Socket
Table
AGTL+ Signal Groups Specifications
Symbol Parameter Input Voltage Input High Voltage Buffer Resistance Leakage Current inputs, outputs, -0.150 VREF 0.200 VREF 0.200 16.67 ±100 Unit Note
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. inputs, outputs, pins must comply with signal quality specifications Section 3.0. Minimum maximum given Table page +3%) (0VOUT1.5V+3%). Refer processor Buffer Models characteristics. Steady state input voltage must above 1.65V below 1.65V.
Table
Non-AGTL+ Signal Group Specifications
Symbol VIL1.5 VIL2.5 VIH1.5 VIH2.5 Parameter Input Voltage Input Voltage Input High Voltage Input High Voltage Output Voltage Output High Voltage Output Current Input Leakage Current Output Leakage Current ±100 ±100 -0.150 -0.58 VREF 0.200 2.000 VREF 0.200 0.700 3.18 0.400 Unit outputs open-drain Note
NOTES: Unless otherwise noted, specifications this table apply Pentum processors frequencies. Parameter measured (for with inputs). 2.5V +5%). VOUT 2.5V +5%). BCLK specifications, refer Table page 1.5V +3%). VOUT 1.5V +3%). Applies non-AGTL+ signals BCLK, PICCLK, PWRGOOD. Applies non-AGTL+ signals except BCLK, PICCLK, PWRGOOD.
Pentium® Processor PGA370 Socket
2.12
AGTL+ System SpecificationIt recommended that AGTL+ routed daisy-chain fashion with termination resistors VTT. These termination resistors placed electrically between ends signal traces voltage supply generally chosen approximate system platform impedance. valid high levels determined input buffers using reference voltage called VREF. Refer appropriate platform design guide more information Table below lists nominal specification AGTL+ termination voltage (VTT). AGTL+ reference voltage (VREF) generated system motherboard should processor other AGTL+ logic. important that baseboard impedance specified held ±15% tolerance, that intrinsic trace capacitance AGTL+ signal group traces known well-controlled. more details AGTL+ buffer specification, Intel® Pentium® Processor Developer's Manual AP-585, Intel® Pentium® Processor AGTL+ Guidelines.
Table
Processor AGTL+ Specifications
Symbol On-die VREF Parameter Termination Voltage Termination Resistor Reference Voltage 0.950 1.50 1.05 Units Note
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. Pentium processors PGA370 socket contain AGTL+ termination resistors processor die, except RESET# input. Vcc1.5 must held 1.5V ±9%. required that Vcc1.5 held 1.5V while processor system idle (static condition). This measured PGA370 socket pins bottom side baseboard. value on-die determined resistor value measured RTTCTRL signal pin. Section more details RTTCTRL signal. Refer recommendation guidelines specific chipset/processor combination. VREF generated motherboard should nominally. Insure that there adequate VREF decoupling motherboard.
2.13
System SpecificationThe processor system timings specified this section defined socket pins bottom motherboard. Unless otherwise specified, timings tested processor pins during manufacturing. Timings processor pins specified design characterization. Section processor signal definitions. Table through Table list specifications associated with processor system bus. These specifications broken into following categories: Table contains system clock specifications, Table contains AGTL+ specifications, Table contains CMOS signal group specifications, Table contains timings reset conditions, Table covers APIC timing, Table covers timing. processor system specifications AGTL+ signal group relative rising edge BCLK input. AGTL+ timings referenced VREF both logic levels unless otherwise specified.
Pentium® Processor PGA370 Socket
timings specified this section should used conjunction with buffer models provided Intel. These buffer models, which include package information, available Pentium processor FC-PGA package Viewlogic* XTK/XNS* model format (formerly known QUAD format) Pentium Processor PGA370 Socket Buffer Models, XTK/XNS Format (Electronic Format). AGTL+ layout guidelines also available appropriate platform design guide. Care should taken read notes associated with particular timing parameter.
2.13.1
Buffer Model
electronic copy Buffer Model AGTL+ CMOS signals available Intel's Developer's Website (http://developer.intel.com). model single processor designs assumes presence motherboard values described Table page
Table System Specifications (Clock)1,
Parameter System Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time 10.0 ±250 ±250 100.00 133.33 Unit Figure Note
Unless otherwise noted, specifications this table apply Pentium processors frequencies. timings AGTL+ signals referenced BCLK rising edge 1.25V processor pin. AGTL+ signal timings (address bus, data bus, etc.) referenced 1.00V processor pins. internal core clock frequency derived from processor system clock. system clock core clock ratio determined during initialization. Individual processors will only operate their specified system frequency, either MHz, both. Table shows supported ratios each processor. BCLK period allows +0.5 tolerance clock driver variation. appropriate clock synthesizer/ driver specification details. difficulty accurately measuring clock jitter system, recommended that clock driver used that designed meet period stability specification into test load This should measured rising edges adjacent BCLKs crossing 1.25V processor pin. jitter present must accounted component BCLK timing skew between devices. clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point, measured into load, should less than kHz. This specification ensured design characterization and/or measured with spectrum analyzer. appropriate clock synthesizer/driver specification details BCLK Rise time measure between 0.5V-2.0V. BCLK fall time measured between 2.0V-0.5V. BCLK high time measured period time above 2.0V. BCLK time measured period time below 0.5V 10.This specification applies Pentium processors operating system frequency MHz. This specification applies Pentium processors operating system frequency MHz. 12.Not 100% tested. Specified design characterization clock driver requirement.
Pentium® Processor PGA370 Socket
Table Valid System Core Frequency Ratios
Processor 500E 533EB 550E 600E 600EB 800EB Core Frequency (MHz) 800.00 800.00 850.00 866.00 933.00 BCLK Frequency (MHz) 100.00 133.33 100.00 133.33 133.33 Frequency Multiplier 11/2 13/2 11/2 15/2 17/2 13/2 Cache (MHz) 800.00 800.00 850.00 866.00 933.00
NOTE: Contact your local Intel representative latest information processor frequencies and/or frequency multipliers. While other ratios defined, operation frequencies other than those listed supported Pentium processor. Individual processors will only operate their specified system frequency. Either MHz, both.
Pentium® Processor PGA370 Socket
Table System Specifications (AGTL+ Signal Group)1,
Parameter AGTL+ Output Valid Delay AGTL+ Input Setup Time AGTL+ Input Hold Time T10: RESET# Pulse Width 0.40 1.20 0.95 1.00 1.00 3.25 Unit Figure Notes
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. These specifications tested during manufacturing. timings AGTL+ signals referenced BCLK rising edge 1.25V processor pin. AGTL+ signal timings (compatibility signals, etc.) referenced 1.00V processor pins. Valid delay timings these signals specified into 1.5V, VREF with on-die RTT. minimum clocks must guaranteed between active-to-inactive transitions TRDY#. RESET# asserted (active) asynchronously, must deasserted synchronously. 2-way systems, RESET# should synchrounous. Specification minimum 0.40 swing from VREF VREF This assumes edge rate 0.3V/ns. Specification maximum swing from VTT. This assumes edge rate 3V/ns. This should measured after VCCCORE, VTT, VccCMOS BCLK become stable. 10.This specification applies Pentium processor running system frequency. This specification applies Pentium processor running system frequency. 12.BREQ signals system observe minimum setup time.
Table System Specifications (CMOS Signal Group)
Parameter T14: CMOS Input Pulse Width, except PWRGOOD T15: PWRGOOD Inactive Pulse Width Unit BCLKs BCLKs Figure Notes Active Inactive states
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies These specifications tested during manufacturing. These signals driven asynchronously. CMOS outputs shall asserted least BCLKs. When driven inactive after VCCCORE, VTT, VCCCMOS, BCLK become stable.
Pentium® Processor PGA370 Socket
Table System Specifications (Reset Conditions)
Parameter T16: Reset Configuration Signals (A[14:5]#, BR0#, INIT#) Setup Time T17: Reset Configuration Signals (A[14:5]#, BR0#, INIT#) Hold Time Unit BCLKs BCLKs Figure Notes Before deassertion RESET# After clock that deasserts RESET#
NOTES: Unless otherwise noted, specifications this table apply Pentium processor frequencies.
Table System Specifications (APIC Clock APIC I/O)1,
Parameter T21: PICCLK Frequency T22: PICCLK Period T23: PICCLK High Time T24: PICCLK Time T25: PICCLK Rise Time T26: PICCLK Fall Time T27: PICD[1:0] Setup Time T28: PICD[1:0] Hold Time T29a: PICD[1:0] Valid Delay (Rising Edge) T29b: PICD[1:0] Valid Delay (Falling Edge) 30.0 10.5 10.5 0.25 0.25 12.0 33.3 500.0 Unit 1.7V 0.7V (0.7V 1.7V) (1.7V 0.7V) Figure Note
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. These specifications tested during manufacturing. timings APIC signals referenced PICCLK rising edge 1.25 processor pins. APIC signal timings referenced 0.75 processor pins. Referenced PICCLK rising edge. open drain signals, valid delay synonymous with float delay. Valid delay timings these signals specified into load pulled
Pentium® Processor PGA370 Socket
Table System Specifications (TAP Connection)1,
Parameter T30: Frequency T31: Period T32: High Time T33: Time T34: Rise Time 60.0 25.0 25.0 16.667 Unit VREF 0.200V, VREF 0.200V, (VREF 0.200V) (VREF 0.200V),
Figure
Note
T35: Fall Time T36: TRST# Pulse Width T37: TDI, Setup Time T38: TDI, Hold Time T39: Valid Delay T40: Float Delay T41: Non-Test Outputs Valid Delay T42: Non-Test Inputs Setup Time T43: Non-Test Inputs Setup Time T44: Non-Test Inputs Hold Time 13.0 40.0 14.0
(VREF 0.200V) (VREF 0.200V),
Asynchronous,
10.0 25.0 25.0 25.0
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. timings signals referenced rising edge 0.75 processor pins. signal timings (TMS, TDI, etc.) referenced 0.75 processor pins. These specifications tested during manufacturing, unless otherwise noted. added maximum rise fall times every below 16.667 MHz. Referenced rising edge. Referenced falling edge. Valid delay timing this signal specified Non-Test Outputs Inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals operations. During Debug Port operation, normal specified timings rather than signal timings. 10.Not 100% tested. Specified design characterization.
Note:
Figure through Figure following apply: Figure through Figure used conjunction with Table through Table timings AGTL+ signals processor pins referenced BCLK rising edge 1.25 AGTL+ signal timings (address bus, data bus, etc.) referenced 1.00 processor pins. timings APIC signals processor pins referenced PICCLK rising edge 1.25 APIC signal timings referenced 0.75 processor pins. timings signals processor pins referenced rising edge 0.75 signal timings (TMS, TDI, etc.) referenced 0.75 processor pins.
Pentium® Processor PGA370 Socket
Figure BCLK, PICCLK, Generic Clock Waveform
T25, T34, (Rise Time) T26, T35, (Fall Time) T23, T32, (High Time) T24, T33, (Low Time) T22, (BCLK, TCK, PICCLK Period) BCLK referenced 0.5V. referenced 200mV. PICCLK referenced 0.7V. BCLK referenced 2.0V. referenced VREF 200mV. PICCLK referenced 1.7V. BCLK PICCLK referenced 1.25V. referenced
Figure System Valid Delay Timing
Valid T11, T29a, T29b (Valid Delay) T14, (Pulse Width) 1.0V AGTL+ signal group; 0.75V CMOS, APIC signal groups Valid
Signal
Figure System Setup Hold Timing
Valid
Signal
T12, (Setup Time) T13, (Hold Time) 1.0V AGTL+ signal group; 0.75V APIC signal group
Pentium® Processor PGA370 Socket
Figure System Reset Configuration TimingBCLK RESET# Configuration (A20M#, IGNNE#, LINT[1:0]) Configuration (A[14:5]#, BR0#, FLUSH#, INT#) (AGTL+ Input Hold Time) (AGTL+ Input Setup Time) (RESET# Pulse Width) (Reset Configuration Signals (Reset Configuration Signals (Reset Configuration Signals (Reset Configuration Signals (Reset Configuration Signals Safe Valid Valid
(A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) (A20M#, IGNNE#, LINT[1:0]) Hold Time) (A20M#, IGNNE#, LINT[1:0]) Delay Time) (A20M#, IGNNE#, LINT[1:0]) Setup Time)
Figure Power-On Reset Configuration TimingBCLK
PWRGOOD RESET#
Configuration (A20M#, IGNNE#, INTR, NMI) Valid Ratio (PWRGOOD Inactive Pulse) (RESET# Pulse Width) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
Pentium® Processor PGA370 Socket
Figure Test Timings (TAP Connection)
TDI, Input Signal Output Signal
(All Non-Test Inputs Setup Time) (All Non-Test Inputs Hold Time) (TDO Float Delay) (TDI, Setup Time) (TDI, Hold TIme) (TDO Valid Delay) (All Non-Test Outputs Valid Delay) (All Non-Test Outputs Float Time)
Figure Test Reset TimingTRST# 1.25V
(TRST# Pulse Width)
Pentium® Processor PGA370 Socket
Signal Quality SpecificationSignals driven processor system should meet signal quality specifications ensure that components read data properly ensure that incoming signals affect long term reliability component. Specifications provided simulation processor pins. Meeting specifications processor pins Table Table Table ensures that signal quality effects will adversely affect processor operation.
BCLK PICCLK Signal Quality Specifications Measurement GuidelineTable describes signal quality specifications processor pins processor system clock (BCLK) APIC clock (PICCLK) signals. Figure describes signal quality waveform system clock processor pins.
Table BCLK/PICCLK Signal Quality Specifications Simulation Processor Pins
Parameter BCLK PICCLK BCLK PICCLK Absolute Voltage Range BCLK Rising Edge Ringback PICCLK Rising Edge Ringback BCLK Falling Edge Ringback PICCLK Falling Edge Ringback 2.000 2.000 -0.58 2.000 2.000 0.500 0.700 3.18 0.500 0.700 Unit Figure Note
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK/PICCLK signal back after passing (rising) (falling) voltage limits. This specification absolute value.
Pentium® Processor PGA370 Socket
Figure BCLK, PICCLK Generic Clock Waveform Processor PinV3
AGTL+ Signal Quality Specifications Measurement GuidelineMany scenarios have been simulated generate AGTL+ layout guidelines which available appropriate platform design guide. Refer Intel® Pentium® Processor Developer's Manual (Order Number 243502) AGTL+ buffer specification. Table provides AGTL+ signal quality specifications processor simulating signal quality processor pins. Pentium processor PGA370 socket maximum allowable overshoot undershoot specifications given duration time detailed Table through Table Figure shows AGTL+ ringback tolerance Figure shows overshoot/undershoot waveform.
Table AGTL+ Signal Groups Ringback Tolerance Specifications Processor Pins
Parameter Overshoot Minimum Time High Amplitude Ringback Final Settling Voltage Duration Squarewave Ringback 0.50 ±200 Unit Figure Note
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. Specifications edge rate 0.8V/ns. Figure generic waveform. values specified design characterization. Please Table maximum allowable overshoot. Ringback between VREF VREF VREF VREF requires flight time measurements adjusted described Intel AGTL+ Specifications (Intel®Pentium®II Developers Manual). Ringback below VREF above VREF supported. Intel recommends simulations exceed ringback value VREF ±200 allow margin other sources system noise. negative value indicates that amplitude ringback above VREF. (i.e., -100 specifies signal cannot ringback below VREF mV). measured relative VREF. measured relative VREF
Pentium® Processor PGA370 Socket
Figure High AGTL+ Receiver Ringback Tolerance
start Clock
0.7V
Time Note: High case analogoui
AGTL+ Signal Quality Specifications Measurement GuidelineOvershoot/Undershoot GuidelineOvershoot undershoot) absolute value maximum voltage above nominal high voltage below VSS. overshoot guideline limits transitions beyond fast signal edge rates. processor damaged repeated overshoot events tolerant buffers charge large enough (i.e., overshoot great enough). Determining impact overshoot/undershoot condition requires knowledge magnitude, pulse direction activity factor (AF). Permanent damage processor likely result excessive overshoot/undershoot. Violating overshoot/undershoot guideline will also make satisfying ringback specification difficult. When performing simulations determine impact overshoot overshoot, diodes must properly characterized. protection diodes voltage clamps will provide overshoot undershoot protection. diodes modeled within Intel Buffer models clamp undershoot overshoot will yield correct simulation results. other buffer models being used characterize Pentium processor performance, care must taken ensure that models clamp extreme voltage levels. Intel Buffer models also contain capacitance characterization. Therefore, removing diodes from Buffer model will impact results yield excessive overshoot/undershoot.
3.3.1
Pentium® Processor PGA370 Socket
3.3.2
Overshoot/Undershoot Magnitude
Magnitude describes maximum potential difference between signal voltage reference level, (overshoot) (undershoot). While overshoot measured relative using probe (probe signal lead VSS), undershoot must measured relative VTT. This could acomplished simultaneously measuring plane while measuring signal undershoot. Today's oscilloscopes easily calculate true undershoot waveform. true undershoot waveform also obtained with following oscilloscope data file analysis: Converted Undershoot Waveform Signal_measured Note: Note: converted undershoot waveform appears positive (overshoot) signal. Overshoot (rising edge) undershoot (falling edge) conditions separate their impact must determined independently. After true waveform conversion, undershoot/overshoot specifications shown Table through Table applied converted undershoot waveform using same magnitude pulse duration specifications used with overshoot waveform. Overshoot/undershoot magnitude levels must observe Absolute Maximum Specifications listed Table through Table These specifications must violated time regardless activity system state. Within these specifications threshold levels that define different allowed pulse durations. Provided that magnitude overshoot/undershoot within Absolute Maximum Specifications (2.18V), pulse magnitude, duration activity factor must used determine overshoot/undershoot pulse within specifications.
3.3.3
Overshoot/Undershoot Pulse Duration
Pulse duration describes total time overshoot/undershoot event exceeds overshoot/ undershoot reference voltage (Vos_ref 1.635V). total time could encompass several oscillations above reference voltage. Multiple overshoot/undershoot pulses within single overshoot/undershoot event need measured determine total pulse duration. Note: Note: Oscillations below reference voltage substracted from total overshoot/ undershoot pulse duration. Multiple Overshoot/Undershoot events occurring within same clock cycle must considered together event. Using worst case Overshoot/Undershoot Magnitude, together individual Pulse Duraitons determine total Overshoot/Undershoot Pulse Duration that total event.
3.3.4
Activity Factor
Activity Factor (AF) describes frequency overshoot undershoot) occurrence relative clock. Since highest frequency assertion AGTL+ CMOS signal every other clock, indicates that specific overshoot undershoot) waveform occurs EVERY OTHER clock cycle. Thus, 0.01 indicates that specific overshoot undershoot) waveform occurs time every clock cycles. specifications provided Table through Table show Maximum Pulse Duration allowed given Overshoot/Undershoot Magnitude specific Activity Factor. Each Table entry independent others, meaning that Pulse Duration reflects existence overshoot/undershoot events that magnitude ONLY. platform with overshoot/undershoot
Pentium® Processor PGA370 Socket
that just meets pulse duration specific magnitude where means that there other overshoot/undershoot events, even lesser magnitude (note that then event occurs times other events occur). Note: Note: Activity factor AGTL+ signals referenced BCLK frequency. Activity factor CMOS signals referenced PICCLK frequency.
3.3.5
Reading Overshoot/Undershoot Specification TableThe overshoot/undershoot specification Pentium processor PGA370 socket simple single value. Instead, many factors needed determine what over/undershoot specification addition magnitude overshoot, following parameters must also known: junction temperature processor will operating width overshoot measured above 1.635V) Activity Factor (AF). determine allowed overshoot particular overshoot event, following must done: Determine signal group that particular signal falls into. signal AGTL+ signal operating with system bus, Table (100MHz AGTL+ signal group). signal AGTL+ signal operating with 133MHz system bus, Table (133 AGTL+ signal group). signal CMOS signal, Table CMOS signal group). Determine maximum junction temperature (Tj) range processors that system will support (80oC 85oC). Determine Magnitude overshoot (relative VSS) Determine Activity Factor (how often does this overshoot occur?) From appropriate Specification table, read Maximum Pulse Duration allowed. Compare specified Maximum Pulse Duration signal being measured. Pulse Duration measured less than Pulse Duration shown table, then signal meets specifications. above procedure similar undershoots after undershoot waveform been converted look like overshoot. Undershoot events must analyzed separately from Overshoot events they mutually exclusive. Below example showing maximum pulse duration determined given waveform.
Table Example Platform Information
Required Information Signal Group Overshoot Magnitude Activity Factor (AF) Maximum Platform Support AGTL+ 2.13V Measured Value Measured overshoot occurs average every clocks Note
NOTES: Corresponding Maximum Puse Duration Specification Pulse Duration (measured)
Given above parameters, using Table oC/AF column) maximum allowed pulse duration Since measure pulse duration this particular overshoot event passes overshoot specifications, although this doesn't guarantee that combined overshoot/ undershoot events meet specifications.
Pentium® Processor PGA370 Socket
3.3.6
Determining System meets Overshoot/Undershoot SpecificationThe overshoot/undershoot specifications listed following tables specify allowable overshoot/undershoot single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their parameters (duration, magnitude). While each overshoot meet overshoot specification, when total impact overshoot events, system fail. guideline ensure system passes overshoot undershoot specifications shown below. important meet these guidelines; otherwise, contact your Intrel field representative. Insure signal (CMOS AGTL+) ever exceed 1.635V only overshoot/undershoot event magnitude occurs, ensure meets over/undershoot specifications following tables multiple overshoots and/or multiple undershoots occur, measure worst case pulse duration each magnitude compare results against specifications. these worst case overshoot undershoot events meet specifications (measured time specifications) table (where AF=1), then system passes. following notes apply Table through Table
NOTES: Overshoot/Undershoot Magnitude 2.18V Absolute value should never exceeded Overshoot measured relative VSS. Undershoot measured relative Overshoot/Undershoot Pulse Duration measured relative 1.635V. Rinbacks below subtracted from Overshoots/Undershoots Lesser Undershoot does allocate longer larger Overshoot OEM's encouraged follow Intel provided layout guidelines. Consult layout guidelines provided specific platform design guide. values specified design characterization
Table
AGTL+ Signal Group Overshoot/Undershoot Tolerance Processor Pins1,2
Overshoot/ Undershoot Magnitude 2.18 2.13 2.08 2.03 1.98 1.93 1.88 Maximum Pulse Duration (ns) 0.01 2.53 4.93 16.6 0.25 0.49 0.91 1.67 Maximum Pulse Duration (ns) 0.01 18.6 1.86 11.4 0.18 0.32
BCLK period Measurements taken processor socket pins solder-side motherboard.
Pentium® Processor PGA370 Socket
Table AGTL+ Signal Group Overshoot/Undershoot Tolerance
Overshoot/Undershoot Magnitude 2.18 2.13 2.08 2.03 1.98 1.93 1.88 Maximum Pulse Duration (ns) 0.01 12.5 0.19 0.37 0.68 1.25 2.28 Maximum Pulse Duration (ns) 0.01 0.14 0.24 0.46 0.84
BCLK period Measurements taken processor socket pins solder-side motherboard.
Table
CMOS Signal Group Overshoot/Undershoot Tolerance Processor Pins1,
Overshoot/ Undershoot Magnitude 2.18 2.13 2.08 2.03 1.98 1.93 1.88 Maximum Pulse Duration (ns) 0.01 14.8 27.2 0.76 1.48 16.4 Maximum Pulse Duration (ns) 0.01 18.4 0.56 0.96
NOTES: PICCLK period Measurements taken processor socket pins solder-side motherboard.
Pentium® Processor PGA370 Socket
Figure Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
Time Dependent Overshoot 2.18V 2.08V 1.98V 1.88V 1.635V Converted Undershoot Waveform
Overshoot Magnitude
Undershoot Magnitude
Overshoot Magnitude Undershoot Magnitude Signal
Signal
Time Dependent Undershoot
Non-AGTL+ Signal Quality Specifications Measurement GuidelineThere three signal quality parameters defined non-AGTL+ signals: overshoot/undershoot, ringback, settling limit. three signal quality parameters shown Figure nonAGTL+ signal group.
Figure Non-AGTL+ Overshoot/Undershoot, Settling Limit, Ringback
Overshoot Settling Limit
Rising-Edge Ringback
Falling-Edge Ringback
Settling Limit
Time
Undershoot
NOTES: 1.5V non-AGTL+ signals except BCLK, PICCLK, PWRGOOD. BCLK, PICCLK, PWRGOOD. BCLK PICCLK signal quality detailed Section 3.1.
Pentium® Processor PGA370 Socket
3.4.1
Overshoot/Undershoot GuidelineOvershoot undershoot) absolute value maximum voltage above nominal high voltage below VSS. overshoot guideline limits transitions beyond fast signal edge rates (see Figure non-AGTL+ signals). processor damaged repeated overshoot events tolerant buffers charge large enough (i.e., overshoot great enough). Permanent damage processor likely result excessive overshoot/undershoot. Violating overshoot/undershoot guideline will also make satisfying ringback specification difficult. overshoot/undershoot guideline assumes absence diodes input. These guidelines should verified simulations without onchip protection diodes present because diodes will begin clamping tolerant signals beginning approximately above appropriate supply below VSS. signals reaching clamping voltage, this will issue. system should rely diodes overshoot/undershoot protection this will negatively affect life components make meeting ringback specification very difficult. Note: undershoot guideline limits transitions exactly described ATGL+ signals. Figure
3.4.2
Ringback Specification
Ringback refers amount reflection seen after signal switched. ringback specification voltage that signal rings back after achieving maximum absolute value. Figure illustration ringback. Excessive ringback cause false signal detection extend propagation delay. ringback specification applies input each receiving agent. Violations signal ringback specification allowed under circumstances non-AGTL+ signals. Ringback simulated with without input protection diodes that added input buffer model. However, signals that reach clamping voltage should evaluated further. Table signal ringback specifications non-AGTL+ signals simulations processor pins.
Table Signal Ringback Specifications Non-AGTL+ Signal Simulation Processor Pins
Input Signal Group Non-AGTL+ Signals Non-AGTL+ Signals PWRGOOD
Transition
Maximum Ringback (with Input Diodes Present) Vref 0.200 Vref 0.200 2.00
Unit
Figure
NOTES: Unless otherwise noted, specifications this table apply Pentium processor frequencies. Non-AGTL+ signals except PWRGOOD.
3.4.3
Settling Limit Guideline
Settling limit defines maximum amount ringing receiving that signal must reach before next transition. amount allowed total signal swing (VHI -VLO) above below final value. signal should within settling limits final value, when either high state state, before transitions again. Signals that within their settling limit before transitioning risk unwanted oscillations which could jeopardize signal integrity. Simulations verify settling limit done either with without input protection diodes present. Violation settling limit guideline acceptable simulations successive transitions show amplitude ringing increasing subsequent transitions.
Pentium® Processor PGA370 Socket
Thermal Specifications Design ConsiderationThis chapter provides needed data designing thermal solution. However, correct thermal measuring processes, refer AP-905, Intel® Pentium® Processor Thermal Design Guidelines (Order Number 245087). Pentium processor uses flip chip grid array packaging technology junction temperature (Tjunction) specified.
Thermal SpecificationTable provides thermal design power dissipation maximum temperatures Pentium processor PGA370 socket. Systems should design highest possible processor power, even processor with lower thermal dissipation planned. thermal solution should designed ensure junction temperature never exceeds these specifications.
Table Intel® Pentium® Processor PGA370 Socket Thermal SpecificationProcessor Core Frequency (MHz) Cache Size (Kbytes) Processor Thermal Design Power 13.2 14.0 14.5 15.8 15.8 17.0 17.5 18.3 19.1 19.5 20.8 20.8 22.5 22.9 24.5 Power Density5 (W/cm2) 18.2 19.3 20.0 21.8 21.8 23.4 24.1 25.2 26.3 26.9 28.7 28.7 31.0 31.5 33.8 Maximum TJUNCTION (°C) TJUNCTION Offset 3,4,6 (°C)
Processor
500E 533EB 550E 600E 600EB 800EB
NOTES: Thermal Design Power (TDP) represents maximum amount power thermal solution required dissipate. thermal solution should designed dissipate power without exceeding maximum Tjunction specification. does represent power delivery voltage regulation requirements processor. Refer Table voltage regulation electrical specifications. Tjunctionoffset worst-case difference between thermal reading from on-die thermal diode hottest location processor's core. Tjunctionoffset values include thermal diode measurement error. Diode measurement error must added Tjunctionoffset value from table, outlined Pentium® Processor Thermal Design Guidelines. Intel characterized Analog Devices AD1021 diode measurement found measurement error
Pentium® Processor PGA370 Socket
Power density maximum power processor dissipate (i.e., processor power) divided area over which power generated. Power these processors generated from core area shown Figure TJUNCTION offset values include thermal diode measurement error. Diode measurement error must added TJUNCTION offset value from table, outlined Intel® Pentium® processor Thermal Metrology CPUID-068h Family Processors (Order Number: 245301). Intel characterized Analog Devices AD1021 diode measurement found measurement error
Figure block diagram Pentium processor layout. layout differentiates processor core from cache area. effect, thermal design power indentified Table dissipated entirely from processor core area. Thermal solution designs should compensate this smaller heat flux area assume that power uniformly distributed across entire area. Figure Processor Functional Layout
Area (1.046 cm2)
Core Area (0.726 cm2) Cache Area (0.320 cm2)
4.1.1
Thermal Diode
Pentium processor PGA370 socket incorporates on-die diode that used monitor temperature (junction temperature). thermal sensor located motherboard, stand-alone measurement kit, monitor temperature processor thermal management instrumentation purposes. Table Table provide diode parameter interface specifications. Note: reading thermal sensor connected thermal diode will necessarily reflect temperature hottest location die. This inaccuracies thermal sensor, ondie temperature gradients between location thermal diode hottest location given point time, time based variations temperature measurement. Time based variations occur when sampling rate thermal diode thermal sensor) slower than rate which Tjunction temperature change.
Pentium® Processor PGA370 Socket
Table Thermal Diode Parameters1
Symbol Parameter Forward Bias Current Diode Ideality Factor 1.0057 1.0080 1.0125 Unit Note
NOTES: Intel does support recommend operation thermal diode under reverse bias. Characterized 100° with forward bias current ideality factor, represents deviation from ideal diode behavior exemplified diode equation: Ifw=Is(e^ ((Vd*q)/(nkT)) where saturation current, electronic charge, voltage across diode, Boltzmann Constant, absolute temperature (Kelvin). 100% tested. Specified design characterization.
Table Thermal Diode Interface
Name THERMDP THERMDN PGA370 Socket AL31 AL29 Description diode anode (p_junction) diode cathode (n_junction)
Pentium® Processor PGA370 Socket
Mechanical SpecificationThe Pentium processor uses FC-PGA package technology. Mechanical specifications processor given this section. Section 1.1.1 complete terminology listing. processor utilizes PGA370 socket installation into motherboard. Details socket available 370-Pin Socket (PGA370) Design Guidelines. Note: Figure following apply: Unless otherwise specified, following drawings dimensioned inches. dimensions provided with tolerances guaranteed normal production product. Figures drawings labeled "Reference Dimensions" provided informational purposes only. Reference dimensions extracted from mechanical design database nominal dimensions with tolerance information applied. Reference dimensions checked part processor manufacturing. Unless noted such, dimensions parentheses without tolerances reference dimensions. Drawings scale.
FC-PGA Mechanical SpecificationThe following figure with package dimensions provided design heatsink clip solutions well demonstrate where pin-side capacitors will located processor. Table includes measurements these dimensions both inches millimeters.
Figure Package Dimension
Pentium® Processor PGA370 Socket
Table Intel® Pentium® Processor Package DimensionMillimeters Symbol Minimum 3.048 0.431 0.787 1.000 11.226 9.296 Maximum 0.889 1.200 11.329 9.398 Notes Minimum 0.031d 0.039 0.442 0.366 0.925 0.850 1.946 1.790 Nominal 3.302 0.483 Diameter 0.120 0.017 0.100 0.130 0.019 1.954 1.810 0.700 0.700 0.035 Nominal Maximum 0.035 0.047 0.446 0.370 Notes Inche
23.495 21.590 49.428 45.466 0.000 0.000 0.000 2.540 49.632 45.974 17.780 17.780 0.889
0.508 Diameteric True Position (Pin-to-Pin)
0.020 Diameteric True Position (Pin-to-Pin)
NOTES: Capacitors will placed pin-side FC-PGA package area defined This area keepout zone motherboard designers.
bare processor mechanical load limits that should exceeded during heat sink assembly, mechanical stress testing, standard drop shipping conditions. heatsink attach solution must induce permanent stress into processor substrate with exception uniform load maintain heatsink processor thermal interface. package dynamic static loading parameters listed Table Table following apply: recommended portion processor substrate mechanical reference load bearing surface thermal solutions. Parameters assume uniformly applied loads Table Processor Loading ParameterParameter Silicon Surface Silicon Edge Dynamic (max)1 Static (max)2 Unit
NOTES: This specification applies uniform non-uniform load. This maximum static force that applied heatsink clip maintain heatsink processor interface
Pentium® Processor PGA370 Socket
Processor MarkingThe following figure exemplifies processor top-side markings provided identification Pentium processor PGA370 socket. Table lists measurements package dimensions.
Figure Side Processor Marking
Dynamic Production Mark Example
Static Mark printed substrate supplier pentium logo Country Origin
intel
RB80526PY550266 FFFFFFFF-0001 SSSSS
MALAY
S-spec#
Product Code
Dynamic Laser Mark Swatch
Processor Signal Listing
Table Table provide processor definitions. signal locations PGA370 socket used signal routing, simulation, component placement baseboard. Figure provides pin-side view Pentium processor pin-out. following notes apply Table Table
NOTES: These pins required backwards compatibility with other Intel processors. They used Pentium processor. Refer appropriate platform design guide Section implementation details. RESET# signal must connected pins backwards compatibility. Refer appropriate platform design guide Section implementation details. backwards compatibility required, then RESET2# (X4) should connected GND. VCC1.5V must supplied same voltage source supplying pins. These pins must left unconnected (N/C) backwards compatibility with Intel® Celeronprocessors (CPUID 066xh). designs which support Intel Celeron processors (CPUID 066xh), compatibility with future processors, these pins should connected plane. Refer appropriate platform design guide Section implementation details. dual processor designs, these pins must connected VTT. This required backwards compatibility. backwards compatibility required, this left connected VCCCORE. Refer appropriate platform design guide implementation details. Previously, PGA370 designs defined this GND. reserved must left unconnected (N/C). Previously, PGA370 socket designs defined this GND. CLKREF. Uniprocessor designs, this used defined RESERVED. Refer Peniutm® processor Specification Update complete listing processors that support operation.
Pentium® Processor PGA370 Socket
Figure Intel® Pentium® Processor Pinout
RESET RESET2 BERR VREF1 DEP7 Dep7 SLEW CTRL DEP5 DEP3 DEP6 DEP1 DEP4 VREF0 DEP0 DEP2 BPM0 VREF2 PICCLK BPM1 CPUPRES VREF3 LINT0 PICD1 PICD0 PREQ LINT1 VREF4 VREF5 CLKREF PLL1 BCLK VREF6 REQ1 REQ4 REQ0 REQ2 BPRI DEFER REQ3 LOCK VREF7 HIAERR TRDY DBSY PWRGD DRDY TRST THRMDP BSEL1 INIT A20M VID0 VID1
THRMDN VID2
BSEL0 VID3
THERM TRIP
EDGCTRL STPCLK IERR V_1.5 FLUSH IGNNE
FERR
V_CMOS
V_2.5
Side View
PLL2
CTRL
BINIT PRDY
Pentium® Processor PGA370 Socket
Table Signal Listing Order Signal Name (Sheet
AH12 AL15 AH10 AK10 AK14 AE33 AN31 AK24 AL11 AN13 Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADS# AERR# AP0# AP1# BCLK BERR# Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ CMOS Input AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ System Clock AGTL+
Table Signal Listing Order Signal Name (Sheet
AH14 AN17 AN29 AJ33 AJ31 Name BINIT# BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0# BR1#8 BSEL0 BSEL1 CLKREF
Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Input AGTL+ AGTL+ Input Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
CPUPRES# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26#
Pentium® Processor PGA370 Socket
Table Signal Listing Order Signal Name (Sheet
AL27 AN19 Name D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DEP0# Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Input AGTL+
Table Signal Listing Order Signal Name (Sheet
AN27 AC35 AE37 AM22 AM26 AM30 AM34 Name DEP1# DEP2# DEP3# DEP4# DEP5# DEP6# DEP7# DRDY# EDGCTRL FERR# FLUSH# Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power/Other CMOS Output CMOS Input Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Pentium® Processor PGA370 Socket
Table Signal Listing Order Signal Name (Sheet
AB32 AC33 AD34 AF32 AF36 AH34 AJ11 AJ15 AJ19 AJ23 AJ27 AK36 AM10 AM14 AM18 Name Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table Signal Listing Order Signal Name (Sheet
AL25 AL23 AE35 AG37 AG33 AK20 AK26 AK18 AH16 AH18 AL19 AL17 Name HIT# HITM# IERR# IGNNE# INIT# LINT0/INTR LINT1/NMI LOCK# PICCLK PICD0 PICD1 PLL1 PLL2 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ CMOS Output CMOS Input CMOS Input CMOS Input CMOS Input AGTL+ APIC Clock Input APIC APIC Power/Other Power/Other AGTL+ Output CMOS Input CMOS Input AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future
Pentium® Processor PGA370 Socket
Table Signal Listing Order Signal Name (Sheet
AK30 AN23 AH26 AH22 AK28 AC37 AH30 AJ35 AG35 AL33 AN35 AN37 AL29 AL31 AH28 AK32 AN25 AN33 AD36 AB36 AA37 AB34 AD32
Table Signal Listing Order Signal Name (Sheet
AF34 AH24 AH32 AH36 AJ13 AJ17 AJ21 AJ25 AJ29 AK34 AM12 AM16 AM20 Name VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Name Reserved Reserved Reserved BR1#8 RESET# RESET2# RS0# RS1# RS2# RSP# RTTCTRL SLEWCTRL SLP# SMI# STPCLK# THERMDN THERMDP THERMTRIP# TRDY# TRST# VCC1.5
Signal Group Reserved future Reserved future Reserved future AGTL+ Input AGTL+ Input AGTL+ AGTL+ AGTL Input AGTL+ Input AGTL+ Input AGTL+ Input Power/Other Power/Other CMOS Input CMOS Input CMOS Input Input Input Output Power/Other Power/Other CMOS Output Input AGTL+ Input Input Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
VCC2.5 VCCCMOS VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE
Pentium® Processor PGA370 Socket
Table Signal Listing Order Signal Name (Sheet
AM24 AM28 AM32 AL35 AM36 Name VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE RESERVE VID0 VID1 Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table Signal Listing Order Signal Name (Sheet
AL37 AJ37 AK12 AK22 AH20 AK16 AL13 AL21 AN11 AN15 AA33 AA35 AN21 Name VID2 VID3 VREF0 VREF1 VREF2 VREF3 VREF4 VREF5 VREF6 VREF7
Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Pentium® Processor PGA370 Socket
Table Signal Listing Order Number (Sheet
AA33 AA35 AA37 AB32 AB34 AB36 AC33 AC35 AC37 AD32 Name D29# D28# D43# D37# D44# D51# D47# D48# D57# D46# D53# D60# D61# DEP7# DEP3# DEP2# PRDY# A27# A30# VCCCORE VCCCORE VCCCORE A24# A23# VCCCORE VCCCMOS A33# A20# FERR# RSP# A31# VREF5 VCCCORE Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Output Power/Other AGTL+ AGTL+ Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ Power/Other Power/Other Power/Other AGTL+ AGTL+ Power/Other Power/Other CMOS Output AGTL+ Input Power/Other AGTL+ Power/Other Power/Other
Table Signal Listing Order Number (Sheet
AD34 AD36 AE33 AE35 AE37 AF32 AF34 AF36 AG33 AG35 AG37 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AH32 AH34 AH36 Name VCC1.5 A17# A22# VCCCORE A20M# IERR# FLUSH# VCCCORE A35# A25# VCCCORE EDGCTRL A19# INIT# STPCLK# IGNNE# RESET# A10# BNR# REQ1# REQ2# RS1# VCCCORE RS0# THERMTRIP# SLP# VCCCORE VCCCORE A21#
Signal Group Power/Other Power/Other AGTL+ AGTL+ Power/Other CMOS Input CMOS Output CMOS Input Power/Other AGTL+ AGTL+ Power/Other Power/Other Power/Other Power/Other AGTL+ Power/Other CMOS Input CMOS Input CMOS Input Power/Other AGTL+ Input AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power/Other AGTL+ Input Power/Other AGTL Input CMOS Output CMOS Input Power/Other Power/Other Power/Other AGTL+ Power/Other
Pentium® Processor PGA370 Socket
Table Signal Listing Order Number (Sheet
AJ11 AJ13 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AJ33 AJ35 AJ37 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK30 AK32 AK34 AK36 Name VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE BSEL1 BSEL0 SMI# VID3 VCCCORE A28# A11# VREF6 A14# REQ0# LOCK# VREF7 AERR# PWRGOOD RS2# Reserved VCCCORE A15# A13# Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Input Power/Other Power/Other Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ Power/Other AGTL+ AGTL+ Power/Other AGTL+ CMOS Input AGTL+ Input Reserved future Input Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ AGTL+
Table Signal Listing Order Number (Sheet
AL11 AL13 AL15 AL17 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL35 AL37 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AM32 AM34 AM36 AN11 AN13 AN15 AN17 Name AP0# REQ4# REQ3# HITM# HIT# DBSY# THERMDN THERMDP VID0 VID2 Reserved VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VID1 A12# A16# AP1# BPRI# Signal Group AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other Power/Other Input Power/Other Power/Other Reserved future Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ Power/Other AGTL+ Input
Pentium® Processor PGA370 Socket
Table Signal Listing Order Number (Sheet
AN19 AN21 AN23 AN25 AN27 AN29 AN31 AN33 AN35 AN37 Name DEFER#
Table Signal Listing Order Number (Sheet
Name D50# D56# DEP5# DEP1# DEP0# BPM0# CPUPRES# VCCCORE D38# D39# D42# D41# D52# VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE D26# D25# VCCCORE VCCCORE VCCCORE VCCCORE RESERVE D62# SLEWCTRL DEP6# Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ Power/Other AGTL+
Signal Group AGTL+ Input Power/Other AGTL+ AGTL+ Input AGTL+ AGTL+ AGTL+ Input Input Output AGTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
TRDY# DRDY# BR0# ADS# TRST# D35# VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE BINIT# D33# VCCCORE D31# D34# D36# D45# D49# D40# D59# D55# D54# D58#
Pentium® Processor PGA370 Socket
Table Signal Listing Order Number (Sheet
Name DEP4# VREF0 BPM1# BP3# VCCCORE VCCCORE D32# D22# Reserved D27# VCCCORE D63# VREF1 VCCCORE VCCCORE VCCCORE VCCCORE D21# D23# BP2# Reserved D16# D19# VCCCORE VCCCORE D30# VCCCORE PICCLK PICD0 PREQ# Signal Group AGTL+ Power/Other AGTL+ AGTL+ Power/Other Power/Other AGTL+ AGTL+ Reserved future AGTL+ Power/Other AGTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ Power/Other AGTL+ Power/Other Reserved future Power/Other AGTL+ AGTL+ Power/Other Power/Other Power/Other AGTL+ AGTL+ Power/Other APIC Clock Input APIC CMOS Input
Table Signal Listing Order Number (Sheet
Name VCCCORE VREF2 D24# VCCCORE VCCCORE D13# D20# Reserved PICD1 LINT1/NMI D11# VCCCORE LINT0/INTR D14# VCCCORE Reserved Reserved Reserved VCCCORE D18# VCCCORE D12# D10# Reserved Reserved Reserved Reserved D17# VREF3 VCCCORE Signal Group Power/Other Power/Other AGTL+ Power/Other Power/Other Power/Other AGTL+ AGTL+ Power/Other Reserved future APIC CMOS Input Power/Other AGTL+ AGTL+ Power/Other Power/Other CMOS Input AGTL+ AGTL+ Power/Other Reserved future Reserved future Reserved future Power/Other AGTL+ AGTL+ Power/Other Power/Other Power/Other AGTL+ AGTL+ Power/Other Reserved future Reserved future Reserved future Reserved future AGTL+ Power/Other Power/Other
Pentium® Processor PGA370 Socket
Table Signal Listing Order Number (Sheet
Name VCCCORE VCCCORE RTTCTRL
Table Signal Listing Order Number (Sheet
Name VCCCORE A34# VCCCORE PLL1 Reserved BCLK BR1#
Signal Group Power/Other Power/Other AGTL+ AGTL+ Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ Power/Other Power/Other Power/Other AGTL+ AGTL+ Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ Power/Other Power/Other Power/Other
Signal Group Power/Other AGTL+ AGTL+ Power/Other Power/Other Reserved future System Clock AGTL+ input AGTL+ AGTL+ Power/Other Power/Other Power/Other Reserved future AGTL+ Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ Power/Other Power/Other Power/Other
VCCCORE VCCCORE D15# PLL2
RESET2# A32# VCCCORE Reserved A26# CLKREF VCCCORE A29# A18# VCCCORE VCC2.5
BERR# VREF4 VCCCORE
Pentium® Processor PGA370 Socket
Boxed Processor SpecificationThe Intel® Pentium® processor PGA370 socket also offered Intel boxed processor. Intel boxed processors intended system integrators build systems from motherboards standard components. boxed Pentium processor PGA370 socket will supplied with unattached heatsink. This section documents motherboard system requirements heatsink that will supplied with boxed Pentium processor. This section particularly important OEMs that manufacture motherboards system integrators. Unless otherwise noted, figures this section dimensioned inches. Figure shows mechanical representation boxed Intel Pentium processor PGA370 socket Flip Chip Grid Array (FC-PGA) package. Note: Drawings this section reflect only specifications Intel Boxed Processor product. These dimensions should used generic keep-out zone heatsinks. system designer's responsibility consider their proprietary solution when designing required keepout zone their system platform chassis. Refer Intel® Pentium® processor Enabling Functional Specification further guidance. Contact your local Intel Sales Representative this document.
Figure Conceptual Boxed Intel® Pentium® Processor PGA370 Socket
Mechanical SpecificationThis section documents mechanical specifications boxed Pentium processor heatsink.
6.1.1
Boxed Processor Thermal Cooling Solution DimensionThe boxed processor ships with unattached heatsink that integrated clip. Clearance required around heatsink ensure unimpeded airflow proper cooling. Note that airflow heatsink into center sides heatsink. dimensions boxed processor with integrated heatsink shown Figure Figure There versions heatsink. larger cooling solution (depicted right Figure Figure required Pentium processors frequencies above. General spatial specifications also outlined Table dimensions inches.
Pentium® Processor PGA370 Socket
boxed processor heatsink asymmetrical that mechanical step feature (specified Figure must over socket's cam. Note that step allows heatsink securely interface with processor order meet thermal requirements. Figure Side View Space Requirements Boxed Processor
2.68
1.76
1.78 1.78
Figure Side View Space Requirements Boxed Processor
2.00
1.78 1.76
1.93
2.65
Table Boxed Processor Heatsink Spatial DimensionDimensions (Inches) Heatsink Length Heatsink 866MHz Length Heatsink Height Heatsink 866MHz Height Heatsink Width Heatsink 866MHz Width Heatsink height above motherboard Heatsink 866MHz height above motherboard 2.52 2.68 1.76 1.78 2.00 2.65
Pentium® Processor PGA370 Socket
Figure Dimensions Mechanical Step Feature Heatsink Base
0.043
0.472
6.1.2
Boxed Processor Heatsink Weight
boxed processor thermal cooling solution will weigh more than grams.
6.1.3
Boxed Processor Thermal Cooling Solution Clip
boxed processor thermal solution requires installation system integrator secure thermal cooling solution processor after installed 370-pin socket socket. Motherboards designed system integrators should take care consider implications clip installation potential scraping motherboard underneath 370-pin socket attach tabs. Motherboard components should placed close 370-pin socket attach tabs that interferes with installation boxed processor thermal cooling solution (see Figure specification).
Figure Clip Keepout Requirements Boxed Intel® Pentium® Processor4X
1.315
1.315
PGA370S PGA370 DESIGN SPEC.
components 122" Max. Height 060" Max. Height 127" Max. Height Pad1
022" Max. Height
dimensions minimum unless otherwise specified
Pentium® Processor PGA370 Socket
6.2.1
Boxed Processor RequirementFan Heatsink Power Supply
boxed processor's heatsink requires power supply. power cable attached will draw power from power header motherboard. power cable connector pinout shown Figure Motherboards must provide matched power header support boxed processor. Table contains specifications input output signals heatsink connector. cable length inches (±0.25"). heatsink outputs SENSE signal, which open-collector output, that pulses rate pulses revolution. motherboard pull-up resistor provides match motherboard-mounted speed monitor requirements, applicable. SENSE signal optional. SENSE signal used, connector should tied GND. power header baseboard must positioned allow heatsink power cable reach power header identification location should documented motherboard documentation motherboard. Figure shows recommended location power connector relative PGA370 socket. motherboard power header should positioned within 4.00 inches from center PGA370 socket.
Figure Boxed Processor Heatsink Power Cable Connector Description
Signal +12V SENSE Straight square pin, 3-pin terminal housing with polarizing ribs friction locking ramp. 0.100" pitch, 0.025" square width. Waldom/Molex 22-01-3037 equivalent. Match with straight pin, friction lock header motherboard Waldom/Molex 22-23-2031, 640456-3, equivalent.
Table Heatsink Power Signal SpecificationDescription volt power supply current draw SENSE: SENSE frequency (motherboard should pull this appropriate with resistor) pulses revolution 13.8
Pentium® Processor PGA370 Socket
Figure Motherboard Power Header Placement Relative Boxed Intel® Pentium® Processor
0.10"
4.00"
PGA3 Socket7
0.10"
Thermal SpecificationThis section describes cooling requirements thermal cooling solution utilized boxed processor.
6.3.1
Boxed Processor Cooling RequirementThe boxed processor cooled with heatsink. boxed processor heatsink will keep processor core specified Tjunction (see Table 24), provided airflow through heatsink unimpeded. recommended that temperature entering inlet below 45°C (measured inches above hub). Airspace required around ensure that airflow through heatsink blocked. Blocking airflow heatsink reduces cooling efficiency decreases life. Figure shows specification boxed Pentium processor heatsinks 0.20" clearance directions. (This inclusive heatsink used boxed Pentium processors higher.)
Pentium® Processor PGA370 Socket
Figure Thermal Airspace Requirement Boxed Intel® Pentium® Processor Heatsinks PGA370 Socket
.20"
.20"
Pentium® Processor PGA370 Socket
Processor Signal Description
This section provides alphabetical listing Intel® Pentium® processor signals. tables this section summarize signals direction: output, input, I/O.
Alphabetical Signals Reference
Table Signal Description (Sheet
Name Type Description A[35:3]# (Address) signals define 236-byte physical memory address space. When ADS# active, these pins transmit address transaction; when ADS# inactive, these pins transmit transaction type information. These signals must connect appropriate pins agents processor system bus. A[35:24]# signals parity-protected AP1# parity signal, A[23:3]# signals parity-protected AP0# parity signal. active-to-inactive transition RESET#, processors sample A[35:3]# pins determine their power-on configuration. Intel® Pentium® Processor Developer's Manual details. A20M# (Address-20 Mask) input signal asserted, processor masks physical address (A20#) before looking line internal cache before driving read/write transaction bus. Asserting A20M# emulates 8086 processor's address wrap-around boundary. Assertion A20M# only supported real mode. A20M# asynchronous signal. However, ensure recognition this signal following write instruction, must valid along with TRDY# assertion corresponding Write transaction. ADS# (Address Strobe) signal asserted indicate validity transaction address A[35:3]# pins. agents observe ADS# activation begin parity checking, protocol checking, address decode, internal snoop, deferred reply match operations associated with transaction. This signal must connect appropriate pins processor system agents. AERR# (Address Parity Error) signal observed driven processor system agents, used, must connect appropriate pins processor system agents. AERR# observation optionally enabled during power-on configuration; enabled, valid assertion AERR# aborts current transaction. AERR# observation disabled during power-on configuration, central agent handle assertion AERR# appropriate error handling architecture system. AP[1:0]# (Address Parity) signals driven request initiator along with ADS#, A[35:3]#, REQ[4:0]#, RP#. AP1# covers A[35:24]#, AP0# covers A[23:3]#. correct parity signal high even number covered signals number covered signals low. This allows parity high when covered signals high. AP[1:0]# should connect appropriate pins processor system agents. BCLK (Bus Clock) signal determines frequency. processor system agents must receive this signal drive their outputs latch their inputs BCLK rising edge. external timing parameters specified with respect BCLK signal.
A[35:3]#
A20M#
ADS#
AERR#
AP[1:0]#
BCLK
Pentium® Processor PGA370 Socket
Table Signal Description (Sheet
Name Type Description BERR# (Bus Error) signal asserted indicate unrecoverable error without protocol violation. driven processor system agents, must connect appropriate pins such agents, used. However, Pentium processors observe assertions BERR# signal. BERR# BERR# assertion conditions configurable system level. Assertion options defined following options: Enabled disabled. Asserted optionally internal errors along with IERR#. Asserted optionally request initiator transaction after observes error. Asserted agent when observes error transaction. BINIT# (Bus Initialization) signal observed driven processor system agents, used must connect appropriate pins such agents. BINIT# driver enabled during power configuration, BINIT# asserted signal condition that prevents reliable future information. BINIT# BINIT# observation enabled during power-on configuration, BINIT# sampled asserted, state machines reset data which transit lost. agents reset their rotating arbitrati
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