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Error Detection, Power Management, Buffer, JTAG, Pentium, Transistor

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Mobile Pentium® Processor with MMX Technology


SmartDie® Product Specification

Preliminary
Mobile Pentium® Processor with MMX Technology
SmartDie® Product Specification
s Support for MMX Technology s Compatible with Large Software Base s Low Voltage CMOS Silicon Technology s 4 Mbyte Pages for Increased TLB Hit
- MS-DOS, Windows, OS / 2, UNIX s 32-Bit Processor with 64-Bit Data Bus
s Superscalar Architecture
s IEEE 1149.1 Boundary Scan s Internal Error Detection Features s Power Management Features
- Enhanced Pipelines - Two Pipelined Integer Units Are Capable of Two Instructions / Clock - Pipelined MMX Unit - Pipelined Floating Point Unit s Separate Code and Data Caches - 16 Kbyte Code, 16 Kbyte Writeback Data - MESI Cache Protocol s Advanced Design Features - Deeper Write Buffers - Enhanced Branch Prediction Feature - Virtual Mode Extensions
- System Management Mode - Clock Control s Voltage Reduction Technology - 2.45 V VCC for Core Supply - 3.3 V VCC for I / O Buffer Supply s Fractional Bus Operation - 150-MHz Core / 60-MHz Bus - 166-MHz Core / 66-MHz Bus s Intel SmartDie® Product - Full AC / DC Testing at Die Level - 0°C to 105°C (Junction) Temperature Range
NOTICE: This document contains preliminary information on new products in production. It is valid for the devices indicated in "DEVICE NOMENCLATURE" on page 18. This specification is subject to change without notice. Verify with your local Intel sales office that you have the latest product specification before finalizing a design. REFERENCE INFORMATION: The information in this document is provided as a supplement to the standard package datasheet on a specific product. Please refer to the standard package datasheet (order number 243292) for product information and specifications not found in this document.
February 1997
Order Number: 272998-001
Contents
Mobile Pentium® Processor with MMX Technology
SmartDie® Product Specification
1.0 DIE SPECIFICATIONS ............................................................... 1 2.0 INTEL DIE PRODUCTS PROCESSING ................................................. 16 2.1 Wafer Probe ................................................................... 16 2.2 Wafer Saw .................................................................... 16 2.3 Test Procedure ................................................................. 16 2.4 Die Inspection .................................................................. 16 2.5 Packing Procedure .............................................................. 16 2.6 Inspection Steps ................................................................ 16 2.7 Storage Requirements ........................................................... 16 2.8 Electro-Static Discharge (ESD) .................................................... 16 3.0 SPECIFICATIONS .................................................................. 17 3.1 Physical Specifications ........................................................... 17 3.2 DC Specifications ............................................................... 18 4.0 DEVICE NOMENCLATURE .......................................................... 18 5.0 REFERENCE INFORMATION ......................................................... 18 6.0 REVISION HISTORY ................................................................ 18 FIGURES Figure 1. Figure 2. TABLES Table 1. Table 2. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data ............. 3 Mobile Pentium® Processor with MMX Technology Physical Specifications ............ 17 Mobile Pentium® Processor with MMX Technology Die Photo ....................... 1 Mobile Pentium® Processor with MMX Technology Die / Bond Pad Layout .............. 2
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
DIE SPECIFICATIONS
The die photo in Figure 1 and the plot in Figure 2 indicate the orientation of the die in the GEL-PAK (shipping container). Die are aligned as shown
relative to a 45 ° notch which is in one corner of the GEL-PAK. An Intel internal manufacturing name "80P55C " appears on the die. Table 1 describes the bond pad number and pad center data for each signal.
Figure 1. Mobile Pentium® Processor with MMX Technology Die Photo
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Gel-Pak Notch 392 310
X 121 196
Figure 2. Mobile Pentium® Processor with MMX Technology Die / Bond Pad Layout
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Table 1. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data (Sheet 2 of 13) Pad Center(1) PAD# 031 032 033 034 035 036 037 038 039 040 041 042 043 044 045 046 047 048 049 050 051 052 053 054 055 056 057 058 059 060 061 SIGNAL
Microns Y 2713 2619 2525 2431 2337 2243 2149 2055 1961 1867 1773 1679 1585 1491 1397 1303 1209 1115 1021 927 833 739 645 551 457 363 269 175 81 -13 -107
N.C. HOLD WB / WT# VSS VCC2 VCC2 VSS NA# BOFF# N.C. BRDY# VSS VCC2 VCC2 VSS KEN# AHOLD INV EWBE# VSS VCC2 VCC2 VSS VCC3 VSS CACHE# M / IO# VCC3 VSS BP3 BP2
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Table 1. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data (Sheet 3 of 13) Pad Center(1) PAD# 062 063 064 065 066 067 068 069 070 071 072 073 074 075 076 077 078 079 080 081 082 083 084 085 086 087 088 089 090 091 092 SIGNAL
Microns Y -201 -295 -389 -483 -577 -671 -765 -859 -953 -1047 -1141 -1235 -1329 -1423 -1517 -1611 -1705 -1799 -1893 -1987 -2081 -2175 -2269 -2363 -2457 -2551 -2645 -2739 -2833 -2927 -3021
PM1 / BP1 PM0 / BP0 FERR# VSS VCC2 VCC2 VSS IERR# VCC3 VSS DP7 D63 D62 D61 VSS VCC2 VCC2 VSS VCC3 VSS D60 D59 D58 D57 VSS VCC2 VCC2 VSS VCC3 VSS D56
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Table 1. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data (Sheet 4 of 13) Pad Center(1) PAD# 093 094 095 096 097 098 099 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 SIGNAL
Microns Y -3115 -3209 -3303 -3397 -3491 -3585 -3679 -3773 -3867 -3961 -4055 -4149 -4243 -4337 -4431 -4525 -4619 -4713 -4807 -4901 -4995 -5089 -5183 -5277 -5371 -5465 -5559 -5653 -5747 -6232 -6232
DP6 D55 D54 VSS VCC2 VCC2 VSS VCC3 VSS D53 D52 D51 D50 VCC2 VSS VCC3 VSS D49 D48 DP5 D47 VCC3 VSS D46 D45 D44 D43 VSS VCC2 VCC3 VSS
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Table 1. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data (Sheet 5 of 13) Pad Center(1) PAD# 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 SIGNAL
Microns Y -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232
D42 D41 D40 DP4 VCC3 VSS D39 D38 D37 D36 VCC3 VSS D35 D34 D33 D32 VCC3 VSS DP3 D31 D30 D29 VCC3 VSS D28 D27 D26 D25 VCC3 VSS VCC2
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Table 1. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data (Sheet 6 of 13) Pad Center(1) PAD# 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 SIGNAL
Microns Y -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232
VSS D24 DP2 D23 D22 VCC3 VSS D21 D20 D19 D18 VCC3 VSS D17 D16 DP1 D15 VCC3 VSS D14 D13 D12 D11 VCC3 VSS D10 D9 D8 DP0 VCC3 VSS
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Table 1. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data (Sheet 7 of 13) Pad Center(1) PAD# 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207(4) 208(4) 209(4) 210(4) 211 212 213 214 215(4) 216 SIGNAL D7 D6 D5 D4 VCC3 VSS D3 D2 D1 D0 VSS VCC2 VCC2 VSS PICCLK PICD0 PICD1 VCC2 VSS VSS VCC3 TCK TDO TDI TMS VCC2 VSS VSS VCC2 TRST# VSS
Microns Y -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -6232 -5559 -5465 -5371 -5277 -5183 -4901 -4713 -4619 -4525 -4431 -4337 -4243 -4055 -3961 -3867 -3773 -3679 -3585 -3491 -3397 -3303
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Table 1. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data (Sheet 8 of 13) Pad Center(1) PAD# 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 SIGNAL
Microns Y -3209 -3115 -3021 -2927 -2833 -2739 -2645 -2551 -2457 -2363 -2269 -2175 -2081 -1987 -1893 -1799 -1705 -1611 -1517 -1423 -1329 -1235 -1141 -1047 -953 -859 -765 -671 -577 -483 -389
VCC2 VCC2 VSS N.C. N.C. VSS VCC2 VCC2 VSS N.C. N.C. VSS VCC2 VCC2 VSS VSS VSS VCC2 VCC2 VSS N.C. N.C. VSS VCC2 VCC2 VSS N.C. N.C. VCC3 VSS VCC2
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Table 1. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data (Sheet 9 of 13) Pad Center(1) PAD# 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 SIGNAL
Microns Y -295 -201 -107 -13 81 175 269 363 457 551 645 739 833 927 1021 1115 1209 1303 1397 1491 1585 1679 1773 1867 1961 2055 2149 2243 2337 2431 2525
VCC2 VSS STPCLK# N.C. VSS VCC2 VCC2 VSS N.C. BF1 BF0 VSS VCC2 VCC2 VSS N.C. N.C. VSS VCC2 VCC2 VSS N.C.
PEN# INIT IGNNE# VSS VCC2 VCC2 VSS SMI# INTR / LINT0
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Table 1. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data (Sheet 10 of 13) Pad Center(1) PAD# 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 SIGNAL
Microns Y 2619 2713 3089 3183 3277 3371 3465 3559 3653 3747 3841 3935 4029 4123 4217 4311 4405 4499 4593 4687 4781 4875 4969 5063 5157 5251 5345 5439 5533 5627 5721
R / S# NMI / LINT1 N.C. A21 A22 A23 VSS VCC3 VSS VCC2 VCC2 VSS A24 A25 A26 A27 VSS VCC3 A28 A29 A30 A31 VSS VCC3 VCC2 VSS VCC2 VSS VSS N.C. N.C.
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Table 1. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data (Sheet 11 of 13) Pad Center(1) PAD# 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 SIGNAL
Microns Y 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232
VSS VCC2 VCC2 VSS A3 VSS VCC3 A4 A5 VSS VCC3 A6 A7 VSS VCC3 A8 VSS VCC2 VCC2 VSS A9 VSS VCC3 A10 A11 VSS VCC3 A12 VCC2 VSS A13
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Table 1. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data (Sheet 12 of 13) Pad Center(1) PAD# 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 SIGNAL
Microns Y 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232
VSS VCC3 A14 VCC2 VSS A15 VSS VCC3 A16 A17 VSS VCC3 A18 VCC2 VSS A19 VSS VCC3 A20 VCC2 VSS RESET N.C. CLK SCYC VSS VCC3 BE7# BE6# BE5# BE4#
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
Table 1. Mobile Pentium® Processor with MMX Technology Bond Pad Center Data (Sheet 13 of 13) Pad Center(1) PAD# 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 SIGNAL
Microns Y 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232 6232
VSS VCC3 BE3# BE2# BE1# BE0# A20M# FLUSH# BUSCHK# W / R# VSS VCC3 HIT# HITM# VSS VCC3 ADS# EADS# D / C# PWT PCD
NOTES: 1. X-Y coordinates represent pad centers and are relative to center of die. 2. N.C. signifies no connect. These pads must not be connected. 3. The symbol "#" is used to denote active low signals. 4. Boundary Scan (JTAG) is implemented through the following pads: 208 (TDO), 207 (TCK), 209 (TDI), 210 (TMS), 215 (TRST#) 5. FRCMC# - Can use an external pull-up for compatibility with other Pentium processors.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
INTEL DIE PRODUCTS PROCESSING Wafer Probe
Wafer probing is performed on every wafer produced in Intel Fabs. The process consists of specific electrical tests and device-specific functionality tests. At the wafer level, built-in test structures are probed to verify that device electrical characteristics are in control and meet specifications. Measurements are made of transistor threshold voltages and current characteristics poly and contact resistance gate oxide and junction integrity and specific parameters critical to the particular technology and device type. Wafer-to-wafer, across-the-wafer run-to-run variation and conformance to spec limits are checked. The actual devices on each wafer are then probed for both functionality and performance to specifications. Additional reliability tests are also included in the probe steps.
Wafer Saw
Inspection Steps
Test Procedure
Intel has instituted full-speed functional testing and burn-in at the die level for SmartDie products. This level of testing is ordinarily performed only after assembly into a package. Each die is tested and burned-in to the same electrical limits as the equivalent packaged unit.
Die Inspection
Storage Requirements
Upon completion of test and burn-in, the die undergo visual inspection. This process is the same visual inspection as standard packaged product. The compliant die are then transferred to GEL-PAKs for shipment.
Packing Procedure
Intel die products will be shipped in GEL-PAKs and sealed in a moisture-barrier anti-static bag with a desiccant. No special storage procedures are required while the bag is still unopened. Once opened, the GEL-PAK should be stored in a dry, inert atmosphere to prevent corrosion of the bond pads.
Intel will ship all Intel die products in GEL-PAKs. GEL-PAKs eliminate the die edge damage usually associated with die cavity plates or chip trays.
Electro-Static Discharge (ESD)
Components are ESD sensitive.
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Mobile Pentium® Processor with MMX Technology
SPECIFICATIONS
Physical Specifications
Specifications within this document are specific to a particular die revision and are subject to change without notice. Verify with your local Intel Sales Office that you have the latest data before finalizing a design.
Table 2 defines Mobile Pentium® Processor with MMX Technology physical specifications.
Table 2. Mobile Pentium® Processor with MMX Technology Physical Specifications Die Revision: Post-Saw Die Dimensions: Die Thickness: Minimum Pad Pitch: Pad Passivation Opening Size: Bond Pad Metallization: (outermost layer first) Pads per Die: Die Backside Material: (outermost layer first) Passivation: (outermost layer first) Intel Fabrication Process:
NOTE:
The die specifications provided are valid for A-step die only.
PRELIMINARY
Mobile Pentium® Processor with MMX Technology
DC Specifications
NOTICE: This datasheet contains preliminary information on new products in production. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. Verify with your local Intel Sales Office that you have the latest data before finalizing a design. WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
GEL-PAK Storage Temperature ........... 0°C to +70°C Junction Temperature Under Bias ....... -65°C to +110°C 3 V Supply Voltage wrt. VSS ............. -0.5 V to +4.6 V 2.9 V Supply Voltage wrt. VSS ........... -0.5 V to +3.7 V 3 V Only Buffer DC Input Voltage ... -0.5 V to VCC3 + 0.5 V to exceed VCC3 max
OPERATING CONDITIONS
DEVICE NOMENCLATURE
Base Product Number
Bus Speed (MHz)
Core Speed (MHz)
VALID COMBINATIONS: X8050366166 X8050360150
REFERENCE INFORMATION
Document Title Order # 243292
Mobile Pentium® Processor with MMX Technology datasheet
REVISION HISTORY
Revision 001 Date 1 / 97 Initial Release Description
PRELIMINARY