Multi-Rate Framer LXP730 multi-purpose Digital Subscriber Line (D

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Multi-Rate Framer LXP730 multi-purpose Digital Subscriber Line (D

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LXP730
Multi-Rate Framer
LXP730 multi-purpose Digital Subscriber Line (DSL) framer which complements Level SK70725/21 Enhanced MDSL Data Pump (EMDP) provide seamless transport data voice signals over more datapaths.
Applications
LXP730 combination with EMDP chipset optimized framer interface device following applications: Digital Pair Gain Systems Ethernet Modems
T1/E1 Fractional Transport Systems Videoconferencing Systems Simultaneous Data Voice Transport Systems Wireless Base Station Access Systems
Product Features
LXP730 provides basic functions required framer: Synchronization external data streams line Multiplexing demultiplexing independent data streams voice data Loopback payload data interface Creation, insertion, recovery MDSL Overhead (MOH) structure, performance monitoring, message transport required system with capacity kbps
Supports input/output data streams simultaneously Slave mode: external clock determines rate which data will transferred from framer Master mode: clock derived from received clock external oscillator Single part architecture allows chip used economically both central remote locations Supports systems with point-to-point architectures Alternate Hardware Control mode (HWC) operation without external microprocessor
January 2001, this document replaces Level document LXP730 Multi-Rate Framer Datasheet.
Order Number: 249266-001 January 2001
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. LXP730 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2001 *Third-party brands names property their respective owners.
Multi-Rate Framer LXP730
Contents
Assignments Signal Descriptions Functional Description.14
LXP730 Nx64 Framer.14 Time Slot Interchange (TSI) PCM-Bus Interface Codec Interface T1/E1 Interface.17 Asynchronous Data Port Interface (ADPI).17 Overhead Interface.18 2.7.1 Overhead Serial (OSIO) 2.7.2 MDSL Overhead Interface.18 MDSL Interface Digital (ADPLL) 2.9.1 ADPLL Performance: Selection Kloop 2.9.2 ADPLL Center Frequency: computation CFREQ Clock Generation Distribution.21 Modes Operation.22 2.11.1 Microprocessor Control (MPC) Mode.22 2.11.2 Hardware Control (HWC) Mode MDSL Overhead Definition.23 2.12.1 Predefined Overhead 2.12.2 bits.24 MDSL Frame Format.25 Startup Operation Activation State Machine.27 Typical Applications.28 3.1.1 Interface Circuitry 3.1.2 Handling TIP/RING Reversal Early Version SK70725 3.1.3 System Loopbacks 3.1.4 Using Multiple Devices Interrupt Line.32
2.10 2.11
2.12
2.13 2.14 2.15
Application Information
Test Specifications Register Definitions.47
Number MDSL Channels Register MDSL Channel Configuration Registers bytes) 5.2.1 Channel 5.2.2 Channel 5.2.3 Channel 5.2.4 Channel 5.2.5 Channel 5.2.6 Channel 5.2.7 Channel 5.2.8 Channel
LXP730 Multi-Rate Framer
5.10 5.11
5.12 5.13
5.2.9 Channel 5.2.10 Channel 5.2.11 Channel 5.2.12 Channel 5.2.13 Channel 5.2.14 Channel 5.2.15 Channel 5.2.16 Channel 5.2.17 Channel 5.2.18 Channel Reserved Registers bytes). Wander Reduction Register FIFO/Miscellaneous Control Register Slip Buffer Lower Threshold Register Slip Buffer Upper Threshold Register Version Register. Internal Clock Control Registers bytes) 5.9.1 ADPLL Control 5.9.2 ADPLL Control 5.9.3 ADPLL Control 5.9.4 MCLK Divide Programmable Idle Code Byte Configuration Registers. 5.11.1 PCM1 Configuration 5.11.2 PCM2 Configuration Codec Configuration Register Overhead Registers bytes) 5.13.1 Miscellaneous Control 5.13.2 Overhead Configuration 5.13.3 Error Counter. 5.13.4 FEBE Error Counter 5.13.5 FEBE Status 5.13.6 Overhead Bits 5.13.7 Overhead Bits 5.13.8 Overhead Bits 5.13.9 Overhead Bits 5.13.10 Bits 5.13.11 Bits 5.13.12 Bits 5.13.13 Bits 5.13.14 Bits 5.13.15 Bits 5.13.16 Overhead Bits 5.13.17 Overhead Bits 5.13.18 Overhead Bits 5.13.19 Overhead Bits 5.13.20 Bits 5.13.21 Bits 5.13.22 Bits 5.13.23 Bits
Multi-Rate Framer LXP730
5.14 5.15
5.13.24 Bits 5.13.25 Bits Reserved Registers bytes).68 Interrupt Registers bytes).69 5.15.1 Interrupt Enables 5.15.2 Interrupt Status.69
Mechanical Specifications.70
Figures
LXP730 Block Diagram LXP730 Assignments.10 Clock Generation Distribution.22 Frame Format N=12.26 Activation State Machine.27 High Performance Voice/Data Transport Pair Gain Transport T1/E1 Fractional Transport.29 Adaption Circuitry Multiple Interrupt Line Circuit.32 Generic Interface Timing Timing, Clock Timing, Clock Codec Interface Timing Asynchronous Port Timing OSIO Timing.39 MDSL Interface Input Timing.40 MDSL Interface Output Timing.40 E1/T1 Input Timing E1/T1 Output Timing Microprocessor Write Cycle Motorola Mode Microprocessor Read Cycle Motorola Mode Microprocessor Write Cycle Intel Mode Microprocessor Read Cycle Intel Mode Reset Timing LQFP Package Specification
LXP730 Multi-Rate Framer
Tables
LXP730 Descriptions Common Transport Line Rates. Kloop Values Typical ADPLL Register Settings, MCLK 16.384MHz. settings Line Rates. MDSL Frame Sync Word (FSW) Patterns MDSL Frame Format Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Generic Interface Timing Specifications (See Figure 11). Codec Interface Timing Specifications (See Figure Asynchronous Port Timing Specifications (See Figure OSIO Timing Specifications (See Figure MDSL Interface Input Timing Specifications (See Figure MDSL Interface Output Timing Specifications (See Figure E1/T1 Input Timing Specifications (See Figure 19). E1/T1 Output Timing Specifications (See Figure Microprocessor Write Cycle Specifications-Motorola Mode (See Figure 21). Microprocessor Read Cycle Specifications Motorola Mode (See Figure 22). Microprocessor Write Cycle Specifications-Intel Mode (See Figure 23). Microprocessor Read Cycle Specifications-Intel Mode (See Figure MCLK Frequency Tolerance Specification. Reset Timing Specifications (See Figure LXP730 Register Summary. Number MDSL Channels Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Timeslot Channel Reserved Registers. Wander Reduction Register FIFO/Miscellaneous Control Register Slip Buffer Lower Threshold. Slip Buffer Upper Threshold.
Multi-Rate Framer LXP730
Version ADPLL Control ADPLL Control PROG Divide.58 Programmable Idle Code Byte Configuration Bits Configuration Bits Codec Configuration.60 Miscellaneous Control Overhead Configuration Error Counter.62 FEBE Error Counter FEBE Status.62 Overhead Bits Overhead Bits Overhead Bits Overhead Bits Bits 8.64 Bits 16.64 Bits 24.64 Bits 32.65 Bits 40.65 Bits 48.65 Overhead Bits Overhead Bits Overhead Bits Overhead Bits Bits Bits Bits Bits Bits Bits Reserved Registers.68 Interrupt Enables Interrupt Status.69
LXP730 Multi-Rate Framer
Revision History
Revision Date Description
Multi-Rate Framer LXP730
Figure LXP730 Block Diagram
PCM-Bus Interface
Slip Buffer Time Slot Interchange (TSI)
Elastic Store
Codec Interface Shared Async Data Port Interface (ADPI) Registers
Stuff Elastic Store
MDSL Interface
Overhead Serial (OSIO) Interface
Recovered Clock Digital (ADPLL)
Receive Framer
Microprocessor Interface
Clock Generation Distribution
LXP730 Multi-Rate Framer
Assignments Signal Descriptions
Figure LXP730 Assignments
Part
LXP730LE XXXXXX XXXXXXXX
Package Topside Markings Marking Part Unique identifier this product family. Identifies particular silicon "stepping" refer specification update additional stepping information. Identifies batch. Identifies Finish Process Order. Definition
Multi-Rate Framer LXP730
Table
LXP730 Descriptions
Symbol Type1 Power Supply. Description
DATA0/ CRC_ERROR DATA1/FEBE DATA2/ LINK_ACTIVE DATA3/RUNSTOP DATA4/ FRMSYNC15 DATA5/ FRMSYNC16 DATA6/ FRMSYNC17 DATA7/ FRMSYNC18 ADDR0/ FRMSYNC13 ADDR1/N1 ADDR2/N2 ADDR3/N3 ADDR4/N4 ADDR5/ FRMSYNC14 MOTEL/HWC R/W(WR)/HWC select (RD)/HWC select /HWC select ALE/HTU_SEL
Ground. DATA0. mode/CRC_ERROR. flag mode, indicates error detected previous frame. DATA1. mode/FEBE. flag mode, indicates other side link encountered error. DATA2. mode/LINK_ACTIVE. mode, indicates that link active ready transport data. DATA3. mode/RUN-STOP. mode, activate link, edge triggered input. DATA4. mode /FRMSYNC15. mode, Frame Sync Pulse, channel DATA5. mode /FRMSYNC16. mode. Frame Sync Pulse, channel DATA6. mode /FRMSYNC17. mode. Frame Sync Pulse, channel DATA7. mode /FRMSYNC18. mode. Frame Sync Pulse, channel ADDR0. mode/FRMSYNC13. mode. Frame Sync Pulse, channel output. ADDR1. mode/N1. rate select, mode. ADDR2. mode/N2. rate select, mode. ADDR3. mode/N3. rate select, mode. ADDR4. mode/N4. rate select, mode. ADDR5. mode/FRMSYNC14. Frame Sync Pulse, channel output, mode. MOTEL/HWC. high Motorola mode, Intel mode, Micro Processor Control (MPC) mode, input /HWC. pull high mode, input. R/W(WR). Motorola interface, Intel interface /HWC select, mode. (RD). Unused Motorola interface, Intel interface /HWC select, mode. Chip select, select, mode. ALE. Address latch enable Intel interface, mode, input /HTU_SEL. HTUC/ HTUR select, High HTUC, HTUR, mode, input.
DI/O, DI/O, DI/O, DI/O, DI/O, DI/O, DI/O, DI/O,
Analog Input; Analog Output; Digital Input; Digital Output; Clamp. will clamp input absence power; Input contains pull-up; Input contains pull-down; Input/Output; Open Drain Output; Tri-State Output.
LXP730 Multi-Rate Framer
Table
LXP730 Descriptions (Continued)
Symbol RESET MCLK CDATI CDATO Type1 Description INT. Interrupt output. Programmed setting bits INT_EN register. RESET. Active input. registers revert their default values. MCLK. Master Clock. CDATI. Codec Data CDATO. Codec Data Out, Tri-state. CCLK. Codec Clock, Nominal 2.048 MHz, tri-state. /TCLKO. Transport Clock 1.544 2.048 clock derived from line rate. FRMSYNC1. Frame Sync Pulse, channel output. /FRMOUT. Frame Out, T1/E1 application, output. FRMSYNC2. Frame Sync Pulse, channel output. FRMSYNC3. Frame Sync Pulse, channel output. FRMSYNC4. Frame Sync Pulse, channel output. FRMSYNC5. Frame Sync Pulse, channel output. FRMSYNC6. Frame Sync Pulse, channel output. FRMSYNC7. Frame Sync Pulse, channel output. /SDOCK. Serial Data Clock, ADPI serial mode, output. FRMSYNC8. Frame Sync Pulse, channel output. /SDO. Serial Data Out, ADPI serial mode, output. FRMSYNC9. Frame Sync Pulse, channel output. /SDICK. Serial Data Clock, ADPI serial mode, output. FRMSYNC10. Frame Sync Pulse, channel output. /SDI. Serial Data ADPI serial mode, input. FRMSYNC11. Frame Sync Pulse, channel output. FRMSYNC12. Frame Sync Pulse, channel output. /PDOE. Data Output Enable, control external interface buffer, output. Enabled bit-3 Register 23h. GAP_CLK. Gapped Clock, recovered from optional external ADPLL, output. Output high when option selected. TEST1. Factory Test input; should tied GND. TEST2. Factory Test input; should tied VCC. OSDCKI. Overhead Serial Data Clock, output. OSDI. Overhead Serial Data input. OSDOCK. Overhead Serial Data Clock, output. OSDO. Overhead Serial Data Out, output.
CCLK/TCLKO FRMSYNC1/ FRMOUT FRMSYNC2 FRMSYNC3 FRMSYNC4 FRMSYNC5 FRMSYNC6 FRMSYNC7/ SDOCK FRMSYNC8/ FRMSYNC9 SDICK FRMSYNC10/ FRMSYNC11 FRMSYNC12/ PDOE GAP_CLK TEST1 TEST2 OSDICK OSDI OSDOCK OSDO
Analog Input; Analog Output; Digital Input; Digital Output; Clamp. will clamp input absence power; Input contains pull-up; Input contains pull-down; Input/Output; Open Drain Output; Tri-State Output.
Multi-Rate Framer LXP730
Table
LXP730 Descriptions (Continued)
Symbol OSOF OSIF TDATA RDATA QUATCLK BITCLK Type1 Description OSOF. Overhead Serial Output Flag, output. Indicates first OSIO output frame. OSIF. Overhead Serial Input Flag, output. Indicates first OSIO input frame. TDATA. Transmit Data, output. Connect SK70725. RDATA. Receive Data, input. Connect SK70725. QUATCLK. Quaternary alignment Clock, input. Connect SK70725. BITCLK. Clock, input. Connect SK70725. PFRM. frame pulse: input slave, output master. Alignment signal first time slot both PDO. /FRMIN. Frame T1/E1 application, input. /Zo. zero 3-bit word used specify number bits Hardware mode, input. PDI. Data input. /T1E1I. Input data, input. /Z1. 3-bit word used specify number bits Hardware mode, input. PDO. Data Out, tri-stateable output. /T1E1O. Output data, tristateable output. /Z2. 3-bit word used specify number bits Hardware mode, input. PCLK. clock: input slave, output master. /TCLKI. Transport Clock T1/E1 application, 1.544MHZ 2.048MHz input.
PFRM FRMIN
DI,DO,DI
T1E1I
PU,DI, TO,TO,DI
T1E1O
PCLK/TCLKI
DI/O
Analog Input; Analog Output; Digital Input; Digital Output; Clamp. will clamp input absence power; Input contains pull-up; Input contains pull-down; Input/Output; Open Drain Output; Tri-State Output.
LXP730 Multi-Rate Framer
Functional Description
LXP730 Nx64 Framer
LXP730 designed multiplex/demultiplex payload sources to/from stream, add/recover overhead data link control. Several popular interfaces provided support variety applications. major categories payload supported synchronous (i.e. voice-frequency data PCM) asynchronous (i.e. digital data Packet/Cell). LXP730 supports Nx64 kbps channels with LXP730 consists following functional blocks shown page
Time Slot Interchange (TSI) PCM-Bus Interface Codec Interface T1/E1 Interface Asynchronous Data Port Interface (ADPI) Microprocessor Interface Overhead Serial (OSIO) Interface SK70725/SK70721 (MDSL) Interface Digital (ADPLL) Clock Generation Distribution
terms Local Remote used this document designate ends link. Local usually master that initiates link startup control actions configuration Remote. There several equivalent nomenclatures Telecom industry. Some these are, respectively: CPE, HTU-C HTU-R, NTU. following description LXP730 functional blocks.
Time Slot Interchange (TSI)
Time Slot Interchange (TSI) central module LXP730 Nx64 framer. maps payload available N-channels transport across loop. uses register settings select time slots into MDSL channels. total number available payload channels N_MDSL register (00h), with selected valid values from Each registers (01h -012h) used select payload source, applicable, time slot assigned register's corresponding MDSL channel. direction (from MDSL Interface), multiplexes payload sources into elastic store ES). payload overhead multiplexed into stream loop transport.
Multi-Rate Framer LXP730
direction (from MSDL Interface TSI), reads from elastic store demultiplexes loop data into payload data sources. Synchronous payload sources typically 8-bit serial time slots, cascaded together with each source repeating every µsec (i.e. kHz). framing pulse, separate from data signal, signifies start frame. 2.048 Mbps data stream time slot sources, while 1.544 Mbps data stream time slot sources plus extra framing. When codec interfaces running, framing pulses used initialize operation have triple buffering schemes that prevent loss data. PCM/codec interfaces typically produce high speed data bursts while MDSL interface runs slower though irregular rate. Asynchronous data typically sequence bytes which have explicit timing relationship between them. Asynchronous Data Port Interface (ADPI) bytes inserted into payload slots that carrying data. ADPI bytes inserted into stream order they received from interface. Channel blocking MDSL channel achieved setting CH_CFG bits register transported value that MDSL channel will stored IDLE register. uses MCLK clock synchronize various interfaces. MCLK frequency must least three times highest interface clock frequency function properly. There other considerations select operating frequency MCLK when using internal ADPLL.
PCM-Bus Interface
LXP730 provides generic interface common PCM-bus configurations either master slave these busses. Some features that allow flexibility are:
Clock data rate Programmable number bytes frame; Programmable clock frame pulse polarities
These features allow interfacing standard styles such IOM, IOM2 (see Figure circuit) CHI. data rates range from kbps 4096 kbps. clock rates range from 8196 kHz. range permissible time slots 2.048 Mbps backplane 4.096 Mbps backplane total number time slots maximum number time slots must assigned ascending order MDSL channels. value TS-bits registers select timeslot into MDSL channel. There limitation disparity allowed between clock BIT_CLK. rate cannot exceed Mbps. Mbps interface NMDSL setting must least channels. these busses, input output data streams synchronized same clock. slip buffer present receive side accommodate differences clock frequencies ends MDSL line.
LXP730 Multi-Rate Framer
slip buffer frame lengths long. buffer will empty clock reading data slip buffer faster than writing into When last frame been read there another byte from next frame clock out, read pointer back beginning current frame repeated. other slip situation occurs when writing data faster than clocking out. When write pointer gets close read pointer that hasn't finished frame, then read pointer allowed finish current frame then advanced skip next frame. slip buffer bypassed setting SBBP bit, (bit PCM_CFG1, register). Slip occurrences detected signalled Interrupt Status register. Normally LXP730 configured slave Local unit, while Remote LXP730 either configured slave master bus. When Remote LXP730 slave mode, slip buffers accommodate differences clocks. When Remote LXP730 master mode, clock frame pulse derived from receive clock using internal ADPLL provide loop timing prevent slip action from occurring. timeslot assignments channels altered while link active. registers changed without interfering with other registers effect their settings. tri-stated except during programmed time slots. PFRM pulse defines start frame. number time slots frame variable from This programmed setting MAXPCHN bits PCM_CFG2 register, with value number time slots. selection MDSL channel accomplished setting CH_CFG bits register `10' (binary).
Codec Interface
LXP730 primarily supports COMBO codec style devices. LXP730 codec interface programmable allow other codec type devices that require positive frame pulse. LXP730 provides separate pins this interface allowing simultaneous operation with with following characteristics:
Short frame positive sync pulse Clock data rate Programmable number bytes frame MPC;
data rates range from kbps 4096 kbps. clock rates range from 8196 kHz. Under mode, number bytes frame limited input output data from connected codec CDATI CDATO pins appropriate time slot. CDATO tri-stated except during programmed time slots. Only twelve (12) codecs supported mode. LXP730 always master codec bus. LXP730 configured derive clock frame pulse from either MCLK codec Master mode) from clock using internal ADPLL codec Slave mode). LXP730 link must Master codec mode other Slave codec mode.
Multi-Rate Framer LXP730
LXP730 generates codec clock framing pulses eighteen (18) codecs from selected reference. Selecting codec timeslot register corresponds FRMSYNC1, FRMSYNC2, etc. mode, FRMSYNC pins automatically assigned with programming pins. number codec time slots frame variable from This programmed setting MAXCCHN bits COD_CFG register (22h) with value number time slots. Codec selection MDSL channel accomplished setting CH_CFG bits register `00' (binary).
T1/E1 Interface
LXP730 supports T1/E1 framer interfaces using hybrid codec interfaces transport pleisiochronous data. interface used slave mode connect T1/E1 framer TxData (T1E1O), RxData (T1E1I), RxCLK (TCLKI) FramePulseOut (FRMIN). slip buffer must bypass mode. codec interface used slave mode derive FramePulseIn (FRMOUT) TxCLK (TCLKO) T1/E1 framer. derived T1/E1 FRMOUT tracks MDSL frame rate from DSL, cases where framing lost, tracking circuits slowly reacquire prevent drastic change output frame frequency. codec sections must each configured through registers handle T1/E1 pleisiochronous data. only N=12 fractional supported. only workable value PCM_CFG2 register 98h. F-bits must part data stream coming from external framer. unused time slots filled with value programmed IDLE register (bit features T1E1 interface are:
Framer interfaces: DS2141and DS2143 Data rates: 1544 2048 kbps Clock rates: 1544 2048
Asynchronous Data Port Interface (ADPI)
LXP730 supports serial method Asynchronous Data Port Interface (ADPI). ADPI available only operating mode. MDSL channels programmed ADPI setting CH_CFG bits `11' (binary) desired register. operation ADPI mutually exclusive with LXP730 codec frame sync pins (FRMSYNC7-10). serial ADPI mode provides separate pins data data out, clock-in clock-out. This compatible with operation protocol (BOP) HDLC devices. LXP730 controls both clocks, therefore, data flow. LXP730 moves bits 8-bit groups. maximum clock rate bit-to-bit transfer SAPCLKDIV bits FIFO_MISC register. This allows clocks MCLK slower. groups clock pulses will gapped availability positions data stream.
LXP730 Multi-Rate Framer
Overhead Interface
LXP730 provides options interface insert receive overhead data link: external serial interface through microprocessor register interface. data either user defined partially predefined described "MDSL Overhead Definition" page overhead channel used signalling, status flags, loopback control, diagnostic messaging between Local Remote ends MDSL link. LXP730 provides transparent channel overhead data does interpret protocol operation. F-bits fractional mode part overhead.
2.7.1
Overhead Serial (OSIO)
OSIO interface default overhead access both operational modes. serial interface provides separate pins data (OSDI), data (OSDO), clock-in (OSDICK) clock-out (OSDOCK), start flag (OSIF), start flag (OSOF). first four pins compatible with operation protocol (BOP) HDLC devices. flag pins (OSIF OSOF) provide indications start MDSL frame used with custom overhead handling devices. flag signals coincident with first overhead MDSL frame. LXP730 controls both clocks, thus, data flow. clocks will gapped availability positions data stream. OSIO disabled mode setting Par/Ser OVRHD_SEL register (24h). OSIF OSOF will continue operate. defined bits (except indc_r bit) microprocessor interface registers. undefined bits (plus indc_r bit) OSIO interface. This allows separate transport HDLC devices while maintaining performance monitoring.
2.7.2
MDSL Overhead Microprocessor Interface
MDSL overhead microprocessor interface mode uses internal registers provide access insert receive overhead data link. Par/Ser must access contents overhead registers. Interrupts used synchronize contents with MDSL link. data either user defined partially predefined described "MDSL Overhead Definition" page Microprocessor writes defined bits have effect, with exception indc_r bit. registers bits double buffered both sections. When OHMX INT_STAT, 3Fh, register, values user assessable registers latched into internal registers, then serially shift throughout frame. user nominal update registers before they latched again transport. Likewise, registers hold their values until OHDX set, then overhead data from latest frame available. user again nominal read data before over written.
Multi-Rate Framer LXP730
MDSL Interface
Each LXP730 device works directly with SK70725/21 data pump chip set. SK70725/21 chip must Mode work with LXP730. Refer SK70725/21 data sheet details. LXP730 provides TDATA data pump accepts QUATCLK, BITCLK RDATA signals from data pump. framer supports line data rates from kbps 1168 kbps. Table shows some common even-numbered transport, nominal line rates number bits frame. numbered values also used. first value Bits/Frame column number bits unstuffed frame, second value with stuffing. MDSL Frame periods nominal regardless nominal line rate.
Table
Common Transport Line Rates
Data Rate (kbps) 1152 Nominal Line Rate (kbps) 1168 kbps Channels Bits/Frame 1630/1634 2398/2402 3166/3170 3934/3938 4702/4706 7006/7010
line rate calculated kbps kbps, where number kbps channels transported. kbps total overhead provided MDSL transport system. kbps holds true long there block described "MDSL Frame Format" page LXP730 supports eight bits block, when greater than one, overhead rate increases. This causes line rate increase accordingly. equation calculate line rate follows: Line rate (kbps) LXP730 will scramble payload data, pass sync word clear. Local mode, LXP730 uses following scrambling polynomial: x-23 Remote mode scrambling polynomial x-23 x-18 transparent mode, LXP730 uses quat alignment signal (QUATCLK) from data pump align sign magnitude bits both transmit receive directions. overhead bits described "MDSL Overhead Definition" page Before routing data descrambler, LXP730 will invert sign bits received data stream, detected frame sync word inverted sign bits.
LXP730 Multi-Rate Framer
MDSL interface provides loopback TDATA, bypassing external RDATA. Loopback activated setting DSL_LB OVRHD_CFG register (24h). This routes kbps channels MDSL Overhead (MOH) from section section. When using external loopback configuration, such FELB SK70725, necessary switch de-scrambling polynomial polynomial. descrambling polynomial inverted setting REMOTE_LB FIFO_MISC register (17h). BITCLK QUATCLK control transfer data from section.
Digital (ADPLL)
LXP730 ADPLL necessary clock recovery control output jitter wander produced environment. ADPLL uses MCLK drive circuitry, while reference frequency comes from received frame rate that nominal period.
2.9.1
ADPLL Performance: Selection Kloop
performance ADPLL user programmable register. shown Table 5-bit value, Kloop, PLLCTL3 register controls lock time bandwidth ADPLL. lock time amount time required ADPLL acquire synchronize input MDSL signal. bandwidth ADPLL determines jitter rejection characteristics ADPLL. bandwidth lock time inversely related: 3/Tlock.
Table
Kloop Values
Register Bits 00000 00001 00010 00011 00100 11111 Kloop_Value freeze 2-30
Kloop control field found register PLLCTL3 (address hex, dec). register bits used select constant (Kloop_Value) that controls loop bandwidth. Bandwidth loop filter determined from selected Kloop_Value frequency MCLK. Loop bandwidth (BW) calculated follows:
(3db) Kloop_Value MCLK 3.89e-5
Multi-Rate Framer LXP730
2.9.2
ADPLL Center Frequency: computation CFREQ
center frequency ADPLL 18-bit unsigned fractional number, CFREQ(17:0). This value programmed PLLCTL1, PLLCTL2, PLLCTL3. CFREQ(17:0) ratio Numerically Controlled Oscillator (NCO) MCLK, shown below. normalizing factor express integer notation. must then converted hexadecimal load into CFREQ register. output divided before being provided clock multiplex circuitry optional PROG_DIV block. This must taken into account when deciding upon frequency NCO. NCO/MCLK ratio should value greater than equal less than 0.98. This ensures that there will maximum number bits accuracy generate frequency. ratio normalized with 131072 hexadecimal, 20000h. This smallest recommended value.
Equation Calculation CFREQ
NCOFREQ CFREQ ROUND -MCLK
Table list values for: CFREQ(17:0), Programmable Divider, frequency MCLK 16.384MHz several configurations.
2.10
Clock Generation Distribution
LXP730 flexible clock generation circuit shown Figure clocks codec interfaces independent external input, division MCLK, division ADPLL output, ADPLL output selected Configuration register (PCM_CFG1) Codec Configuration register (COD_CFG). port considered slave mode when clock source external pin. frame pulse also sourced from external PFRM when clock configured such. port master mode other three settings. frame pulse derived from internal PCLK driven PFRM pin. codec port initially CCLK tristated until configured output setting CCLK_OE MISC_CTL register. never input. external source codec clock PCLK pin. This allows simultaneous codec interfaces with providing clock allowing MCLK some other frequency that suitable divide down codecs. ADPI clock derived from circuit shown Figure rather comes from module. keeps track opportunities transmit bytes into frame creates burst eight pulses clock byte data insert direction. unloads data from direction also creates burst eight pulses clock byte data external device connected ADPI interface.
LXP730 Multi-Rate Framer
burst frequency ADPI clocks derived from MCLK adjusted SAPCLKDIV (bits register 17h, FIFO_MISC). Table
PCMCLK Output (MHz) 1.544 2.048 1.152 0.896 0.768 0.256
Typical ADPLL Register Settings, MCLK 16.384MHz
Frequency (MHz) PCMCLK PCMCLK PCMCLK PCMCLK PCMCLK PCMCLK PROG_ NCOFREQ/ MCLK 0.754 0.5625 0.875 0.75 CFREQ(17:0) 0x30400 0x20000 0x24000 0x38000 0x30000 0x20000
Figure Clock Generation Distribution
MCLK (pin
Divider Clock Select
Programmable Divider (1E: Clock Select
Port (20:
PCLK (pin
Codec Clock Select
Codec Port (22:
2.11
2.11.1
Modes Operation
Microprocessor Control (MPC) Mode
Microprocessor Control (MPC) mode provides access microprocessor configure control operation framer. LXP730 provides 8-bit data purpose reading writing internal registers. registers used configure framer settings, read write MDSL Overhead bits configure interrupts other run-time operational functions. microprocessor access circuits support both MOTEL (MOTorola/IntEL) microprocessor interfaces. chip select signal activates interface between device microprocessor. Motorola mode, LXP730 supports signals. Motorola signal used this mode. Intel mode, LXP730 supports ALE, signals. Intel mode, data pins conform Intel style Address/Data (AD) functionality.
Multi-Rate Framer LXP730
address presented pins internally latched with ALE, then data either read from written device. held high non-multiplexed address data operation Intel mode signals. interrupt provided. Registers provided enabling/disabling interrupts monitoring status interrupt signals. mode, both Codec/Data Port interfaces used simultaneously. assignment kbps timeslots from interfaces controlled (Time Slot Interchange) block. This feature allows data from different sources transported over DSL.
2.11.2
Hardware Control (HWC) Mode
This mode provides operational method only codec OSIO interface without microprocessor. Pins provided select number kbps channels transported. following Error/Status flags output pins provided: LINK_ACTIVE, CRC_ERR FEBE. RESET, HTUC/HUTR RUN-STOP control signals (input pins) provided. These pins shared with microprocessor mode pins. mode selected pulling pins MOTEL High. Only codec OSIO interfaces accessible mode. first codec frame sync pins active sequence from shown Table pins through used select quantity codecs supported select proper MDSL frame format. used since always even number mode. codec interface runs only 2.048 clock mode.
Table
settings Line Rates
Number MDSL Channels
2.12
MDSL Overhead Definition
MDSL overhead bits carry payload values used exchanging messaging signalling information between ends link. overhead bits divided into categories; bits. bits defined both ETSI ERT/ETS-152 ANSI T1E1.4/94-006 standards. These usually have specific definitions. LXP730, bits partially defined, according standards, totally user definable which referred transparent mode. LXP730 supports bits four modes:
LXP730 Multi-Rate Framer
Transparent register accessible. Transparent OSIO accessible. Partially Predefined register accessible. Partially Predefined OSIO accessible.
reset default overhead mode number modes selected setting bits register 24h, OVRHD_CFG. mode some pre-defined bits' status routed external status pins, i.e. CRC_ERROR, FEBE, LINK_ACTIVE.
2.12.1
Predefined Overhead
Pre-defined bit-fields support: frame sync word, stuff-bits, los, CRC-6, febe, indc_r, bits user defined overhead bits. this mode user write corresponding bits MXOH registers, LXP730 will ignore them insert predefined bits into stream. frame sync word (FSW) pattern consists following bits order from left right: (10101000001000), this generates quat valued sync waveform MDSL. Other valid sync patterns time-reversed, sign inverted, time reversed sign inverted patterns shown Table generation detection automatic. Detection frame that inverted sign causes MDSL block invert sign bits data stream before sent descrambler. Stuff-bits normally either four bits zero bits immediately before sync word next frame. stuffing decision circuit located MDSL Interface block. special mode fixes stuff bits frame applications that require fixed timing such connections from wireless base station remote sites. This controlled register 17h, FIFO_MISC. used notify other side loss source from bus. CRC-6 bits calculated transmitter each frame sent during following frame. receiver CRC-6 calculated received frame, stored then compared with CRC-6 value received following frame. Sync word bits, stuff bits CRC-6 bits CRC-6 calculation. febe side other MDSL unit when CRC-6 error detected side. indc_r side notify other MDSL unit that ready receive transport data.
2.12.2
bits
first three bits MDSL frame reserved loop multi-loop systems ETSI standard. other bits user defined. common send time slot configuration from Local unit Remote unit.
Multi-Rate Framer LXP730
bits either accessed through registers OSIO interface. This controlled Z_CTL register 23h, MISC_CTL. When bits both through OSIO, they order listed frame structure Table example: transparent bits through OSIO, then order MDSL frame bits, bits, bits, bits, bits, bits, bits, bits. Switching predefined, corresponding predefined bits would appear OSIO there would those time locations. mode bits user definable bits through OSIO. When LXP730 fractional mode, bits part payload accessible, otherwise they accessible registers.
2.13
MDSL Frame Format
LXP730 transport frame format that adjusts automatically with setting. overall structure remains constant while adjusting number time slots within payload blocks. Table Figure shows overall frame format.
Table
MDSL Frame Sync Word (FSW) Patterns
Type Pattern Normal Time-reversed Inverted-Sign-Bit Inverted-Sign-Time-Reversed Bits 10101000001000 00100000101010 00000010100010 10001010000000 Quat Value
Table
MDSL Frame Format
Description Sync Word B1-B12 B13-B24 B25-B36 B37-B48 Stuff Number Bits
frame made sync word, followed alternating sets MDSL Overhead bits groups data blocks. final element each frame section aside stuffing, used synchronize payload with framing where required.
LXP730 Multi-Rate Framer
Each data block contains bits. blocks transmitted groups mode Z-bits block group reserved framing/signalling referred fbits. other modes they user accessible overhead bits known Z-bits. frame structure matches kbps structure adopted T1E1 ETSI. N=18 Z=1, frame format follows that 1168 kbps HDSL system compliant with ETSI standards.
2.14
Startup Operation
This description applies mode LXP730. Typically user sets most desired register values then sets register 24h, OVRHD_CFG. this point side framer sending data TDATA side looking FSW. next step requires clearing INT_STAT register writing OxFF must ensured that SK70725/21 chipset either Master Slave mode needed. SK70725/21 chipset needs reset ACTIVATE toggled SK70725/21 chipsets. main control register toggled. Master mode, SK70725/21 will start activation sequence with Slave responding. seconds data pumps will have their filter echo coefficients switch transparent transport mode. There additional setup consider when LXP730 slave mode N=18. there clock running, then there halt condition when time slots selected. work around temporarily last registers codec configuration, then bit. Once that done then change registers back desired configuration.
Figure Frame Format N=12
MDSL Frame (784k):
SYNCH 1164 BLKS 1164 BLKS 1164 BLKS 1164 BLKS STUFF
msec
MDSL Block (784k):
side LXP730 will ACTIVE upon receipt successive MDSL frames. When this first occurs, ACTIVE INT_STAT set, will stay reset once cleared until framer goes inactive back active again. ACTIVE edge triggered. DSLACTIVE CRC_FEBE_ST level triggered `sticky'. Once active, support required keep operating. this point there basically tasks perform: monitor error conditions, overhead pass messages/ signalling between Local Remote units.
Multi-Rate Framer LXP730
Most registers/bits changed while with following exceptions:
N_MDSL register TX8KSSEL
FIFOs (MXFIFORXT DXFIFORXT) should reset whenever codec clocks changed while framer mode. This will cause interruption payload, link will stay
2.15
Activation State Machine
LXP730 framer ANSI T1E1.4/94-006 compatible activation state machine. operation state machine shown Figure
Figure Activation State Machine
Sync Initial "Out-of-Sync" State ACTIVE
Sync RUN/ STOP Sync Sync with Change Frame Alignment Sync
Sync
Sync (COFA
Sync
Sync
Sync
Sync State ACTIVE
Sync State ACTIVE Sync
Sync Sync Sync Sync Sync
Sync
Sync Sync with Change Frame Alignment
COFA
Sync COFA
LXP730 Multi-Rate Framer
Application Information
Typical Applications
This section shows some block diagrams serve example applications. Connections LXP730 shown emphasize those relevant application. Detailed connections processor shown. Figure demonstrates LXP730 simultaneously handle voice from circuit packet-type data from HDLC style device. Figure example mode. codecs' digital interfaces connect directly LXP730. external device needed handle signalling information each voice line supported. this case bits could used carry signalling information such off-hook status from ringing signal from FPGA fast dedicated processor could handle these tasks.
Figure High Performance Voice/Data Transport
2.048/4.096 Mbps Highway PCLK PFRM HDLC TDATA RDATA LXP730 Framer
ADPI
QUATCLK BIT_CK
SK70725/21 Data Pump
Router
Microprocessor
Packet/Cell Data Transceiver LXT905 Nx64 kbps Channels
Multi-Rate Framer LXP730
Figure Pair Gain Transport
2.048 Mbps Highway CDATI CDATO CCLK TDATA RDATA QUATCLK BITCLK ACTIVE Combo Codec
SK70725/21 Data Pump
FRM1
LXP730 Framer
Signalling Control Combo Codec Indicators FRMn
kbps Voiceband Channels
Figure shows more traditional application carry phone traffic over longer distance single copper pair. LXP730 supports pleisiochronous nature T1/E1 traffic.
3.1.1
Interface Circuitry
LXP730 uses frame pulse second cycle clocks data timing. This directly compatible with electrical interface. interfaces first clock cycle frame pulse. circuit Figure shows adapt LXP730 bus. Note that even though circuit same master slave modes, there difference connections LXP730 device.
Figure T1/E1 Fractional Transport
PFRM PDATI PCLK T1/E1 Framer FRM1 CCLK LXP730 Framer TDATA RDATA QUATCLK BITCLK SK70725/21 Data Pump
Microprocessor
LXP730 Multi-Rate Framer
Figure Adaption Circuitry
LXP730 Master PCM_FS_POS PFRM PFRM Delayed
PCLK
74HC74
74HC74
Master FRAME
LXP730 Slave PCM_FS_POS PFRM
PCLK
74HC74
74HC74
3.1.2
Handling TIP/RING Reversal Early Version SK70725
early version SK70725 data pump device error Master (CO) mode. QUAT_CLK aligned correctly with RDATA sign magnitude bits. When there TIP/RING reversal, LXP730 able correctly parse data bits. However, when TIP/ RING reversal occurred LXP730 detects that sign inverted detecting inverted Frame Sync Word (FSW) pattern. LXP730 then uses QUAT_CLK determine which invert. sign already inverted LXP730 inverts magnitude bit. This problem does occur Slave (CPE) mode SK70725. SK70725 ability invert received data pulses inside itself. This done setting register WR2. following procedure takes advantage LXP730 reacts during error condition ability invert data stream from SK70725. procedure uses Z-bit bytes after frame sync been achieved determine there tip-ring reversal LTU. DXZ2 MXZ2 good choices used only start time. TIP/RING reversal indicator SK70725 does have meaning mode transparent mode needed work with LXP730. This procedure left code future SK70725 revision. procedure also shows handle BELB from end. TIP/RING Reversal Procedure: Start. Initialize LXP730s required configuration. Activate SK70725s. Send test pattern MXZ2 from side. MXZ2 AAh. DXZ2 received TIP/RING lines straight system ready transmission. step
Multi-Rate Framer LXP730
Otherwise DXZ2 55h, register SK70725 (Address data 80h). register LXP730 stop then this back re-start. framer needs restarted recognize sync word. TIP/RING lines reversed corrected SK70725, system ready transmission. Normal operation. BELB (Back Loop Back) side: Send message side SK70725 BELB (set register SK70725 side). TIP/RING detected straight then register LXP730 (Address 57h, data 10h) step BELB completed system ready transmission. TIP/RING reversal detected corrected side, then register SK70725. register LXP730 (Address 57h, data 10h). register LXP730 stop then this back re-start. BELB completed system ready transmission. When BELB testing done, reset register LXP730 send command undo BELB. Before shuts BELB received payload overhead data will scrambled with wrong polynomial value DXZ2 will jump. wait until there consecutive frames where DXZ2 AAh. step
3.1.3
System Loopbacks
Data loopbacks telecom systems primarily used system diagnostics. These tests usually either (Bit Error Rate), determine which part system malfunctioning. systems loopback points usually controlled (Central Office) end. Line cards have more loops, processor board sets loopback operation; typically command from central control point switching system. loopback linecard demonstrates that data successfully moved from input section through section receive side payload. Typically this done with data pump Front Loop Back (FELB). This transmits data onto wire pair, receive signal from wire pair ignored. Instead, receiver signal from transmitter internal multiplexer. framer also loop back that ignores data from data pump. This useful isolating data pump source malfunction such when line been lightning. back loopback (BELB) used test wire pair remote data pump. Here RDATA from data pump passed framer still receive commands from such turn BELB. payload loopback remote line card will check framer give more complete evaluation system. each different scrambling polynomial their transmitted data. Each side expects receive different scrambling setting than they transmit. When framer loopback knows switch receive scrambler match transmitter. When local
LXP730 Multi-Rate Framer
FELB framer does know itself that receive scrambler switched. Switching accomplished LXP730 setting REMOTE_LB register 17h. This also needs done when remote BELB operation. When remote switches BELB will correctly interpret data until REMOTE_LB turned off. However will still recognize because scrambled.
3.1.4
Using Multiple Devices Interrupt Line
LXP730 output therefore requires circuit, shown Figure operate with additional devices that share same interrupt line microprocessor. Each LXP730 that tied shared interrupt line will need isolating diode.
Figure Multiple Interrupt Line Circuit
LXP730
Interrupt Line Pull-up
1N4148 equivalent
LXP730
1N4148 equivalent
other device interrupt pins
Multi-Rate Framer LXP730
Note:
Test Specifications
Table through Table Figure through Figure represent performance specifications LXP730 guaranteed test except, where noted, design. minimum maximum values listed Table through Table guaranteed over recommended operating conditions specified Table Absolute Maximum Ratings
Parameter Symbol -0.3 +150 Unit
Table
Supply voltage Storage temperature
Caution: Exceeding these values cause permanent damage. Functional operation under these conditions implied. Exposure maximum rating conditions extended periods affect device reliability.
Table
Recommended Operating Conditions
Parameter Typ1 Unit
Recommended supply voltage Recommended operating temperature Power dissipation
Typical figures design only; guaranteed subject production testing.
Table Electrical Characteristics
Parameter Input voltage Input High voltage Output voltage Output High voltage Input current Input High current Output rise/fall time Capacitance, input 0.7xVCC 0.7xVCC Typ1 0.3xVCC Unit Test Conditions CMOS inputs CMOS inputs Gnd, 5.5V VCC, 5.5V CLOAD
Typical values design only; guaranteed subject production testing.
LXP730 Multi-Rate Framer
Figure Generic Interface Timing
tCP1
PCLK1 PCLK2
tCH1 tCP2 tCL2
tCL1
tCH2
tFPW
PFRM
tFSU
tFHT
NOTES: PCLK1 clock, PCLK2 clock. Clock sampling edges frame pulse polarity programmable.
Table Generic Interface Timing Specifications (See Figure
Parameter PCLK period PCLK duty cycle input PCLK duty cycle output (MCLK) PCLK duty cycle output (ADPLL) delay time setup time hold time PFRM setup time PFRM hold time PFRM pulse width Typ1 Note 3906 Unit Test Conditions
tCP1 tCP2
tFSU tFHT tFPW
Typical values design only; guaranteed subject production testing. Jitter PCLK frequency MCLK frequency.
Multi-Rate Framer LXP730
Figure Timing, Clock
Clocks shown with arrow indicating sampling edge data FE=0, FS_POS=0 DCE=0 DATA FE=0, FS_POS=1
FE=1, FS_POS=0 DCE=1 DATA FE=1, FS_POS=1
FE=1, FS_POS=0 DCE=0 DATA FE=1, FS_POS=1
FE=0, FS_POS=0 DCE=1 DATA FE=0, FS_POS=1
LXP730 Multi-Rate Framer
Figure Timing, Clock
Clocks shown with arrow indicating sampling edge data FE=0, FS_POS=0 DCE=0 DATA FE=0, FS_POS=1
FE=1, FS_POS=0 DCE=1 DATA FE=1, FS_POS=1
FE=1, FS_POS=0 DCE=0 DATA FE=1, FS_POS=1
FE=0, FS_POS=0 DCE=1 DATA FE=0, FS_POS=1
Multi-Rate Framer LXP730
Figure Codec Interface Timing
CDATO
CCLK
FRAMESYNCk
CDATI
Table Codec Interface Timing Specifications (See Figure
Parameter Output delay time CDATO, FRAMESYNCk Codec clock period CCLK duty cycle output (MCLK) CCLK duty cycle output (ADPLL) CDATI setup CDATI hold time Typ1 Note 3906 Unit Test Conditions Referenced from rising edge CCLK
Referenced from falling edge CCLK Referenced from falling edge CCLK
Typical values design only; guaranteed subject production testing. Jitter PCLK frequency MCLK frequency.
LXP730 Multi-Rate Framer
Figure Asynchronous Port Timing
Arrows clocks indicate sampling edge
OSIF SDICK
tBYTE_SPACE
tPER
Waveforms assume ADPI programmed first MDSL channels
SDICK OSOF SDOCK tBYTE_SPACE
SDOCK
tPER
Table Asynchronous Port Timing Specifications (See Figure
Parameter Time next adjacent byte Clock period Delay first transmit byte Delay first receive byte Set-up time Hold time Output delay tBYTE_SPACE tPER Typ1 BIT_CLK
Unit seconds seconds seconds seconds
MCLK SAPCLKDIV BIT_CLK
BIT_CLK-1
Typical figures design only; guaranteed subject production testing.
Multi-Rate Framer LXP730
Figure OSIO Timing
TDATA Frame OSIF OSDICK OSDI BIT_CLK
RDATA Frame OSOF OSDOCK
NOTE:
OSDICK OSDOCK shown transparent setting, both bits Data waveforms exagerated with respect clock show timing details more clearly.
Table OSIO Timing Specifications (See Figure
Parameter Set-up time Hold time Output delay Typ1 Unit
Typical figures design only; guaranteed subject production testing.
LXP730 Multi-Rate Framer
Figure MDSL Interface Input Timing
BITCLK
RDATA
QUATCLK
Sign
Magnitude
Table MDSL Interface Input Timing Specifications (See Figure
Parameter Setup time RDATA Hold time RDATA Typ1 Unit Test Conditions Referenced from falling edge BITCLK Referenced from falling edge BITCLK
Typical values design only; guaranteed subject production testing.
Figure MDSL Interface Output Timing
BITCLK
TDATA
Sign
Magnitude
QUATCLK
Table MDSL Interface Output Timing Specifications (See Figure
Parameter Output delay time TDATA Typ1 Unit Test Conditions Referenced from rising edge BITCLK
Typical values design only; guaranteed subject production testing.
Multi-Rate Framer LXP730
Figure E1/T1 Input Timing
tPWL
tPWH
TCLKI
T1E1I, FRMIN
Table E1/T1 Input Timing Specifications (See Figure
Parameter Setup time T1E1I, FRMIN Hold time T1E1I, FRMIN clock period TCLKI pulse width TCLKI pulse width high Typ1 488, Unit Test Conditions Referenced from falling edge PCLK Referenced from falling edge PCLK
tPWL tPWH
Typical values design only; guaranteed subject production testing.
Figure E1/T1 Output Timing
tPWH
tPWL
TCLK0
T1E10, FRMOUT
LXP730 Multi-Rate Framer
Table E1/T1 Output Timing Specifications (See Figure
Parameter Output delay time T1E10, FRMOUT nominal clock period TCLK0 pulse width TCLK0 pulse width High Typ1 488, Unit Test Conditions Referenced from rising edge CCLK
tPWL tPWH
Typical values design only; guaranteed subject production testing.
Figure Microprocessor Write Cycle Motorola Mode
tASU
Address (A<0:5>)
tDSU
D<0:7>
tDHT
tCPW
tDHW
Table Microprocessor Write Cycle Specifications-Motorola Mode (See Figure
Parameter Address setup time D<0:7> setup time Data-In hold time from Allowable width Write hold time 4/MCLK Typ1 Unit Test Conditions
tASU tDSU tDHT tCPW tDHW
Typical values design only; guaranteed subject production testing.
Multi-Rate Framer LXP730
Figure Microprocessor Read Cycle Motorola Mode
Address (A<0:5>)
D<0:7>
Table Microprocessor Read Cycle Specifications Motorola Mode (See Figure
Parameter D<0:7> valid after D<0:7> keep valid after negation Typ1 4/MCLK Unit Test Conditions
Typical values design only; guaranteed subject production testing.
LXP730 Multi-Rate Framer
Figure Microprocessor Write Cycle Intel Mode
tCPW
tWPW
tASU tWSU tDHT
AD<0:7>
tAPW
Table Microprocessor Write Cycle Specifications-Intel Mode (See Figure
Parameter Address setup time Address latch enable pulse width D<0:7> setup time D<0:7> hold time width width 4/MCLK 4/MCLK Typ1 Unit Referenced from rising edge Referenced from rising edge Test Conditions Referenced from falling edge
tASU tAPW tWSU tDHT tCPW tWPW
Typical values design only; guaranteed subject production testing.
Multi-Rate Framer LXP730
Figure Microprocessor Read Cycle Intel Mode
tASU
tCPW
tRPW tDHT
AD<0:7>
tAPW
Table Microprocessor Read Cycle Specifications-Intel Mode (See Figure
Parameter Address setup time Address latch enable pulse width D<0:7> valid after assertion D<0:7> keep valid after negation Allowed width Allowed width 4/MCLK 4/MCLK Typ1 Unit Referenced from falling edge Referenced from rising edge Test Conditions Referenced from falling edge
tASU
tAPW
tDHT tCPW tRPW
Typical values design only; guaranteed subject production testing.
Table MCLK Frequency Tolerance Specification
Parameter MCLK frequency MCLK duty cycle Typ1 24.832 Unit Test Conditions
Fmclk
Typical values design only; guaranteed subject production testing.
Figure Reset Timing
tRESET RESET
LXP730 Multi-Rate Framer
Table Reset Timing Specifications (See Figure
Parameter Reset Time tRESET Unit Clock periods slowest externally applied clock
Multi-Rate Framer LXP730
Register Definitions
Table LXP730 Register Summary
Address Decimal Address Symbol N_MDSL RSVR1 RSVR2 RSVR3 WANDER FIFO_MISC SLIP_THDL SLIP_THDH VERSION PLLCTL1 PLLCTL2 PLLCTL3 PROG_DIV IDLE PCM1_CFG PCM2_CFG Type Description Number nx64 channels MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration MDSL channel configuration Reserved future Reserved future Reserved future Wander Reduction Register Fifo/Miscellaneous Control Register Slip Buffer Threshold Level Slip Buffer Threshold High Level Version LXP730 ADPLL Control ADPLL Control ADPLL Control MCLK Divide PCM/codec blocks Idle code blocked MDSL slots configurations configuration
LXP730 Multi-Rate Framer
Table LXP730 Register Summary (Continued)
Address Decimal Address Symbol COD_CFG MISC_CTL OVRHD_CFG CRC_ERR_CNT FEBE_ERR_CNT CRC_FEBE_ST MXOH1 MXOH2 MXOH3 MXOH4 MXZ1 MXZ2 MXZ3 MXZ4 MXZ5 MXZ6 DXOH1 DXOH2 DXOH3 DXOH4 DXZ1 DXZ2 DXZ3 DXZ4 DXZ5 DXZ6 RSVR4 RSVR5 INT_EN INT_STATUS Type Description Codec Configuration Miscellaneous Control Overhead mode error counter FEBE error counter FEBE status Overhead Bits Overhead Bits Overhead Bits Overhead Bits Bits Bits Bits Bits Bits Bits Demux Overhead Bits Demux Overhead Bits Demux Overhead Bits Demux Overhead Bits Demux Bits Demux Bits Demux Bits Demux Bits Demux Bits Demux Bits Reserved future Reserved future Interrupt enables Interrupt status flags
Number MDSL Channels Register
Address: Abbreviation: N_MDSL Read/Write
Multi-Rate Framer LXP730
Table Number MDSL Channels
<7:5> <4:0> Name Z_NUM Number<4:0> Default Description Number bits group, valid values Number bits Z_NUM T1/E1, only Z_NUM valid Number MDSL channels, valid values: Number channels Number
5.2.1
MDSL Channel Configuration Registers bytes)
Channel
Address: Abbreviation: Read/Write
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.2
Channel
Address: Abbreviation: Read/Write
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.3
Channel
Address: Abbreviation: Read/Write
LXP730 Multi-Rate Framer
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.4
Channel
Address: Abbreviation: Read/Write
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.5
Channel
Address: Abbreviation: Read/Write
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.6
Channel
Address: Abbreviation: Read/Write
Multi-Rate Framer LXP730
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.7
Channel
Address: Abbreviation: Read/Write
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.8
Channel
Address: Abbreviation: Read/Write
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.9
Channel
Address: Abbreviation: Read/Write
LXP730 Multi-Rate Framer
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.10
Channel
Address: Abbreviation: Read/Write
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.11
Channel
Address: Abbreviation: Read/Write
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.12
Channel
Address: Abbreviation: Read/Write
Multi-Rate Framer LXP730
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.13
Channel
Address: Abbreviation: Read/Write
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.14
Channel
Address: Abbreviation: Read/Write
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.15
Channel
Address: Abbreviation: Read/Write
LXP730 Multi-Rate Framer
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.16
Channel
Address: Abbreviation: Read/Write
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.17
Channel
Address: Abbreviation: Read/Write
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
5.2.18
Channel
Address: Abbreviation: Read/Write
Multi-Rate Framer LXP730
Table Timeslot Channel
<7,6> <5:0> Name CH_CFG Default Description Channel configuration: codec, Idle code, PCM, Async data timeslot, valid values
Reserved Registers bytes)
Addresses: Abbreviation: RSVR1-3
Table Reserved Registers
<7:0> Name RSRV1-3 Default valid read write. Description
Wander Reduction Register
Addresses: Abbreviation: WANDER Read/Write
Table Wander Reduction Register
<7:0> Name W_ENABLE Default Description disable wander reduction circuit; enable wander reduction circuit.
FIFO/Miscellaneous Control Register
Addresses: Abbreviation: FIFO_MISC Read/Write
LXP730 Multi-Rate Framer
Table FIFO/Miscellaneous Control Register
<7:6> Name SAPCLKDIV Default Description Async serial port clock select, MCLK/2, MCLK/4, MCLK/ MCLK/16. Transmit reference sync select control. reference sync selected from interface, reference sync selected from codec interface. Remote Loopback select. Controls scrambling polynomial remote loopback. normal operation, remote loopback. data output enable select. Default value causes FRMSYNC12 codec operation. create output enable signal PDOE usage. PDOE goes high programmed time slots registers. FIFO reset control. elastic store FIFO reset transition. state must active minimum BITCLK periods. FIFO reset control. elastic store FIFO reset transition. state must active minimum BITCLK periods. Fixed 2-bit stuffing mode enable; disable, enable.
TX8KSSEL
REMOTE_LB
PDOE_SEL
DXFIFORXT
MXFIFORXT FIX2BSTUF
Slip Buffer Lower Threshold Register
Address: Abbreviation: SLP_THDL Read/Write
Table Slip Buffer Lower Threshold
<6:0> Name SLP_L_EN SLP_LWR Default Description default, Enable Bits <6:0> Lower Threshold. Must when Stopped (Run/Stop Mode: Lower Threshold Receive Slip Buffer (Default 31-N). Mode: Used.
Multi-Rate Framer LXP730
Slip Buffer Upper Threshold Register
Address: Abbreviation: SLP_THDH Read/Write
Table Slip Buffer Upper Threshold
<6:0> Name SLP_U_EN SLP_UPR Default Description default, Enable Bits <6:0> Upper Threshold. Must when Stopped (Run/Stop Mode: Upper Threshold Receive Slip Buffer (Default 32+N). Mode: Used.
Version Register
Address: Abbreviation: VERSION Read only
Table Version
<7:0> Name Default Version Device. Description
5.9.1
Internal Clock Control Registers bytes)
ADPLL Control
Address: Abbreviation: PLLCTL1 Read/Write
Table ADPLL Control
<7:0> Name CFREQ(17:1 Default Description Center Frequency ADPLL.
LXP730 Multi-Rate Framer
5.9.2
ADPLL Control
Address: Abbreviation: PLLCTL2 Read/Write
Table ADPLL Control
<7:0> Name CFREQ(9:2) Default Description Center Frequency DPPL.
5.9.3
ADPLL Control
Address: Abbreviation: PLLCTL3 Read/Write
<7:6> <4:0> Name CFREQ(1:0) AUTO_RST KLOOP(4:0) Default Description Center Frequency DPPL. ADPLL automatically resets FIFO after lock. Reset. ADPLL Loop Filter Gain Setting.
5.9.4
MCLK Divide
Address: Abbreviation: PROG_DIV Read/Write
Table PROG Divide
<7:0> Name PROG_DIV Default Description PROG Divide, pre-scaler codec Interfaces, PrescaleOut MCLK/(MCLK_DIV
5.10
Programmable Idle Code Byte
Address: Abbreviation: IDLE Read/Write
Multi-Rate Framer LXP730
Table Programmable Idle Code Byte
<7:0> Name IDLE <7:0> Default Description Programmable idle code. This code contains used channel blocking.
5.11
5.11.1
Configuration Registers
PCM1 Configuration
Address: Abbreviation: PCM_CFG1 Read/Write
Table Configuration Bits
Name PCLKMODE Default Description clock, clock. Clock <6:5> PCLKMUX External Pin, PCLK pin-14 (PCM Slave) Internal ADPLL (PCM Master) MCLK divided PROG_DIV register ADPLL output divided PROG_DIV register
FINV SBBP
Data clock edge, sample input data falling edge output data rising edge, sample input rising edge output data falling edge. Frame Sync Pulse polarity, Active low, Active high. Frame Clock Edge, sample frame sync falling edge output rising edge, sample frame sync rising edge output falling edge. Slip buffer ByPass, Slip buffer active, Slip buffer bypassed. Tri-state IDLE code, pass IDLE PCM, Tri-state IDLE.
5.11.2
PCM2 Configuration
Address: Abbreviation: PCM_CFG2 Read/Write
LXP730 Multi-Rate Framer
Table Configuration Bits
<5:0> Name T1E1/PCM T1E1 MAXPCHN Default Description T1E1 selection, mode, T1E1 mode. T1/E1 selection, frame mode, frame mode. Number Channels, values MAXPCHN channels between sync pulses.
5.12
Codec Configuration Register
Address: Abbreviation: COD_CFG Read/Write
Table Codec Configuration
Name Default Codec Clock <7:6> CCLKMUX <0:5> MAXCCHN External Pin, PCLK pin-14 Internal ADPLL MCLK divided PROG_DIV register ADPLL output divided PROG_DIV register Description
Number codec channels, values MAXCCHN codec channels between codec sync pulses.
5.13
5.13.1
Overhead Registers bytes)
Miscellaneous Control
Address: Abbreviation: MISC_CTL Read/Write
Table Miscellaneous Control
Name Default Description Select, outgoing direction based PCLK <7:6> LOS_SEL based codec clock disable LOS; LOSD frame enable LOS, testing; LOSD frame CCLKMODE clock, clock.
Multi-Rate Framer LXP730
Table Miscellaneous Control (Continued)
Name GAP_CLK Z_CTL ASPSEL CCLK_OE PCM_FS_PO Default Description Gapped Clock Select, Enable output gapped receive clock. output always high, Gapped clock out. control, bits registers (Z_NUM only), bits OSIO. ADPI serial port select enable. disabled, enabled. Enabling ADPI disables codec frame syncs Codec Clock Output Enable. disabled, enabled. Frame Sync Position: first frame, last frame.
5.13.2
Overhead Configuration
Address: Abbreviation: OVRHD_CFG Read/Write
Table Overhead Configuration
Name Par/Ser Trans/PreDef CRC_CNT FEBE_CNT SRC_EN DSL_LB RUN/STOP Default Description Overhead Data Mode: external pins, internal register. transparent mode, limited pre-defined mode. CRC-6 error counter mode: reset when read, modulo count. FEBE error counter mode: reset when read, modulo count. Local/Remote Mode, Remote, Local, selects scrambling polynomial. Scrambler Enable, enabled, disabled. Interface Loop Back, disabled, enabled. MDSL framer state machine Deactivated state, MDSL framer state machine Activation state.
5.13.3
Error Counter
Address: Abbreviation: CRC_ERR_CNT Read/Write
LXP730 Multi-Rate Framer
Table Error Counter
<7:0> Name CRC_ERR_ <7:0> Default Description error counter, mode mode OVRHD_CFG register.
5.13.4
FEBE Error Counter
Address: Abbreviation: FEBE_ERR_CNT Read/Write
Table FEBE Error Counter
<7:0> Name FEBE_ERR_ <7:0> Default Description FEBE error counter, mode FEBE mode OVRHD_CFG register.
5.13.5
FEBE Status
Address: Abbreviation: CRC_FEBE_ST Read/Write
Table FEBE Status
<3:1> Name CRC_OVR FEBE_OVR CRCERRINJ MX_LOS DSLACTIVE Default 000b Description when error counter overflowed reset mode. Must write reset. when FEBE error counter overflowed reset mode. Must write reset. Error Injection; when this will injected, then LXP730 will clear this after frame. when occurs, affected LOS_SEL MISC_CTL. Reserved. link active status reports current status.
5.13.6
Overhead Bits
Address: Abbreviation: MXOH1 Read/Write
Multi-Rate Framer LXP730
Table Overhead Bits
<5:2> Name mx8/crc2 mx7/crc1 mx<6:3> mx2/febe mx1/los Default Description Transparent mode/ defined mode. Transparent mode/ defined mode. User definable. Transparent mode/ defined mode. Transparent mode/ defined mode.
5.13.7
Overhead Bits
Address: Abbreviation: MXOH2 Read/Write
Table Overhead Bits
<7:0> Name mx<16:9> Default User definable. Description
5.13.8
Overhead Bits
Address: Abbreviation: MXOH3 Read/Write
Table Overhead Bits
<7:2> Name mx<24:19> mx18/crc4 mx17/crc3 Default User definable. Transparent mode/ defined mode. Transparent mode/ defined mode. Description
5.13.9
Overhead Bits
Address: Abbreviation: MXOH4 Read/Write
LXP730 Multi-Rate Framer
Table Overhead Bits
<7:6> <0:1> Name mx<32,31> mx30/indcr mx29 mx28/crc6 mx27/crc5 mx<25,26> Default User definable. Transparent mode/ defined mode. User definable. Transparent mode/ defined mode. Transparent mode/ defined mode. User definable. Description
5.13.10
Bits
Address: Abbreviation: MXZ1 Read/Write
Table Bits
<7:0> Name mxz<8:1> Default Description User definable when mode.
5.13.11
Bits
Address: Abbreviation: MXZ2 Read/Write
Table Bits
<7:0> Name mxz<16:9> Default Description User definable when mode.
5.13.12
Bits
Address: Abbreviation: MXZ3 Read/Write
Table Bits
<7:0> Name mxz<17:24> Default Description User definable when mode.
Multi-Rate Framer LXP730
5.13.13
Bits
Address: Abbreviation: MXZ4 Read/Write
Table Bits
<7:0> Name mxz<32:25> Default Description User definable when mode.
5.13.14
Bits
Address: Abbreviation: MXZ5 Read/Write
Table Bits
<7:0> Name mxz<40:33> Default Description User definable when mode.
5.13.15
Bits
Address: Abbreviation: MXZ6 Read/Write
Table Bits
<7:0> Name mxz<48:41> Default Description User definable when mode.
5.13.16
Overhead Bits
Address: Abbreviation: DXOH1 Read/Write
LXP730 Multi-Rate Framer
Table Overhead Bits
<5:2> Name dx8/crc2 dx7/crc1 dx<6:3> dx2/febe dx1/los Default 0000b Description Transparent mode/ defined mode. Transparent mode/ defined mode. User definable. Transparent mode/ defined mode. Transparent mode/ defined mode.
5.13.17
Overhead Bits
Address: Abbreviation: DXOH2 Read/Write
Table Overhead Bits
<7:0> Name dx<16:9> Default User definable. Description
5.13.18
Overhead Bits
Address: Abbreviation: DXOH3 Read/Write
Table Overhead Bits
<7:2> Name dx<24:19> dx18/crc4 dx17/crc3 Default User definable. Transparent mode/ defined mode. Transparent mode/ defined mode. Description
5.13.19
Overhead Bits
Address: Abbreviation: DXOH4 Read/Write
Multi-Rate Framer LXP730
Table Overhead Bits
<7:6> <0:1> Name dx<32,31> dx30/indcr dx29 dx28/crc6 dx27/crc5 dx<25,26> Default User definable. Transparent mode/ defined mode. User definable. Transparent mode/ defined mode. Transparent mode/ defined mode. User definable. Description
5.13.20
Bits
Address: Abbreviation: DXZ1 Read/Write
Table Bits
<7:0> Name dxz<8:1> Default Description User definable when mode.
5.13.21
Bits
Address: Abbreviation: DXZ2 Read/Write
Table Bits
<7:0> Name dxz<16:9> Default Description User definable when mode.
5.13.22
Bits
Address: Abbreviation: DXZ3 Read/Write
Table Bits
<7:0> Name dxz<17:24> Default Description User definable when mode.
LXP730 Multi-Rate Framer
5.13.23
Bits
Address: Abbreviation: DXZ4 Read/Write
Table Bits
<7:0> Name dxz<32:25> Default Description User definable when mode.
5.13.24
Bits
Address: Abbreviation: DXZ5 Read/Write
Table Bits
<7:0> Name dxz<40:33> Default Description User definable when mode.
5.13.25
Bits
Address: Abbreviation: DXZ6 Read/Write
Table Bits
<7:0> Name dxz<48:41> Default Description User definable when mode.
5.14
Reserved Registers bytes)
Addresses: Abbreviation: RSVR4
Table Reserved Registers
<7:0> Name RSRV4,5 Default valid read write. Description
Multi-Rate Framer LXP730
5.15
5.15.1
Interrupt Registers bytes)
Interrupt Enables
Address: Abbreviation: INT_EN Read/Write
Table Interrupt Enables
Name LOS_EN CRC_FEBE_E INDCR_EN SLIP_DET_ OHMX_EN OHDX_EN ACTIVE_EN COFA_EN Default Description Loss source interrupt enable (set enable). FEBE interrupt enable. indcr interrupt enable. Slip detect interrupt enable. Overhead interrupt enable. Overhead interrupt enable. ACTIVE interrupt enable. COFA interrupt enable.
5.15.2
Interrupt Status
Address: Abbreviation: INT_STAT Read/Write
Table Interrupt Status
Name CRC_FEBE INDCR SLIP_DET OHMX OHDX ACTIVE COFA Default Description loss source interrupt, when received dx1/los. FEBE interrupt, when error detected febe received dx2/febe. indcr interrupt, when indcr received dx30/indcr. Slip detect interrupt, when slip occurs slip buffer. Overhead interrupt, when frame started allowing write registers before start next frame. Overhead interrupt, when frame ended allowing read registers before next frame. ACTIVE interrupt, when MDSL link COFA interrupt, when change frame position occurs.
LXP730 Multi-Rate Framer
Mechanical Specifications
Figure LQFP Package Specification
Part Number LXP730LE
64-pin Profile Quad Flat Pack Extended Temperature Range (-40 +85°
sides with even number pins
sides with number pins
Inches .002 .053 .007 0.472 .063 .006 .057 .011
Millimeters 0.05 1.35 0.17 12.00
1.60 0.15 1.45 0.27
0.394 BSC1 0.472
10.00 BSC1 12.00 BSC1 10.00 BSC1 0.50 BSC1 0.45 1.00 0.75
0.394 BSC1 0.020 BSC1 0.018 0.030 0.039

Multi-Rate Framer LXP730 multi-purpose Digital Subscriber Line (D

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